1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "X86MCAsmInfo.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "InstPrinter/X86IntelInstPrinter.h"
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Support/Host.h"
27 #include "llvm/Support/TargetRegistry.h"
29 #define GET_REGINFO_MC_DESC
30 #include "X86GenRegisterInfo.inc"
32 #define GET_INSTRINFO_MC_DESC
33 #include "X86GenInstrInfo.inc"
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "X86GenSubtargetInfo.inc"
41 std::string X86_MC::ParseX86Triple(StringRef TT) {
44 if (TheTriple.getArch() == Triple::x86_64)
48 if (TheTriple.getOS() == Triple::NativeClient)
55 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
56 /// specified arguments. If we can't run cpuid on the host, return true.
57 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
58 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
59 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
61 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
62 asm ("movq\t%%rbx, %%rsi\n\t"
64 "xchgq\t%%rbx, %%rsi\n\t"
71 #elif defined(_MSC_VER)
73 __cpuid(registers, value);
80 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
82 asm ("movl\t%%ebx, %%esi\n\t"
84 "xchgl\t%%ebx, %%esi\n\t"
91 #elif defined(_MSC_VER)
96 mov dword ptr [esi],eax
98 mov dword ptr [esi],ebx
100 mov dword ptr [esi],ecx
102 mov dword ptr [esi],edx
110 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
112 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
113 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
114 if (Family == 6 || Family == 0xf) {
116 // Examine extended family ID if family ID is F.
117 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
118 // Examine extended model ID if family ID is 6 or F.
119 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
123 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
124 Triple TheTriple(TT);
125 if (TheTriple.getArch() == Triple::x86_64)
126 return DWARFFlavour::X86_64;
128 if (TheTriple.isOSDarwin())
129 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
130 if (TheTriple.getOS() == Triple::MinGW32 ||
131 TheTriple.getOS() == Triple::Cygwin)
132 // Unsupported by now, just quick fallback
133 return DWARFFlavour::X86_32_Generic;
134 return DWARFFlavour::X86_32_Generic;
137 /// getX86RegNum - This function maps LLVM register identifiers to their X86
138 /// specific numbering, which is used in various places encoding instructions.
139 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
141 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
142 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
143 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
144 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
145 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
147 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
149 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
151 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
154 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
156 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
158 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
160 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
162 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
164 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
166 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
168 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
171 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
172 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
173 return RegNo-X86::ST0;
175 case X86::XMM0: case X86::XMM8:
176 case X86::YMM0: case X86::YMM8: case X86::MM0:
178 case X86::XMM1: case X86::XMM9:
179 case X86::YMM1: case X86::YMM9: case X86::MM1:
181 case X86::XMM2: case X86::XMM10:
182 case X86::YMM2: case X86::YMM10: case X86::MM2:
184 case X86::XMM3: case X86::XMM11:
185 case X86::YMM3: case X86::YMM11: case X86::MM3:
187 case X86::XMM4: case X86::XMM12:
188 case X86::YMM4: case X86::YMM12: case X86::MM4:
190 case X86::XMM5: case X86::XMM13:
191 case X86::YMM5: case X86::YMM13: case X86::MM5:
193 case X86::XMM6: case X86::XMM14:
194 case X86::YMM6: case X86::YMM14: case X86::MM6:
196 case X86::XMM7: case X86::XMM15:
197 case X86::YMM7: case X86::YMM15: case X86::MM7:
200 case X86::ES: return 0;
201 case X86::CS: return 1;
202 case X86::SS: return 2;
203 case X86::DS: return 3;
204 case X86::FS: return 4;
205 case X86::GS: return 5;
207 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
208 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
209 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
210 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
211 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
212 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
213 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
214 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
216 // Pseudo index registers are equivalent to a "none"
217 // scaled index (See Intel Manual 2A, table 2-3)
223 assert((int(RegNo) > 0) && "Unknown physical register!");
228 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
229 // FIXME: TableGen these.
230 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
231 int SEH = X86_MC::getX86RegNum(Reg);
233 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
234 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
235 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
236 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
237 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
238 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
239 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
240 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
241 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
242 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
243 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
244 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
248 MRI->mapLLVMRegToSEHReg(Reg, SEH);
252 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
254 std::string ArchFS = X86_MC::ParseX86Triple(TT);
257 ArchFS = ArchFS + "," + FS.str();
262 std::string CPUName = CPU;
263 if (CPUName.empty()) {
264 #if defined (__x86_64__) || defined(__i386__)
265 CPUName = sys::getHostCPUName();
271 MCSubtargetInfo *X = new MCSubtargetInfo();
272 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
276 static MCInstrInfo *createX86MCInstrInfo() {
277 MCInstrInfo *X = new MCInstrInfo();
278 InitX86MCInstrInfo(X);
282 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
283 Triple TheTriple(TT);
284 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
285 ? X86::RIP // Should have dwarf #16.
286 : X86::EIP; // Should have dwarf #8.
288 MCRegisterInfo *X = new MCRegisterInfo();
289 InitX86MCRegisterInfo(X, RA,
290 X86_MC::getDwarfRegFlavour(TT, false),
291 X86_MC::getDwarfRegFlavour(TT, true));
292 X86_MC::InitLLVM2SEHRegisterMapping(X);
296 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
297 Triple TheTriple(TT);
298 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
301 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
303 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
305 MAI = new X86MCAsmInfoDarwin(TheTriple);
306 } else if (TheTriple.isOSWindows()) {
307 MAI = new X86MCAsmInfoCOFF(TheTriple);
309 MAI = new X86ELFMCAsmInfo(TheTriple);
312 // Initialize initial frame state.
313 // Calculate amount of bytes used for return address storing
314 int stackGrowth = is64Bit ? -8 : -4;
316 // Initial state of the frame pointer is esp+stackGrowth.
317 MachineLocation Dst(MachineLocation::VirtualFP);
318 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
319 MAI->addInitialFrameState(0, Dst, Src);
321 // Add return address to move list
322 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
323 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
324 MAI->addInitialFrameState(0, CSDst, CSSrc);
329 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
330 CodeModel::Model CM) {
331 MCCodeGenInfo *X = new MCCodeGenInfo();
334 bool is64Bit = T.getArch() == Triple::x86_64;
336 if (RM == Reloc::Default) {
337 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
338 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
339 // use static relocation model by default.
340 if (T.isOSDarwin()) {
344 RM = Reloc::DynamicNoPIC;
345 } else if (T.isOSWindows() && is64Bit)
351 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
352 // is defined as a model for code which may be used in static or dynamic
353 // executables but not necessarily a shared library. On X86-32 we just
354 // compile in -static mode, in x86-64 we use PIC.
355 if (RM == Reloc::DynamicNoPIC) {
358 else if (!T.isOSDarwin())
362 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
363 // the Mach-O file format doesn't support it.
364 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
367 // For static codegen, if we're not already set, use Small codegen.
368 if (CM == CodeModel::Default)
369 CM = CodeModel::Small;
370 else if (CM == CodeModel::JITDefault)
371 // 64-bit JIT places everything in the same buffer except external funcs.
372 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
374 X->InitMCCodeGenInfo(RM, CM);
378 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
379 MCContext &Ctx, MCAsmBackend &MAB,
381 MCCodeEmitter *_Emitter,
384 Triple TheTriple(TT);
386 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
387 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
389 if (TheTriple.isOSWindows())
390 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
392 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
395 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
396 unsigned SyntaxVariant,
397 const MCAsmInfo &MAI) {
398 if (SyntaxVariant == 0)
399 return new X86ATTInstPrinter(MAI);
400 if (SyntaxVariant == 1)
401 return new X86IntelInstPrinter(MAI);
405 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
406 return new MCInstrAnalysis(Info);
409 // Force static initialization.
410 extern "C" void LLVMInitializeX86TargetMC() {
411 // Register the MC asm info.
412 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
413 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
415 // Register the MC codegen info.
416 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
417 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
419 // Register the MC instruction info.
420 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
421 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
423 // Register the MC register info.
424 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
425 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
427 // Register the MC subtarget info.
428 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
429 X86_MC::createX86MCSubtargetInfo);
430 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
431 X86_MC::createX86MCSubtargetInfo);
433 // Register the MC instruction analyzer.
434 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
435 createX86MCInstrAnalysis);
436 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
437 createX86MCInstrAnalysis);
439 // Register the code emitter.
440 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
441 createX86MCCodeEmitter);
442 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
443 createX86MCCodeEmitter);
445 // Register the asm backend.
446 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
447 createX86_32AsmBackend);
448 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
449 createX86_64AsmBackend);
451 // Register the object streamer.
452 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
454 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
457 // Register the MCInstPrinter.
458 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
459 createX86MCInstPrinter);
460 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
461 createX86MCInstPrinter);