1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/raw_ostream.h"
30 class X86MCCodeEmitter : public MCCodeEmitter {
31 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
33 const MCInstrInfo &MCII;
34 const MCSubtargetInfo &STI;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
39 : MCII(mcii), STI(sti), Ctx(ctx) {
42 ~X86MCCodeEmitter() {}
44 bool is64BitMode() const {
45 // FIXME: Can tablegen auto-generate this?
46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
49 static unsigned GetX86RegNum(const MCOperand &MO) {
50 return X86_MC::getX86RegNum(MO.getReg());
53 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
54 // 0-7 and the difference between the 2 groups is given by the REX prefix.
55 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
56 // in 1's complement form, example:
58 // ModRM field => XMM9 => 1
59 // VEX.VVVV => XMM9 => ~9
61 // See table 4-35 of Intel AVX Programming Reference for details.
62 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
64 unsigned SrcReg = MI.getOperand(OpNum).getReg();
65 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
66 if (X86II::isX86_64ExtendedReg(SrcReg))
69 // The registers represented through VEX_VVVV should
70 // be encoded in 1's complement form.
71 return (~SrcRegNum) & 0xf;
74 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
79 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
80 raw_ostream &OS) const {
81 // Output the constant in little endian byte order.
82 for (unsigned i = 0; i != Size; ++i) {
83 EmitByte(Val & 255, CurByte, OS);
88 void EmitImmediate(const MCOperand &Disp,
89 unsigned ImmSize, MCFixupKind FixupKind,
90 unsigned &CurByte, raw_ostream &OS,
91 SmallVectorImpl<MCFixup> &Fixups,
92 int ImmOffset = 0) const;
94 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
96 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
97 return RM | (RegOpcode << 3) | (Mod << 6);
100 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
101 unsigned &CurByte, raw_ostream &OS) const {
102 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
105 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
106 unsigned &CurByte, raw_ostream &OS) const {
107 // SIB byte is in the same format as the ModRMByte.
108 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
112 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
113 unsigned RegOpcodeField,
114 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
118 SmallVectorImpl<MCFixup> &Fixups) const;
120 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
121 const MCInst &MI, const MCInstrDesc &Desc,
122 raw_ostream &OS) const;
124 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
125 int MemOperand, const MCInst &MI,
126 raw_ostream &OS) const;
128 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
129 const MCInst &MI, const MCInstrDesc &Desc,
130 raw_ostream &OS) const;
133 } // end anonymous namespace
136 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
137 const MCSubtargetInfo &STI,
139 return new X86MCCodeEmitter(MCII, STI, Ctx);
142 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
143 /// sign-extended field.
144 static bool isDisp8(int Value) {
145 return Value == (signed char)Value;
148 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
149 /// in an instruction with the specified TSFlags.
150 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
151 unsigned Size = X86II::getSizeOfImm(TSFlags);
152 bool isPCRel = X86II::isImmPCRel(TSFlags);
154 return MCFixup::getKindForSize(Size, isPCRel);
157 /// Is32BitMemOperand - Return true if the specified instruction with a memory
158 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
159 /// memory operand. Op specifies the operand # of the memoperand.
160 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
161 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
162 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
164 if ((BaseReg.getReg() != 0 &&
165 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
166 (IndexReg.getReg() != 0 &&
167 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
172 /// StartsWithGlobalOffsetTable - Check if this expression starts with
173 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
174 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
175 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
176 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
177 /// of a binary expression.
178 enum GlobalOffsetTableExprKind {
183 static GlobalOffsetTableExprKind
184 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
185 const MCExpr *RHS = 0;
186 if (Expr->getKind() == MCExpr::Binary) {
187 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
192 if (Expr->getKind() != MCExpr::SymbolRef)
195 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
196 const MCSymbol &S = Ref->getSymbol();
197 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
199 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
204 void X86MCCodeEmitter::
205 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
206 unsigned &CurByte, raw_ostream &OS,
207 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
208 const MCExpr *Expr = NULL;
209 if (DispOp.isImm()) {
210 // If this is a simple integer displacement that doesn't require a
211 // relocation, emit it now.
212 if (FixupKind != FK_PCRel_1 &&
213 FixupKind != FK_PCRel_2 &&
214 FixupKind != FK_PCRel_4) {
215 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
218 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
220 Expr = DispOp.getExpr();
223 // If we have an immoffset, add it to the expression.
224 if ((FixupKind == FK_Data_4 ||
225 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
226 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
227 if (Kind != GOT_None) {
228 assert(ImmOffset == 0);
230 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
231 if (Kind == GOT_Normal)
236 // If the fixup is pc-relative, we need to bias the value to be relative to
237 // the start of the field, not the end of the field.
238 if (FixupKind == FK_PCRel_4 ||
239 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
240 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
242 if (FixupKind == FK_PCRel_2)
244 if (FixupKind == FK_PCRel_1)
248 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
251 // Emit a symbolic constant as a fixup and 4 zeros.
252 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
253 EmitConstant(0, Size, CurByte, OS);
256 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
257 unsigned RegOpcodeField,
258 uint64_t TSFlags, unsigned &CurByte,
260 SmallVectorImpl<MCFixup> &Fixups) const{
261 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
262 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
263 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
264 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
265 unsigned BaseReg = Base.getReg();
267 // Handle %rip relative addressing.
268 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
269 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
270 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
271 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
273 unsigned FixupKind = X86::reloc_riprel_4byte;
275 // movq loads are handled with a special relocation form which allows the
276 // linker to eliminate some loads for GOT references which end up in the
277 // same linkage unit.
278 if (MI.getOpcode() == X86::MOV64rm)
279 FixupKind = X86::reloc_riprel_4byte_movq_load;
281 // rip-relative addressing is actually relative to the *next* instruction.
282 // Since an immediate can follow the mod/rm byte for an instruction, this
283 // means that we need to bias the immediate field of the instruction with
284 // the size of the immediate field. If we have this case, add it into the
285 // expression to emit.
286 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
288 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
289 CurByte, OS, Fixups, -ImmSize);
293 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
295 // Determine whether a SIB byte is needed.
296 // If no BaseReg, issue a RIP relative instruction only if the MCE can
297 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
298 // 2-7) and absolute references.
300 if (// The SIB byte must be used if there is an index register.
301 IndexReg.getReg() == 0 &&
302 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
303 // encode to an R/M value of 4, which indicates that a SIB byte is
305 BaseRegNo != N86::ESP &&
306 // If there is no base register and we're in 64-bit mode, we need a SIB
307 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
308 (!is64BitMode() || BaseReg != 0)) {
310 if (BaseReg == 0) { // [disp32] in X86-32 mode
311 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
312 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
316 // If the base is not EBP/ESP and there is no displacement, use simple
317 // indirect register encoding, this handles addresses like [EAX]. The
318 // encoding for [EBP] with no displacement means [disp32] so we handle it
319 // by emitting a displacement of 0 below.
320 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
321 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
325 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
326 if (Disp.isImm() && isDisp8(Disp.getImm())) {
327 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
328 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
332 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
333 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
334 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
339 // We need a SIB byte, so start by outputting the ModR/M byte first
340 assert(IndexReg.getReg() != X86::ESP &&
341 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
343 bool ForceDisp32 = false;
344 bool ForceDisp8 = false;
346 // If there is no base register, we emit the special case SIB byte with
347 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
348 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
350 } else if (!Disp.isImm()) {
351 // Emit the normal disp32 encoding.
352 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
354 } else if (Disp.getImm() == 0 &&
355 // Base reg can't be anything that ends up with '5' as the base
356 // reg, it is the magic [*] nomenclature that indicates no base.
357 BaseRegNo != N86::EBP) {
358 // Emit no displacement ModR/M byte
359 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
360 } else if (isDisp8(Disp.getImm())) {
361 // Emit the disp8 encoding.
362 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
363 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
365 // Emit the normal disp32 encoding.
366 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
369 // Calculate what the SS field value should be...
370 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
371 unsigned SS = SSTable[Scale.getImm()];
374 // Handle the SIB byte for the case where there is no base, see Intel
375 // Manual 2A, table 2-7. The displacement has already been output.
377 if (IndexReg.getReg())
378 IndexRegNo = GetX86RegNum(IndexReg);
379 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
381 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
384 if (IndexReg.getReg())
385 IndexRegNo = GetX86RegNum(IndexReg);
387 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
388 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
391 // Do we need to output a displacement?
393 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
394 else if (ForceDisp32 || Disp.getImm() != 0)
395 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
399 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
401 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
402 int MemOperand, const MCInst &MI,
403 const MCInstrDesc &Desc,
404 raw_ostream &OS) const {
405 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
406 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
408 // VEX_R: opcode externsion equivalent to REX.R in
409 // 1's complement (inverted) form
411 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
412 // 0: Same as REX_R=1 (64 bit mode only)
414 unsigned char VEX_R = 0x1;
416 // VEX_X: equivalent to REX.X, only used when a
417 // register is used for index in SIB Byte.
419 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
420 // 0: Same as REX.X=1 (64-bit mode only)
421 unsigned char VEX_X = 0x1;
425 // 1: Same as REX_B=0 (ignored in 32-bit mode)
426 // 0: Same as REX_B=1 (64 bit mode only)
428 unsigned char VEX_B = 0x1;
430 // VEX_W: opcode specific (use like REX.W, or used for
431 // opcode extension, or ignored, depending on the opcode byte)
432 unsigned char VEX_W = 0;
434 // XOP_W: opcode specific, same bit as VEX_W, but used to
435 // swap operand 3 and 4 for FMA4 and XOP instructions
436 unsigned char XOP_W = 0;
438 // VEX_5M (VEX m-mmmmm field):
440 // 0b00000: Reserved for future use
441 // 0b00001: implied 0F leading opcode
442 // 0b00010: implied 0F 38 leading opcode bytes
443 // 0b00011: implied 0F 3A leading opcode bytes
444 // 0b00100-0b11111: Reserved for future use
446 unsigned char VEX_5M = 0x1;
448 // VEX_4V (VEX vvvv field): a register specifier
449 // (in 1's complement form) or 1111 if unused.
450 unsigned char VEX_4V = 0xf;
452 // VEX_L (Vector Length):
454 // 0: scalar or 128-bit vector
457 unsigned char VEX_L = 0;
459 // VEX_PP: opcode extension providing equivalent
460 // functionality of a SIMD prefix
467 unsigned char VEX_PP = 0;
469 // Encode the operand size opcode prefix as needed.
470 if (TSFlags & X86II::OpSize)
473 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
476 if ((TSFlags >> X86II::VEXShift) & X86II::XOP_W)
479 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
482 switch (TSFlags & X86II::Op0Mask) {
483 default: assert(0 && "Invalid prefix!");
484 case X86II::T8: // 0F 38
487 case X86II::TA: // 0F 3A
490 case X86II::T8XS: // F3 0F 38
494 case X86II::T8XD: // F2 0F 38
498 case X86II::TAXD: // F2 0F 3A
502 case X86II::XS: // F3 0F
505 case X86II::XD: // F2 0F
508 case X86II::A6: // Bypass: Not used by VEX
509 case X86II::A7: // Bypass: Not used by VEX
510 case X86II::TB: // Bypass: Not used by VEX
515 // Set the vector length to 256-bit if YMM0-YMM15 is used
516 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
517 if (!MI.getOperand(i).isReg())
519 unsigned SrcReg = MI.getOperand(i).getReg();
520 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
524 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
526 switch (TSFlags & X86II::FormMask) {
527 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
528 case X86II::MRMDestMem: {
529 // MRMDestMem instructions forms:
530 // MemAddr, src1(ModR/M)
531 // MemAddr, src1(VEX_4V), src2(ModR/M)
532 // MemAddr, src1(ModR/M), imm8
534 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
536 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
539 CurOp = X86::AddrNumOperands;
541 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
543 const MCOperand &MO = MI.getOperand(CurOp);
544 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
548 case X86II::MRMSrcMem:
549 // MRMSrcMem instructions forms:
550 // src1(ModR/M), MemAddr
551 // src1(ModR/M), src2(VEX_4V), MemAddr
552 // src1(ModR/M), MemAddr, imm8
553 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
556 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
557 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
558 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
562 VEX_4V = getVEXRegisterEncoding(MI, 1);
564 if (X86II::isX86_64ExtendedReg(
565 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
567 if (X86II::isX86_64ExtendedReg(
568 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
572 VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1);
574 case X86II::MRM0m: case X86II::MRM1m:
575 case X86II::MRM2m: case X86II::MRM3m:
576 case X86II::MRM4m: case X86II::MRM5m:
577 case X86II::MRM6m: case X86II::MRM7m: {
578 // MRM[0-9]m instructions forms:
580 // src1(VEX_4V), MemAddr
582 VEX_4V = getVEXRegisterEncoding(MI, 0);
584 if (X86II::isX86_64ExtendedReg(
585 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
587 if (X86II::isX86_64ExtendedReg(
588 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
592 case X86II::MRMSrcReg:
593 // MRMSrcReg instructions forms:
594 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
595 // dst(ModR/M), src1(ModR/M)
596 // dst(ModR/M), src1(ModR/M), imm8
598 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
603 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
604 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
608 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
610 case X86II::MRMDestReg:
611 // MRMDestReg instructions forms:
612 // dst(ModR/M), src(ModR/M)
613 // dst(ModR/M), src(ModR/M), imm8
614 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
616 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
619 case X86II::MRM0r: case X86II::MRM1r:
620 case X86II::MRM2r: case X86II::MRM3r:
621 case X86II::MRM4r: case X86II::MRM5r:
622 case X86II::MRM6r: case X86II::MRM7r:
623 // MRM0r-MRM7r instructions forms:
624 // dst(VEX_4V), src(ModR/M), imm8
625 VEX_4V = getVEXRegisterEncoding(MI, 0);
626 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
633 // Emit segment override opcode prefix as needed.
634 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
636 // VEX opcode prefix can have 2 or 3 bytes
639 // +-----+ +--------------+ +-------------------+
640 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
641 // +-----+ +--------------+ +-------------------+
643 // +-----+ +-------------------+
644 // | C5h | | R | vvvv | L | pp |
645 // +-----+ +-------------------+
647 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
649 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
650 EmitByte(0xC5, CurByte, OS);
651 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
656 EmitByte(0xC4, CurByte, OS);
657 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
658 EmitByte(LastByte | ((VEX_W | XOP_W) << 7), CurByte, OS);
661 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
662 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
663 /// size, and 3) use of X86-64 extended registers.
664 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
665 const MCInstrDesc &Desc) {
667 if (TSFlags & X86II::REX_W)
668 REX |= 1 << 3; // set REX.W
670 if (MI.getNumOperands() == 0) return REX;
672 unsigned NumOps = MI.getNumOperands();
673 // FIXME: MCInst should explicitize the two-addrness.
674 bool isTwoAddr = NumOps > 1 &&
675 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
677 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
678 unsigned i = isTwoAddr ? 1 : 0;
679 for (; i != NumOps; ++i) {
680 const MCOperand &MO = MI.getOperand(i);
681 if (!MO.isReg()) continue;
682 unsigned Reg = MO.getReg();
683 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
684 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
685 // that returns non-zero.
686 REX |= 0x40; // REX fixed encoding prefix
690 switch (TSFlags & X86II::FormMask) {
691 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
692 case X86II::MRMSrcReg:
693 if (MI.getOperand(0).isReg() &&
694 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
695 REX |= 1 << 2; // set REX.R
696 i = isTwoAddr ? 2 : 1;
697 for (; i != NumOps; ++i) {
698 const MCOperand &MO = MI.getOperand(i);
699 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
700 REX |= 1 << 0; // set REX.B
703 case X86II::MRMSrcMem: {
704 if (MI.getOperand(0).isReg() &&
705 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
706 REX |= 1 << 2; // set REX.R
708 i = isTwoAddr ? 2 : 1;
709 for (; i != NumOps; ++i) {
710 const MCOperand &MO = MI.getOperand(i);
712 if (X86II::isX86_64ExtendedReg(MO.getReg()))
713 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
719 case X86II::MRM0m: case X86II::MRM1m:
720 case X86II::MRM2m: case X86II::MRM3m:
721 case X86II::MRM4m: case X86II::MRM5m:
722 case X86II::MRM6m: case X86II::MRM7m:
723 case X86II::MRMDestMem: {
724 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
725 i = isTwoAddr ? 1 : 0;
726 if (NumOps > e && MI.getOperand(e).isReg() &&
727 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
728 REX |= 1 << 2; // set REX.R
730 for (; i != e; ++i) {
731 const MCOperand &MO = MI.getOperand(i);
733 if (X86II::isX86_64ExtendedReg(MO.getReg()))
734 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
741 if (MI.getOperand(0).isReg() &&
742 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
743 REX |= 1 << 0; // set REX.B
744 i = isTwoAddr ? 2 : 1;
745 for (unsigned e = NumOps; i != e; ++i) {
746 const MCOperand &MO = MI.getOperand(i);
747 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
748 REX |= 1 << 2; // set REX.R
755 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
756 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
757 unsigned &CurByte, int MemOperand,
759 raw_ostream &OS) const {
760 switch (TSFlags & X86II::SegOvrMask) {
761 default: assert(0 && "Invalid segment!");
763 // No segment override, check for explicit one on memory operand.
764 if (MemOperand != -1) { // If the instruction has a memory operand.
765 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
766 default: assert(0 && "Unknown segment register!");
768 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
769 case X86::SS: EmitByte(0x36, CurByte, OS); break;
770 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
771 case X86::ES: EmitByte(0x26, CurByte, OS); break;
772 case X86::FS: EmitByte(0x64, CurByte, OS); break;
773 case X86::GS: EmitByte(0x65, CurByte, OS); break;
778 EmitByte(0x64, CurByte, OS);
781 EmitByte(0x65, CurByte, OS);
786 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
788 /// MemOperand is the operand # of the start of a memory operand if present. If
789 /// Not present, it is -1.
790 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
791 int MemOperand, const MCInst &MI,
792 const MCInstrDesc &Desc,
793 raw_ostream &OS) const {
795 // Emit the lock opcode prefix as needed.
796 if (TSFlags & X86II::LOCK)
797 EmitByte(0xF0, CurByte, OS);
799 // Emit segment override opcode prefix as needed.
800 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
802 // Emit the repeat opcode prefix as needed.
803 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
804 EmitByte(0xF3, CurByte, OS);
806 // Emit the address size opcode prefix as needed.
807 if ((TSFlags & X86II::AdSize) ||
808 (MemOperand != -1 && is64BitMode() && Is32BitMemOperand(MI, MemOperand)))
809 EmitByte(0x67, CurByte, OS);
811 // Emit the operand size opcode prefix as needed.
812 if (TSFlags & X86II::OpSize)
813 EmitByte(0x66, CurByte, OS);
815 bool Need0FPrefix = false;
816 switch (TSFlags & X86II::Op0Mask) {
817 default: assert(0 && "Invalid prefix!");
818 case 0: break; // No prefix!
819 case X86II::REP: break; // already handled.
820 case X86II::TB: // Two-byte opcode prefix
821 case X86II::T8: // 0F 38
822 case X86II::TA: // 0F 3A
823 case X86II::A6: // 0F A6
824 case X86II::A7: // 0F A7
827 case X86II::T8XS: // F3 0F 38
828 EmitByte(0xF3, CurByte, OS);
831 case X86II::T8XD: // F2 0F 38
832 EmitByte(0xF2, CurByte, OS);
835 case X86II::TAXD: // F2 0F 3A
836 EmitByte(0xF2, CurByte, OS);
839 case X86II::XS: // F3 0F
840 EmitByte(0xF3, CurByte, OS);
843 case X86II::XD: // F2 0F
844 EmitByte(0xF2, CurByte, OS);
847 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
848 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
849 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
850 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
851 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
852 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
853 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
854 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
857 // Handle REX prefix.
858 // FIXME: Can this come before F2 etc to simplify emission?
860 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
861 EmitByte(0x40 | REX, CurByte, OS);
864 // 0x0F escape code must be emitted just before the opcode.
866 EmitByte(0x0F, CurByte, OS);
868 // FIXME: Pull this up into previous switch if REX can be moved earlier.
869 switch (TSFlags & X86II::Op0Mask) {
870 case X86II::T8XS: // F3 0F 38
871 case X86II::T8XD: // F2 0F 38
872 case X86II::T8: // 0F 38
873 EmitByte(0x38, CurByte, OS);
875 case X86II::TAXD: // F2 0F 3A
876 case X86II::TA: // 0F 3A
877 EmitByte(0x3A, CurByte, OS);
879 case X86II::A6: // 0F A6
880 EmitByte(0xA6, CurByte, OS);
882 case X86II::A7: // 0F A7
883 EmitByte(0xA7, CurByte, OS);
888 void X86MCCodeEmitter::
889 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
890 SmallVectorImpl<MCFixup> &Fixups) const {
891 unsigned Opcode = MI.getOpcode();
892 const MCInstrDesc &Desc = MCII.get(Opcode);
893 uint64_t TSFlags = Desc.TSFlags;
895 // Pseudo instructions don't get encoded.
896 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
899 // If this is a two-address instruction, skip one of the register operands.
900 // FIXME: This should be handled during MCInst lowering.
901 unsigned NumOps = Desc.getNumOperands();
903 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1)
905 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0)
906 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
909 // Keep track of the current byte being emitted.
910 unsigned CurByte = 0;
912 // Is this instruction encoded using the AVX VEX prefix?
913 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX;
915 // It uses the VEX.VVVV field?
916 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
917 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
918 bool HasXOP_W = (TSFlags >> X86II::VEXShift) & X86II::XOP_W;
919 unsigned XOP_W_I8IMMOperand = 2;
921 // Determine where the memory operand starts, if present.
922 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
923 if (MemoryOperand != -1) MemoryOperand += CurOp;
926 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
928 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
930 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
932 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
933 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
935 unsigned SrcRegNum = 0;
936 switch (TSFlags & X86II::FormMask) {
937 case X86II::MRMInitReg:
938 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
939 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
940 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
942 assert(0 && "Pseudo instruction shouldn't be emitted");
944 EmitByte(BaseOpcode, CurByte, OS);
946 case X86II::RawFrmImm8:
947 EmitByte(BaseOpcode, CurByte, OS);
948 EmitImmediate(MI.getOperand(CurOp++),
949 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
950 CurByte, OS, Fixups);
951 EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups);
953 case X86II::RawFrmImm16:
954 EmitByte(BaseOpcode, CurByte, OS);
955 EmitImmediate(MI.getOperand(CurOp++),
956 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
957 CurByte, OS, Fixups);
958 EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups);
961 case X86II::AddRegFrm:
962 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
965 case X86II::MRMDestReg:
966 EmitByte(BaseOpcode, CurByte, OS);
967 EmitRegModRMByte(MI.getOperand(CurOp),
968 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
972 case X86II::MRMDestMem:
973 EmitByte(BaseOpcode, CurByte, OS);
974 SrcRegNum = CurOp + X86::AddrNumOperands;
976 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
979 EmitMemModRMByte(MI, CurOp,
980 GetX86RegNum(MI.getOperand(SrcRegNum)),
981 TSFlags, CurByte, OS, Fixups);
982 CurOp = SrcRegNum + 1;
985 case X86II::MRMSrcReg:
986 EmitByte(BaseOpcode, CurByte, OS);
987 SrcRegNum = CurOp + 1;
989 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
992 if(HasXOP_W) // Skip 2nd src (which is encoded in I8IMM)
995 EmitRegModRMByte(MI.getOperand(SrcRegNum),
996 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
998 // 2 operands skipped with HasXOP_W, comensate accordingly
999 CurOp = HasXOP_W ? SrcRegNum : SrcRegNum + 1;
1004 case X86II::MRMSrcMem: {
1005 int AddrOperands = X86::AddrNumOperands;
1006 unsigned FirstMemOp = CurOp+1;
1009 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1011 if(HasXOP_W) // Skip second register source (encoded in I8IMM)
1014 EmitByte(BaseOpcode, CurByte, OS);
1016 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1017 TSFlags, CurByte, OS, Fixups);
1018 CurOp += AddrOperands + 1;
1024 case X86II::MRM0r: case X86II::MRM1r:
1025 case X86II::MRM2r: case X86II::MRM3r:
1026 case X86II::MRM4r: case X86II::MRM5r:
1027 case X86II::MRM6r: case X86II::MRM7r:
1028 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1030 EmitByte(BaseOpcode, CurByte, OS);
1031 EmitRegModRMByte(MI.getOperand(CurOp++),
1032 (TSFlags & X86II::FormMask)-X86II::MRM0r,
1035 case X86II::MRM0m: case X86II::MRM1m:
1036 case X86II::MRM2m: case X86II::MRM3m:
1037 case X86II::MRM4m: case X86II::MRM5m:
1038 case X86II::MRM6m: case X86II::MRM7m:
1039 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1041 EmitByte(BaseOpcode, CurByte, OS);
1042 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
1043 TSFlags, CurByte, OS, Fixups);
1044 CurOp += X86::AddrNumOperands;
1047 EmitByte(BaseOpcode, CurByte, OS);
1048 EmitByte(0xC1, CurByte, OS);
1051 EmitByte(BaseOpcode, CurByte, OS);
1052 EmitByte(0xC2, CurByte, OS);
1055 EmitByte(BaseOpcode, CurByte, OS);
1056 EmitByte(0xC3, CurByte, OS);
1059 EmitByte(BaseOpcode, CurByte, OS);
1060 EmitByte(0xC4, CurByte, OS);
1063 EmitByte(BaseOpcode, CurByte, OS);
1064 EmitByte(0xC8, CurByte, OS);
1067 EmitByte(BaseOpcode, CurByte, OS);
1068 EmitByte(0xC9, CurByte, OS);
1071 EmitByte(BaseOpcode, CurByte, OS);
1072 EmitByte(0xE8, CurByte, OS);
1075 EmitByte(BaseOpcode, CurByte, OS);
1076 EmitByte(0xF0, CurByte, OS);
1079 EmitByte(BaseOpcode, CurByte, OS);
1080 EmitByte(0xF8, CurByte, OS);
1083 EmitByte(BaseOpcode, CurByte, OS);
1084 EmitByte(0xF9, CurByte, OS);
1087 EmitByte(BaseOpcode, CurByte, OS);
1088 EmitByte(0xD0, CurByte, OS);
1091 EmitByte(BaseOpcode, CurByte, OS);
1092 EmitByte(0xD1, CurByte, OS);
1096 // If there is a remaining operand, it must be a trailing immediate. Emit it
1097 // according to the right size for the instruction.
1098 if (CurOp != NumOps) {
1099 // The last source register of a 4 operand instruction in AVX is encoded
1100 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
1101 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1102 const MCOperand &MO = MI.getOperand(HasXOP_W ? XOP_W_I8IMMOperand
1105 bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg());
1106 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
1107 RegNum |= GetX86RegNum(MO) << 4;
1108 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
1112 // FIXME: Is there a better way to know that we need a signed relocation?
1113 if (MI.getOpcode() == X86::ADD64ri32 ||
1114 MI.getOpcode() == X86::MOV64ri32 ||
1115 MI.getOpcode() == X86::MOV64mi32 ||
1116 MI.getOpcode() == X86::PUSH64i32)
1117 FixupKind = X86::reloc_signed_4byte;
1119 FixupKind = getImmFixupKind(TSFlags);
1120 EmitImmediate(MI.getOperand(CurOp++),
1121 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1122 CurByte, OS, Fixups);
1126 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1127 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1131 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1132 errs() << "Cannot encode all operands of: ";