1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/raw_ostream.h"
30 class X86MCCodeEmitter : public MCCodeEmitter {
31 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
33 const MCInstrInfo &MCII;
34 const MCSubtargetInfo &STI;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
39 : MCII(mcii), STI(sti), Ctx(ctx) {
42 ~X86MCCodeEmitter() {}
44 bool is64BitMode() const {
45 // FIXME: Can tablegen auto-generate this?
46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
49 bool is32BitMode() const {
50 // FIXME: Can tablegen auto-generate this?
51 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
54 static unsigned GetX86RegNum(const MCOperand &MO) {
55 return X86_MC::getX86RegNum(MO.getReg());
58 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
59 // 0-7 and the difference between the 2 groups is given by the REX prefix.
60 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
61 // in 1's complement form, example:
63 // ModRM field => XMM9 => 1
64 // VEX.VVVV => XMM9 => ~9
66 // See table 4-35 of Intel AVX Programming Reference for details.
67 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
69 unsigned SrcReg = MI.getOperand(OpNum).getReg();
70 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
71 if (X86II::isX86_64ExtendedReg(SrcReg))
74 // The registers represented through VEX_VVVV should
75 // be encoded in 1's complement form.
76 return (~SrcRegNum) & 0xf;
79 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
84 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
85 raw_ostream &OS) const {
86 // Output the constant in little endian byte order.
87 for (unsigned i = 0; i != Size; ++i) {
88 EmitByte(Val & 255, CurByte, OS);
93 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
94 unsigned ImmSize, MCFixupKind FixupKind,
95 unsigned &CurByte, raw_ostream &OS,
96 SmallVectorImpl<MCFixup> &Fixups,
97 int ImmOffset = 0) const;
99 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
101 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
102 return RM | (RegOpcode << 3) | (Mod << 6);
105 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
106 unsigned &CurByte, raw_ostream &OS) const {
107 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
110 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
111 unsigned &CurByte, raw_ostream &OS) const {
112 // SIB byte is in the same format as the ModRMByte.
113 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
117 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
118 unsigned RegOpcodeField,
119 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
123 SmallVectorImpl<MCFixup> &Fixups) const;
125 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
126 const MCInst &MI, const MCInstrDesc &Desc,
127 raw_ostream &OS) const;
129 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
130 int MemOperand, const MCInst &MI,
131 raw_ostream &OS) const;
133 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
134 const MCInst &MI, const MCInstrDesc &Desc,
135 raw_ostream &OS) const;
138 } // end anonymous namespace
141 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
142 const MCSubtargetInfo &STI,
144 return new X86MCCodeEmitter(MCII, STI, Ctx);
147 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
148 /// sign-extended field.
149 static bool isDisp8(int Value) {
150 return Value == (signed char)Value;
153 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
154 /// in an instruction with the specified TSFlags.
155 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
156 unsigned Size = X86II::getSizeOfImm(TSFlags);
157 bool isPCRel = X86II::isImmPCRel(TSFlags);
159 return MCFixup::getKindForSize(Size, isPCRel);
162 /// Is32BitMemOperand - Return true if the specified instruction has
163 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
164 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
165 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
166 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
168 if ((BaseReg.getReg() != 0 &&
169 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
170 (IndexReg.getReg() != 0 &&
171 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
176 /// Is64BitMemOperand - Return true if the specified instruction has
177 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
179 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
180 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
181 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
183 if ((BaseReg.getReg() != 0 &&
184 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
185 (IndexReg.getReg() != 0 &&
186 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
192 /// Is16BitMemOperand - Return true if the specified instruction has
193 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
194 static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) {
195 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
196 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
198 if ((BaseReg.getReg() != 0 &&
199 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
200 (IndexReg.getReg() != 0 &&
201 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
206 /// StartsWithGlobalOffsetTable - Check if this expression starts with
207 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
208 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
209 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
210 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
211 /// of a binary expression.
212 enum GlobalOffsetTableExprKind {
217 static GlobalOffsetTableExprKind
218 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
219 const MCExpr *RHS = 0;
220 if (Expr->getKind() == MCExpr::Binary) {
221 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
226 if (Expr->getKind() != MCExpr::SymbolRef)
229 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
230 const MCSymbol &S = Ref->getSymbol();
231 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
233 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
238 void X86MCCodeEmitter::
239 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
240 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
241 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
242 const MCExpr *Expr = NULL;
243 if (DispOp.isImm()) {
244 // If this is a simple integer displacement that doesn't require a
245 // relocation, emit it now.
246 if (FixupKind != FK_PCRel_1 &&
247 FixupKind != FK_PCRel_2 &&
248 FixupKind != FK_PCRel_4) {
249 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
252 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
254 Expr = DispOp.getExpr();
257 // If we have an immoffset, add it to the expression.
258 if ((FixupKind == FK_Data_4 ||
259 FixupKind == FK_Data_8 ||
260 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
261 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
262 if (Kind != GOT_None) {
263 assert(ImmOffset == 0);
265 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
266 if (Kind == GOT_Normal)
268 } else if (Expr->getKind() == MCExpr::SymbolRef) {
269 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
270 if (Ref->getKind() == MCSymbolRefExpr::VK_SECREL) {
271 FixupKind = MCFixupKind(FK_SecRel_4);
276 // If the fixup is pc-relative, we need to bias the value to be relative to
277 // the start of the field, not the end of the field.
278 if (FixupKind == FK_PCRel_4 ||
279 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
280 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
282 if (FixupKind == FK_PCRel_2)
284 if (FixupKind == FK_PCRel_1)
288 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
291 // Emit a symbolic constant as a fixup and 4 zeros.
292 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
293 EmitConstant(0, Size, CurByte, OS);
296 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
297 unsigned RegOpcodeField,
298 uint64_t TSFlags, unsigned &CurByte,
300 SmallVectorImpl<MCFixup> &Fixups) const{
301 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
302 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
303 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
304 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
305 unsigned BaseReg = Base.getReg();
307 // Handle %rip relative addressing.
308 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
309 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
310 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
311 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
313 unsigned FixupKind = X86::reloc_riprel_4byte;
315 // movq loads are handled with a special relocation form which allows the
316 // linker to eliminate some loads for GOT references which end up in the
317 // same linkage unit.
318 if (MI.getOpcode() == X86::MOV64rm)
319 FixupKind = X86::reloc_riprel_4byte_movq_load;
321 // rip-relative addressing is actually relative to the *next* instruction.
322 // Since an immediate can follow the mod/rm byte for an instruction, this
323 // means that we need to bias the immediate field of the instruction with
324 // the size of the immediate field. If we have this case, add it into the
325 // expression to emit.
326 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
328 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
329 CurByte, OS, Fixups, -ImmSize);
333 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
335 // Determine whether a SIB byte is needed.
336 // If no BaseReg, issue a RIP relative instruction only if the MCE can
337 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
338 // 2-7) and absolute references.
340 if (// The SIB byte must be used if there is an index register.
341 IndexReg.getReg() == 0 &&
342 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
343 // encode to an R/M value of 4, which indicates that a SIB byte is
345 BaseRegNo != N86::ESP &&
346 // If there is no base register and we're in 64-bit mode, we need a SIB
347 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
348 (!is64BitMode() || BaseReg != 0)) {
350 if (BaseReg == 0) { // [disp32] in X86-32 mode
351 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
352 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
356 // If the base is not EBP/ESP and there is no displacement, use simple
357 // indirect register encoding, this handles addresses like [EAX]. The
358 // encoding for [EBP] with no displacement means [disp32] so we handle it
359 // by emitting a displacement of 0 below.
360 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
361 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
365 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
366 if (Disp.isImm() && isDisp8(Disp.getImm())) {
367 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
368 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
372 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
373 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
374 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
379 // We need a SIB byte, so start by outputting the ModR/M byte first
380 assert(IndexReg.getReg() != X86::ESP &&
381 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
383 bool ForceDisp32 = false;
384 bool ForceDisp8 = false;
386 // If there is no base register, we emit the special case SIB byte with
387 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
388 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
390 } else if (!Disp.isImm()) {
391 // Emit the normal disp32 encoding.
392 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
394 } else if (Disp.getImm() == 0 &&
395 // Base reg can't be anything that ends up with '5' as the base
396 // reg, it is the magic [*] nomenclature that indicates no base.
397 BaseRegNo != N86::EBP) {
398 // Emit no displacement ModR/M byte
399 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
400 } else if (isDisp8(Disp.getImm())) {
401 // Emit the disp8 encoding.
402 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
403 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
405 // Emit the normal disp32 encoding.
406 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
409 // Calculate what the SS field value should be...
410 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
411 unsigned SS = SSTable[Scale.getImm()];
414 // Handle the SIB byte for the case where there is no base, see Intel
415 // Manual 2A, table 2-7. The displacement has already been output.
417 if (IndexReg.getReg())
418 IndexRegNo = GetX86RegNum(IndexReg);
419 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
421 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
424 if (IndexReg.getReg())
425 IndexRegNo = GetX86RegNum(IndexReg);
427 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
428 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
431 // Do we need to output a displacement?
433 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
434 else if (ForceDisp32 || Disp.getImm() != 0)
435 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
436 CurByte, OS, Fixups);
439 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
441 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
442 int MemOperand, const MCInst &MI,
443 const MCInstrDesc &Desc,
444 raw_ostream &OS) const {
445 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
446 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
448 // VEX_R: opcode externsion equivalent to REX.R in
449 // 1's complement (inverted) form
451 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
452 // 0: Same as REX_R=1 (64 bit mode only)
454 unsigned char VEX_R = 0x1;
456 // VEX_X: equivalent to REX.X, only used when a
457 // register is used for index in SIB Byte.
459 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
460 // 0: Same as REX.X=1 (64-bit mode only)
461 unsigned char VEX_X = 0x1;
465 // 1: Same as REX_B=0 (ignored in 32-bit mode)
466 // 0: Same as REX_B=1 (64 bit mode only)
468 unsigned char VEX_B = 0x1;
470 // VEX_W: opcode specific (use like REX.W, or used for
471 // opcode extension, or ignored, depending on the opcode byte)
472 unsigned char VEX_W = 0;
474 // XOP: Use XOP prefix byte 0x8f instead of VEX.
475 unsigned char XOP = 0;
477 // VEX_5M (VEX m-mmmmm field):
479 // 0b00000: Reserved for future use
480 // 0b00001: implied 0F leading opcode
481 // 0b00010: implied 0F 38 leading opcode bytes
482 // 0b00011: implied 0F 3A leading opcode bytes
483 // 0b00100-0b11111: Reserved for future use
484 // 0b01000: XOP map select - 08h instructions with imm byte
485 // 0b10001: XOP map select - 09h instructions with no imm byte
486 unsigned char VEX_5M = 0x1;
488 // VEX_4V (VEX vvvv field): a register specifier
489 // (in 1's complement form) or 1111 if unused.
490 unsigned char VEX_4V = 0xf;
492 // VEX_L (Vector Length):
494 // 0: scalar or 128-bit vector
497 unsigned char VEX_L = 0;
499 // VEX_PP: opcode extension providing equivalent
500 // functionality of a SIMD prefix
507 unsigned char VEX_PP = 0;
509 // Encode the operand size opcode prefix as needed.
510 if (TSFlags & X86II::OpSize)
513 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
516 if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
519 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
522 switch (TSFlags & X86II::Op0Mask) {
523 default: llvm_unreachable("Invalid prefix!");
524 case X86II::T8: // 0F 38
527 case X86II::TA: // 0F 3A
530 case X86II::T8XS: // F3 0F 38
534 case X86II::T8XD: // F2 0F 38
538 case X86II::TAXD: // F2 0F 3A
542 case X86II::XS: // F3 0F
545 case X86II::XD: // F2 0F
554 case X86II::A6: // Bypass: Not used by VEX
555 case X86II::A7: // Bypass: Not used by VEX
556 case X86II::TB: // Bypass: Not used by VEX
562 // Set the vector length to 256-bit if YMM0-YMM15 is used
563 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
564 if (!MI.getOperand(i).isReg())
566 unsigned SrcReg = MI.getOperand(i).getReg();
567 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
571 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
573 switch (TSFlags & X86II::FormMask) {
574 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!");
575 case X86II::MRMDestMem: {
576 // MRMDestMem instructions forms:
577 // MemAddr, src1(ModR/M)
578 // MemAddr, src1(VEX_4V), src2(ModR/M)
579 // MemAddr, src1(ModR/M), imm8
581 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
583 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
586 CurOp = X86::AddrNumOperands;
588 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
590 const MCOperand &MO = MI.getOperand(CurOp);
591 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
595 case X86II::MRMSrcMem:
596 // MRMSrcMem instructions forms:
597 // src1(ModR/M), MemAddr
598 // src1(ModR/M), src2(VEX_4V), MemAddr
599 // src1(ModR/M), MemAddr, imm8
600 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
603 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
604 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
605 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
609 VEX_4V = getVEXRegisterEncoding(MI, 1);
611 if (X86II::isX86_64ExtendedReg(
612 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
614 if (X86II::isX86_64ExtendedReg(
615 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
619 VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1);
621 case X86II::MRM0m: case X86II::MRM1m:
622 case X86II::MRM2m: case X86II::MRM3m:
623 case X86II::MRM4m: case X86II::MRM5m:
624 case X86II::MRM6m: case X86II::MRM7m: {
625 // MRM[0-9]m instructions forms:
627 // src1(VEX_4V), MemAddr
629 VEX_4V = getVEXRegisterEncoding(MI, 0);
631 if (X86II::isX86_64ExtendedReg(
632 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
634 if (X86II::isX86_64ExtendedReg(
635 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
639 case X86II::MRMSrcReg:
640 // MRMSrcReg instructions forms:
641 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
642 // dst(ModR/M), src1(ModR/M)
643 // dst(ModR/M), src1(ModR/M), imm8
645 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
650 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
651 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
655 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
657 case X86II::MRMDestReg:
658 // MRMDestReg instructions forms:
659 // dst(ModR/M), src(ModR/M)
660 // dst(ModR/M), src(ModR/M), imm8
661 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
663 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
666 case X86II::MRM0r: case X86II::MRM1r:
667 case X86II::MRM2r: case X86II::MRM3r:
668 case X86II::MRM4r: case X86II::MRM5r:
669 case X86II::MRM6r: case X86II::MRM7r:
670 // MRM0r-MRM7r instructions forms:
671 // dst(VEX_4V), src(ModR/M), imm8
672 VEX_4V = getVEXRegisterEncoding(MI, 0);
673 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
680 // Emit segment override opcode prefix as needed.
681 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
683 // VEX opcode prefix can have 2 or 3 bytes
686 // +-----+ +--------------+ +-------------------+
687 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
688 // +-----+ +--------------+ +-------------------+
690 // +-----+ +-------------------+
691 // | C5h | | R | vvvv | L | pp |
692 // +-----+ +-------------------+
694 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
696 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
697 EmitByte(0xC5, CurByte, OS);
698 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
703 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
704 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
705 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
708 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
709 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
710 /// size, and 3) use of X86-64 extended registers.
711 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
712 const MCInstrDesc &Desc) {
714 if (TSFlags & X86II::REX_W)
715 REX |= 1 << 3; // set REX.W
717 if (MI.getNumOperands() == 0) return REX;
719 unsigned NumOps = MI.getNumOperands();
720 // FIXME: MCInst should explicitize the two-addrness.
721 bool isTwoAddr = NumOps > 1 &&
722 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
724 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
725 unsigned i = isTwoAddr ? 1 : 0;
726 for (; i != NumOps; ++i) {
727 const MCOperand &MO = MI.getOperand(i);
728 if (!MO.isReg()) continue;
729 unsigned Reg = MO.getReg();
730 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
731 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
732 // that returns non-zero.
733 REX |= 0x40; // REX fixed encoding prefix
737 switch (TSFlags & X86II::FormMask) {
738 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!");
739 case X86II::MRMSrcReg:
740 if (MI.getOperand(0).isReg() &&
741 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
742 REX |= 1 << 2; // set REX.R
743 i = isTwoAddr ? 2 : 1;
744 for (; i != NumOps; ++i) {
745 const MCOperand &MO = MI.getOperand(i);
746 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
747 REX |= 1 << 0; // set REX.B
750 case X86II::MRMSrcMem: {
751 if (MI.getOperand(0).isReg() &&
752 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
753 REX |= 1 << 2; // set REX.R
755 i = isTwoAddr ? 2 : 1;
756 for (; i != NumOps; ++i) {
757 const MCOperand &MO = MI.getOperand(i);
759 if (X86II::isX86_64ExtendedReg(MO.getReg()))
760 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
766 case X86II::MRM0m: case X86II::MRM1m:
767 case X86II::MRM2m: case X86II::MRM3m:
768 case X86II::MRM4m: case X86II::MRM5m:
769 case X86II::MRM6m: case X86II::MRM7m:
770 case X86II::MRMDestMem: {
771 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
772 i = isTwoAddr ? 1 : 0;
773 if (NumOps > e && MI.getOperand(e).isReg() &&
774 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
775 REX |= 1 << 2; // set REX.R
777 for (; i != e; ++i) {
778 const MCOperand &MO = MI.getOperand(i);
780 if (X86II::isX86_64ExtendedReg(MO.getReg()))
781 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
788 if (MI.getOperand(0).isReg() &&
789 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
790 REX |= 1 << 0; // set REX.B
791 i = isTwoAddr ? 2 : 1;
792 for (unsigned e = NumOps; i != e; ++i) {
793 const MCOperand &MO = MI.getOperand(i);
794 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
795 REX |= 1 << 2; // set REX.R
802 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
803 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
804 unsigned &CurByte, int MemOperand,
806 raw_ostream &OS) const {
807 switch (TSFlags & X86II::SegOvrMask) {
808 default: llvm_unreachable("Invalid segment!");
810 // No segment override, check for explicit one on memory operand.
811 if (MemOperand != -1) { // If the instruction has a memory operand.
812 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
813 default: llvm_unreachable("Unknown segment register!");
815 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
816 case X86::SS: EmitByte(0x36, CurByte, OS); break;
817 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
818 case X86::ES: EmitByte(0x26, CurByte, OS); break;
819 case X86::FS: EmitByte(0x64, CurByte, OS); break;
820 case X86::GS: EmitByte(0x65, CurByte, OS); break;
825 EmitByte(0x64, CurByte, OS);
828 EmitByte(0x65, CurByte, OS);
833 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
835 /// MemOperand is the operand # of the start of a memory operand if present. If
836 /// Not present, it is -1.
837 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
838 int MemOperand, const MCInst &MI,
839 const MCInstrDesc &Desc,
840 raw_ostream &OS) const {
842 // Emit the lock opcode prefix as needed.
843 if (TSFlags & X86II::LOCK)
844 EmitByte(0xF0, CurByte, OS);
846 // Emit segment override opcode prefix as needed.
847 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
849 // Emit the repeat opcode prefix as needed.
850 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
851 EmitByte(0xF3, CurByte, OS);
853 // Emit the address size opcode prefix as needed.
854 bool need_address_override;
855 if (TSFlags & X86II::AdSize) {
856 need_address_override = true;
857 } else if (MemOperand == -1) {
858 need_address_override = false;
859 } else if (is64BitMode()) {
860 assert(!Is16BitMemOperand(MI, MemOperand));
861 need_address_override = Is32BitMemOperand(MI, MemOperand);
862 } else if (is32BitMode()) {
863 assert(!Is64BitMemOperand(MI, MemOperand));
864 need_address_override = Is16BitMemOperand(MI, MemOperand);
866 need_address_override = false;
869 if (need_address_override)
870 EmitByte(0x67, CurByte, OS);
872 // Emit the operand size opcode prefix as needed.
873 if (TSFlags & X86II::OpSize)
874 EmitByte(0x66, CurByte, OS);
876 bool Need0FPrefix = false;
877 switch (TSFlags & X86II::Op0Mask) {
878 default: llvm_unreachable("Invalid prefix!");
879 case 0: break; // No prefix!
880 case X86II::REP: break; // already handled.
881 case X86II::TB: // Two-byte opcode prefix
882 case X86II::T8: // 0F 38
883 case X86II::TA: // 0F 3A
884 case X86II::A6: // 0F A6
885 case X86II::A7: // 0F A7
888 case X86II::T8XS: // F3 0F 38
889 EmitByte(0xF3, CurByte, OS);
892 case X86II::T8XD: // F2 0F 38
893 EmitByte(0xF2, CurByte, OS);
896 case X86II::TAXD: // F2 0F 3A
897 EmitByte(0xF2, CurByte, OS);
900 case X86II::XS: // F3 0F
901 EmitByte(0xF3, CurByte, OS);
904 case X86II::XD: // F2 0F
905 EmitByte(0xF2, CurByte, OS);
908 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
909 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
910 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
911 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
912 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
913 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
914 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
915 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
918 // Handle REX prefix.
919 // FIXME: Can this come before F2 etc to simplify emission?
921 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
922 EmitByte(0x40 | REX, CurByte, OS);
925 // 0x0F escape code must be emitted just before the opcode.
927 EmitByte(0x0F, CurByte, OS);
929 // FIXME: Pull this up into previous switch if REX can be moved earlier.
930 switch (TSFlags & X86II::Op0Mask) {
931 case X86II::T8XS: // F3 0F 38
932 case X86II::T8XD: // F2 0F 38
933 case X86II::T8: // 0F 38
934 EmitByte(0x38, CurByte, OS);
936 case X86II::TAXD: // F2 0F 3A
937 case X86II::TA: // 0F 3A
938 EmitByte(0x3A, CurByte, OS);
940 case X86II::A6: // 0F A6
941 EmitByte(0xA6, CurByte, OS);
943 case X86II::A7: // 0F A7
944 EmitByte(0xA7, CurByte, OS);
949 void X86MCCodeEmitter::
950 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
951 SmallVectorImpl<MCFixup> &Fixups) const {
952 unsigned Opcode = MI.getOpcode();
953 const MCInstrDesc &Desc = MCII.get(Opcode);
954 uint64_t TSFlags = Desc.TSFlags;
956 // Pseudo instructions don't get encoded.
957 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
960 // If this is a two-address instruction, skip one of the register operands.
961 // FIXME: This should be handled during MCInst lowering.
962 unsigned NumOps = Desc.getNumOperands();
964 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1)
966 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0)
967 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
970 // Keep track of the current byte being emitted.
971 unsigned CurByte = 0;
973 // Is this instruction encoded using the AVX VEX prefix?
974 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX;
976 // It uses the VEX.VVVV field?
977 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
978 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
979 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
980 const unsigned MemOp4_I8IMMOperand = 2;
982 // Determine where the memory operand starts, if present.
983 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
984 if (MemoryOperand != -1) MemoryOperand += CurOp;
987 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
989 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
991 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
993 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
994 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
996 unsigned SrcRegNum = 0;
997 switch (TSFlags & X86II::FormMask) {
998 case X86II::MRMInitReg:
999 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
1000 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1001 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1003 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1005 EmitByte(BaseOpcode, CurByte, OS);
1007 case X86II::RawFrmImm8:
1008 EmitByte(BaseOpcode, CurByte, OS);
1009 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1010 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1011 CurByte, OS, Fixups);
1012 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1015 case X86II::RawFrmImm16:
1016 EmitByte(BaseOpcode, CurByte, OS);
1017 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1018 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1019 CurByte, OS, Fixups);
1020 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1024 case X86II::AddRegFrm:
1025 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1028 case X86II::MRMDestReg:
1029 EmitByte(BaseOpcode, CurByte, OS);
1030 EmitRegModRMByte(MI.getOperand(CurOp),
1031 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
1035 case X86II::MRMDestMem:
1036 EmitByte(BaseOpcode, CurByte, OS);
1037 SrcRegNum = CurOp + X86::AddrNumOperands;
1039 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1042 EmitMemModRMByte(MI, CurOp,
1043 GetX86RegNum(MI.getOperand(SrcRegNum)),
1044 TSFlags, CurByte, OS, Fixups);
1045 CurOp = SrcRegNum + 1;
1048 case X86II::MRMSrcReg:
1049 EmitByte(BaseOpcode, CurByte, OS);
1050 SrcRegNum = CurOp + 1;
1052 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1055 if(HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1058 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1059 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1061 // 2 operands skipped with HasMemOp4, comensate accordingly
1062 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1067 case X86II::MRMSrcMem: {
1068 int AddrOperands = X86::AddrNumOperands;
1069 unsigned FirstMemOp = CurOp+1;
1072 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1074 if(HasMemOp4) // Skip second register source (encoded in I8IMM)
1077 EmitByte(BaseOpcode, CurByte, OS);
1079 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1080 TSFlags, CurByte, OS, Fixups);
1081 CurOp += AddrOperands + 1;
1087 case X86II::MRM0r: case X86II::MRM1r:
1088 case X86II::MRM2r: case X86II::MRM3r:
1089 case X86II::MRM4r: case X86II::MRM5r:
1090 case X86II::MRM6r: case X86II::MRM7r:
1091 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1093 EmitByte(BaseOpcode, CurByte, OS);
1094 EmitRegModRMByte(MI.getOperand(CurOp++),
1095 (TSFlags & X86II::FormMask)-X86II::MRM0r,
1098 case X86II::MRM0m: case X86II::MRM1m:
1099 case X86II::MRM2m: case X86II::MRM3m:
1100 case X86II::MRM4m: case X86II::MRM5m:
1101 case X86II::MRM6m: case X86II::MRM7m:
1102 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1104 EmitByte(BaseOpcode, CurByte, OS);
1105 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
1106 TSFlags, CurByte, OS, Fixups);
1107 CurOp += X86::AddrNumOperands;
1109 case X86II::MRM_C1: case X86II::MRM_C2:
1110 case X86II::MRM_C3: case X86II::MRM_C4:
1111 case X86II::MRM_C8: case X86II::MRM_C9:
1112 case X86II::MRM_D0: case X86II::MRM_D1:
1113 case X86II::MRM_D4: case X86II::MRM_D8:
1114 case X86II::MRM_D9: case X86II::MRM_DA:
1115 case X86II::MRM_DB: case X86II::MRM_DC:
1116 case X86II::MRM_DD: case X86II::MRM_DE:
1117 case X86II::MRM_DF: case X86II::MRM_E8:
1118 case X86II::MRM_F0: case X86II::MRM_F8:
1120 EmitByte(BaseOpcode, CurByte, OS);
1123 switch (TSFlags & X86II::FormMask) {
1124 default: llvm_unreachable("Invalid Form");
1125 case X86II::MRM_C1: MRM = 0xC1; break;
1126 case X86II::MRM_C2: MRM = 0xC2; break;
1127 case X86II::MRM_C3: MRM = 0xC3; break;
1128 case X86II::MRM_C4: MRM = 0xC4; break;
1129 case X86II::MRM_C8: MRM = 0xC8; break;
1130 case X86II::MRM_C9: MRM = 0xC9; break;
1131 case X86II::MRM_D0: MRM = 0xD0; break;
1132 case X86II::MRM_D1: MRM = 0xD1; break;
1133 case X86II::MRM_D4: MRM = 0xD4; break;
1134 case X86II::MRM_D8: MRM = 0xD8; break;
1135 case X86II::MRM_D9: MRM = 0xD9; break;
1136 case X86II::MRM_DA: MRM = 0xDA; break;
1137 case X86II::MRM_DB: MRM = 0xDB; break;
1138 case X86II::MRM_DC: MRM = 0xDC; break;
1139 case X86II::MRM_DD: MRM = 0xDD; break;
1140 case X86II::MRM_DE: MRM = 0xDE; break;
1141 case X86II::MRM_DF: MRM = 0xDF; break;
1142 case X86II::MRM_E8: MRM = 0xE8; break;
1143 case X86II::MRM_F0: MRM = 0xF0; break;
1144 case X86II::MRM_F8: MRM = 0xF8; break;
1145 case X86II::MRM_F9: MRM = 0xF9; break;
1147 EmitByte(MRM, CurByte, OS);
1151 // If there is a remaining operand, it must be a trailing immediate. Emit it
1152 // according to the right size for the instruction.
1153 if (CurOp != NumOps) {
1154 // The last source register of a 4 operand instruction in AVX is encoded
1155 // in bits[7:4] of a immediate byte.
1156 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1157 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1160 bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg());
1161 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
1162 RegNum |= GetX86RegNum(MO) << 4;
1163 // If there is an additional 5th operand it must be an immediate, which
1164 // is encoded in bits[3:0]
1165 if(CurOp != NumOps) {
1166 const MCOperand &MIMM = MI.getOperand(CurOp++);
1168 unsigned Val = MIMM.getImm();
1169 assert(Val < 16 && "Immediate operand value out of range");
1173 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1174 CurByte, OS, Fixups);
1177 // FIXME: Is there a better way to know that we need a signed relocation?
1178 if (MI.getOpcode() == X86::ADD64ri32 ||
1179 MI.getOpcode() == X86::MOV64ri32 ||
1180 MI.getOpcode() == X86::MOV64mi32 ||
1181 MI.getOpcode() == X86::PUSH64i32)
1182 FixupKind = X86::reloc_signed_4byte;
1184 FixupKind = getImmFixupKind(TSFlags);
1185 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1186 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1187 CurByte, OS, Fixups);
1191 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1192 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1196 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1197 errs() << "Cannot encode all operands of: ";