1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Support/raw_ostream.h"
31 class X86MCCodeEmitter : public MCCodeEmitter {
32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 const MCInstrInfo &MCII;
35 const MCSubtargetInfo &STI;
38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
40 : MCII(mcii), STI(sti), Ctx(ctx) {
43 ~X86MCCodeEmitter() {}
45 bool is64BitMode() const {
46 // FIXME: Can tablegen auto-generate this?
47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
50 bool is32BitMode() const {
51 // FIXME: Can tablegen auto-generate this?
52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
55 unsigned GetX86RegNum(const MCOperand &MO) const {
56 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
59 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
60 // 0-7 and the difference between the 2 groups is given by the REX prefix.
61 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
62 // in 1's complement form, example:
64 // ModRM field => XMM9 => 1
65 // VEX.VVVV => XMM9 => ~9
67 // See table 4-35 of Intel AVX Programming Reference for details.
68 unsigned char getVEXRegisterEncoding(const MCInst &MI,
69 unsigned OpNum) const {
70 unsigned SrcReg = MI.getOperand(OpNum).getReg();
71 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
72 if (X86II::isX86_64ExtendedReg(SrcReg))
75 // The registers represented through VEX_VVVV should
76 // be encoded in 1's complement form.
77 return (~SrcRegNum) & 0xf;
80 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
81 unsigned OpNum) const {
82 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
83 "Invalid mask register as write-mask!");
84 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
88 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
93 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
94 raw_ostream &OS) const {
95 // Output the constant in little endian byte order.
96 for (unsigned i = 0; i != Size; ++i) {
97 EmitByte(Val & 255, CurByte, OS);
102 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
103 unsigned ImmSize, MCFixupKind FixupKind,
104 unsigned &CurByte, raw_ostream &OS,
105 SmallVectorImpl<MCFixup> &Fixups,
106 int ImmOffset = 0) const;
108 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
110 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
111 return RM | (RegOpcode << 3) | (Mod << 6);
114 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
115 unsigned &CurByte, raw_ostream &OS) const {
116 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
119 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
120 unsigned &CurByte, raw_ostream &OS) const {
121 // SIB byte is in the same format as the ModRMByte.
122 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
126 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
127 unsigned RegOpcodeField,
128 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
132 SmallVectorImpl<MCFixup> &Fixups) const;
134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
135 const MCInst &MI, const MCInstrDesc &Desc,
136 raw_ostream &OS) const;
138 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
139 int MemOperand, const MCInst &MI,
140 raw_ostream &OS) const;
142 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
143 const MCInst &MI, const MCInstrDesc &Desc,
144 raw_ostream &OS) const;
147 } // end anonymous namespace
150 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
151 const MCRegisterInfo &MRI,
152 const MCSubtargetInfo &STI,
154 return new X86MCCodeEmitter(MCII, STI, Ctx);
157 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
158 /// sign-extended field.
159 static bool isDisp8(int Value) {
160 return Value == (signed char)Value;
163 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
164 /// compressed dispacement field.
165 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
166 assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) &&
167 "Compressed 8-bit displacement is only valid for EVEX inst.");
169 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask;
170 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask;
172 if (CD8V == 0 && CD8E == 0) {
174 return isDisp8(Value);
177 unsigned MemObjSize = 1U << CD8E;
179 // Fixed vector length
180 MemObjSize *= 1U << (CD8V & 0x3);
182 // Modified vector length
183 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B;
185 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0;
186 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0;
187 assert(EVEX_LL < 3 && "");
189 unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize;
190 NumElems /= 1U << (CD8V & 0x3);
192 MemObjSize *= NumElems;
196 unsigned MemObjMask = MemObjSize - 1;
197 assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size.");
199 if (Value & MemObjMask) // Unaligned offset
202 bool Ret = (Value == (signed char)Value);
209 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
210 /// in an instruction with the specified TSFlags.
211 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
212 unsigned Size = X86II::getSizeOfImm(TSFlags);
213 bool isPCRel = X86II::isImmPCRel(TSFlags);
215 return MCFixup::getKindForSize(Size, isPCRel);
218 /// Is32BitMemOperand - Return true if the specified instruction has
219 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
220 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
221 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
222 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
224 if ((BaseReg.getReg() != 0 &&
225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
226 (IndexReg.getReg() != 0 &&
227 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
232 /// Is64BitMemOperand - Return true if the specified instruction has
233 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
235 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
236 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
237 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
239 if ((BaseReg.getReg() != 0 &&
240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
241 (IndexReg.getReg() != 0 &&
242 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
248 /// Is16BitMemOperand - Return true if the specified instruction has
249 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
250 static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) {
251 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
252 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
254 if ((BaseReg.getReg() != 0 &&
255 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
256 (IndexReg.getReg() != 0 &&
257 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
262 /// StartsWithGlobalOffsetTable - Check if this expression starts with
263 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
264 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
265 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
266 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
267 /// of a binary expression.
268 enum GlobalOffsetTableExprKind {
273 static GlobalOffsetTableExprKind
274 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
275 const MCExpr *RHS = 0;
276 if (Expr->getKind() == MCExpr::Binary) {
277 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
282 if (Expr->getKind() != MCExpr::SymbolRef)
285 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
286 const MCSymbol &S = Ref->getSymbol();
287 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
289 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
294 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
295 if (Expr->getKind() == MCExpr::SymbolRef) {
296 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
297 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
302 void X86MCCodeEmitter::
303 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
304 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
305 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
306 const MCExpr *Expr = NULL;
307 if (DispOp.isImm()) {
308 // If this is a simple integer displacement that doesn't require a
309 // relocation, emit it now.
310 if (FixupKind != FK_PCRel_1 &&
311 FixupKind != FK_PCRel_2 &&
312 FixupKind != FK_PCRel_4) {
313 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
316 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
318 Expr = DispOp.getExpr();
321 // If we have an immoffset, add it to the expression.
322 if ((FixupKind == FK_Data_4 ||
323 FixupKind == FK_Data_8 ||
324 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
325 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
326 if (Kind != GOT_None) {
327 assert(ImmOffset == 0);
329 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
330 if (Kind == GOT_Normal)
332 } else if (Expr->getKind() == MCExpr::SymbolRef) {
333 if (HasSecRelSymbolRef(Expr)) {
334 FixupKind = MCFixupKind(FK_SecRel_4);
336 } else if (Expr->getKind() == MCExpr::Binary) {
337 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
338 if (HasSecRelSymbolRef(Bin->getLHS())
339 || HasSecRelSymbolRef(Bin->getRHS())) {
340 FixupKind = MCFixupKind(FK_SecRel_4);
345 // If the fixup is pc-relative, we need to bias the value to be relative to
346 // the start of the field, not the end of the field.
347 if (FixupKind == FK_PCRel_4 ||
348 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
349 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
351 if (FixupKind == FK_PCRel_2)
353 if (FixupKind == FK_PCRel_1)
357 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
360 // Emit a symbolic constant as a fixup and 4 zeros.
361 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
362 EmitConstant(0, Size, CurByte, OS);
365 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
366 unsigned RegOpcodeField,
367 uint64_t TSFlags, unsigned &CurByte,
369 SmallVectorImpl<MCFixup> &Fixups) const{
370 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
371 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
372 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
373 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
374 unsigned BaseReg = Base.getReg();
375 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
377 // Handle %rip relative addressing.
378 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
379 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
380 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
381 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
383 unsigned FixupKind = X86::reloc_riprel_4byte;
385 // movq loads are handled with a special relocation form which allows the
386 // linker to eliminate some loads for GOT references which end up in the
387 // same linkage unit.
388 if (MI.getOpcode() == X86::MOV64rm)
389 FixupKind = X86::reloc_riprel_4byte_movq_load;
391 // rip-relative addressing is actually relative to the *next* instruction.
392 // Since an immediate can follow the mod/rm byte for an instruction, this
393 // means that we need to bias the immediate field of the instruction with
394 // the size of the immediate field. If we have this case, add it into the
395 // expression to emit.
396 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
398 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
399 CurByte, OS, Fixups, -ImmSize);
403 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
405 // Determine whether a SIB byte is needed.
406 // If no BaseReg, issue a RIP relative instruction only if the MCE can
407 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
408 // 2-7) and absolute references.
410 if (// The SIB byte must be used if there is an index register.
411 IndexReg.getReg() == 0 &&
412 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
413 // encode to an R/M value of 4, which indicates that a SIB byte is
415 BaseRegNo != N86::ESP &&
416 // If there is no base register and we're in 64-bit mode, we need a SIB
417 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
418 (!is64BitMode() || BaseReg != 0)) {
420 if (BaseReg == 0) { // [disp32] in X86-32 mode
421 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
422 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
426 // If the base is not EBP/ESP and there is no displacement, use simple
427 // indirect register encoding, this handles addresses like [EAX]. The
428 // encoding for [EBP] with no displacement means [disp32] so we handle it
429 // by emitting a displacement of 0 below.
430 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
431 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
435 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
437 if (!HasEVEX && isDisp8(Disp.getImm())) {
438 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
439 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
442 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
443 // 32-bit displacement.
445 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
446 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
447 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
448 CDisp8 - Disp.getImm());
453 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
454 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
455 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
460 // We need a SIB byte, so start by outputting the ModR/M byte first
461 assert(IndexReg.getReg() != X86::ESP &&
462 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
464 bool ForceDisp32 = false;
465 bool ForceDisp8 = false;
469 // If there is no base register, we emit the special case SIB byte with
470 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
471 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
473 } else if (!Disp.isImm()) {
474 // Emit the normal disp32 encoding.
475 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
477 } else if (Disp.getImm() == 0 &&
478 // Base reg can't be anything that ends up with '5' as the base
479 // reg, it is the magic [*] nomenclature that indicates no base.
480 BaseRegNo != N86::EBP) {
481 // Emit no displacement ModR/M byte
482 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
483 } else if (!HasEVEX && isDisp8(Disp.getImm())) {
484 // Emit the disp8 encoding.
485 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
486 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
487 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
488 // Emit the disp8 encoding.
489 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
490 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
491 ImmOffset = CDisp8 - Disp.getImm();
493 // Emit the normal disp32 encoding.
494 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
497 // Calculate what the SS field value should be...
498 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
499 unsigned SS = SSTable[Scale.getImm()];
502 // Handle the SIB byte for the case where there is no base, see Intel
503 // Manual 2A, table 2-7. The displacement has already been output.
505 if (IndexReg.getReg())
506 IndexRegNo = GetX86RegNum(IndexReg);
507 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
509 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
512 if (IndexReg.getReg())
513 IndexRegNo = GetX86RegNum(IndexReg);
515 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
516 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
519 // Do we need to output a displacement?
521 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
522 else if (ForceDisp32 || Disp.getImm() != 0)
523 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
524 CurByte, OS, Fixups);
527 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
529 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
530 int MemOperand, const MCInst &MI,
531 const MCInstrDesc &Desc,
532 raw_ostream &OS) const {
533 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
534 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
535 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
536 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
537 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
539 // VEX_R: opcode externsion equivalent to REX.R in
540 // 1's complement (inverted) form
542 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
543 // 0: Same as REX_R=1 (64 bit mode only)
545 unsigned char VEX_R = 0x1;
546 unsigned char EVEX_R2 = 0x1;
548 // VEX_X: equivalent to REX.X, only used when a
549 // register is used for index in SIB Byte.
551 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
552 // 0: Same as REX.X=1 (64-bit mode only)
553 unsigned char VEX_X = 0x1;
557 // 1: Same as REX_B=0 (ignored in 32-bit mode)
558 // 0: Same as REX_B=1 (64 bit mode only)
560 unsigned char VEX_B = 0x1;
562 // VEX_W: opcode specific (use like REX.W, or used for
563 // opcode extension, or ignored, depending on the opcode byte)
564 unsigned char VEX_W = 0;
566 // XOP: Use XOP prefix byte 0x8f instead of VEX.
569 // VEX_5M (VEX m-mmmmm field):
571 // 0b00000: Reserved for future use
572 // 0b00001: implied 0F leading opcode
573 // 0b00010: implied 0F 38 leading opcode bytes
574 // 0b00011: implied 0F 3A leading opcode bytes
575 // 0b00100-0b11111: Reserved for future use
576 // 0b01000: XOP map select - 08h instructions with imm byte
577 // 0b01001: XOP map select - 09h instructions with no imm byte
578 // 0b01010: XOP map select - 0Ah instructions with imm dword
579 unsigned char VEX_5M = 0x1;
581 // VEX_4V (VEX vvvv field): a register specifier
582 // (in 1's complement form) or 1111 if unused.
583 unsigned char VEX_4V = 0xf;
584 unsigned char EVEX_V2 = 0x1;
586 // VEX_L (Vector Length):
588 // 0: scalar or 128-bit vector
591 unsigned char VEX_L = 0;
592 unsigned char EVEX_L2 = 0;
594 // VEX_PP: opcode extension providing equivalent
595 // functionality of a SIMD prefix
602 unsigned char VEX_PP = 0;
605 unsigned char EVEX_U = 1; // Always '1' so far
608 unsigned char EVEX_z = 0;
611 unsigned char EVEX_b = 0;
614 unsigned char EVEX_aaa = 0;
616 // Encode the operand size opcode prefix as needed.
617 if (TSFlags & X86II::OpSize)
620 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
623 if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
626 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
628 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
631 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z))
634 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_B))
637 switch (TSFlags & X86II::Op0Mask) {
638 default: llvm_unreachable("Invalid prefix!");
639 case X86II::T8: // 0F 38
642 case X86II::TA: // 0F 3A
645 case X86II::T8XS: // F3 0F 38
649 case X86II::T8XD: // F2 0F 38
653 case X86II::TAXD: // F2 0F 3A
657 case X86II::XS: // F3 0F
660 case X86II::XD: // F2 0F
672 case X86II::TB: // VEX_5M/VEX_PP already correct
677 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
678 unsigned NumOps = Desc.getNumOperands();
680 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
682 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
683 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
684 // Special case for AVX-512 GATHER with 2 TIED_TO operands
685 // Skip the first 2 operands: dst, mask_wb
687 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
688 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
689 // Special case for GATHER with 2 TIED_TO operands
690 // Skip the first 2 operands: dst, mask_wb
692 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
696 switch (TSFlags & X86II::FormMask) {
697 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!");
698 case X86II::MRMDestMem: {
699 // MRMDestMem instructions forms:
700 // MemAddr, src1(ModR/M)
701 // MemAddr, src1(VEX_4V), src2(ModR/M)
702 // MemAddr, src1(ModR/M), imm8
704 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
705 X86::AddrBaseReg).getReg()))
707 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
708 X86::AddrIndexReg).getReg()))
710 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
711 X86::AddrIndexReg).getReg()))
714 CurOp += X86::AddrNumOperands;
717 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
720 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
721 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
726 const MCOperand &MO = MI.getOperand(CurOp);
728 if (X86II::isX86_64ExtendedReg(MO.getReg()))
730 if (HasEVEX && X86II::is32ExtendedReg(MO.getReg()))
735 case X86II::MRMSrcMem:
736 // MRMSrcMem instructions forms:
737 // src1(ModR/M), MemAddr
738 // src1(ModR/M), src2(VEX_4V), MemAddr
739 // src1(ModR/M), MemAddr, imm8
740 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
743 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
744 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
745 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
747 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
752 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
755 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
756 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
761 if (X86II::isX86_64ExtendedReg(
762 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
764 if (X86II::isX86_64ExtendedReg(
765 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
767 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
768 X86::AddrIndexReg).getReg()))
772 // Instruction format for 4VOp3:
773 // src1(ModR/M), MemAddr, src3(VEX_4V)
774 // CurOp points to start of the MemoryOperand,
775 // it skips TIED_TO operands if exist, then increments past src1.
776 // CurOp + X86::AddrNumOperands will point to src3.
777 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
779 case X86II::MRM0m: case X86II::MRM1m:
780 case X86II::MRM2m: case X86II::MRM3m:
781 case X86II::MRM4m: case X86II::MRM5m:
782 case X86II::MRM6m: case X86II::MRM7m: {
783 // MRM[0-9]m instructions forms:
785 // src1(VEX_4V), MemAddr
787 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
788 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
794 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
796 if (X86II::isX86_64ExtendedReg(
797 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
799 if (X86II::isX86_64ExtendedReg(
800 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
804 case X86II::MRMSrcReg:
805 // MRMSrcReg instructions forms:
806 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
807 // dst(ModR/M), src1(ModR/M)
808 // dst(ModR/M), src1(ModR/M), imm8
811 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
812 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
813 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
815 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
820 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
823 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
824 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
829 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
832 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
834 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
838 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
840 case X86II::MRMDestReg:
841 // MRMDestReg instructions forms:
842 // dst(ModR/M), src(ModR/M)
843 // dst(ModR/M), src(ModR/M), imm8
844 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
845 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
847 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
852 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
855 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
856 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
861 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
863 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
866 case X86II::MRM0r: case X86II::MRM1r:
867 case X86II::MRM2r: case X86II::MRM3r:
868 case X86II::MRM4r: case X86II::MRM5r:
869 case X86II::MRM6r: case X86II::MRM7r:
870 // MRM0r-MRM7r instructions forms:
871 // dst(VEX_4V), src(ModR/M), imm8
873 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
874 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
879 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
881 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
883 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
890 // Emit segment override opcode prefix as needed.
891 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
894 // VEX opcode prefix can have 2 or 3 bytes
897 // +-----+ +--------------+ +-------------------+
898 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
899 // +-----+ +--------------+ +-------------------+
901 // +-----+ +-------------------+
902 // | C5h | | R | vvvv | L | pp |
903 // +-----+ +-------------------+
905 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
907 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
908 EmitByte(0xC5, CurByte, OS);
909 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
914 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
915 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
916 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
918 // EVEX opcode prefix can have 4 bytes
920 // +-----+ +--------------+ +-------------------+ +------------------------+
921 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
922 // +-----+ +--------------+ +-------------------+ +------------------------+
923 assert((VEX_5M & 0x3) == VEX_5M
924 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
928 EmitByte(0x62, CurByte, OS);
929 EmitByte((VEX_R << 7) |
933 VEX_5M, CurByte, OS);
934 EmitByte((VEX_W << 7) |
937 VEX_PP, CurByte, OS);
938 EmitByte((EVEX_z << 7) |
943 EVEX_aaa, CurByte, OS);
947 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
948 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
949 /// size, and 3) use of X86-64 extended registers.
950 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
951 const MCInstrDesc &Desc) {
953 if (TSFlags & X86II::REX_W)
954 REX |= 1 << 3; // set REX.W
956 if (MI.getNumOperands() == 0) return REX;
958 unsigned NumOps = MI.getNumOperands();
959 // FIXME: MCInst should explicitize the two-addrness.
960 bool isTwoAddr = NumOps > 1 &&
961 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
963 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
964 unsigned i = isTwoAddr ? 1 : 0;
965 for (; i != NumOps; ++i) {
966 const MCOperand &MO = MI.getOperand(i);
967 if (!MO.isReg()) continue;
968 unsigned Reg = MO.getReg();
969 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
970 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
971 // that returns non-zero.
972 REX |= 0x40; // REX fixed encoding prefix
976 switch (TSFlags & X86II::FormMask) {
977 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!");
978 case X86II::MRMSrcReg:
979 if (MI.getOperand(0).isReg() &&
980 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
981 REX |= 1 << 2; // set REX.R
982 i = isTwoAddr ? 2 : 1;
983 for (; i != NumOps; ++i) {
984 const MCOperand &MO = MI.getOperand(i);
985 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
986 REX |= 1 << 0; // set REX.B
989 case X86II::MRMSrcMem: {
990 if (MI.getOperand(0).isReg() &&
991 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
992 REX |= 1 << 2; // set REX.R
994 i = isTwoAddr ? 2 : 1;
995 for (; i != NumOps; ++i) {
996 const MCOperand &MO = MI.getOperand(i);
998 if (X86II::isX86_64ExtendedReg(MO.getReg()))
999 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
1005 case X86II::MRM0m: case X86II::MRM1m:
1006 case X86II::MRM2m: case X86II::MRM3m:
1007 case X86II::MRM4m: case X86II::MRM5m:
1008 case X86II::MRM6m: case X86II::MRM7m:
1009 case X86II::MRMDestMem: {
1010 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
1011 i = isTwoAddr ? 1 : 0;
1012 if (NumOps > e && MI.getOperand(e).isReg() &&
1013 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
1014 REX |= 1 << 2; // set REX.R
1016 for (; i != e; ++i) {
1017 const MCOperand &MO = MI.getOperand(i);
1019 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1020 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
1027 if (MI.getOperand(0).isReg() &&
1028 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1029 REX |= 1 << 0; // set REX.B
1030 i = isTwoAddr ? 2 : 1;
1031 for (unsigned e = NumOps; i != e; ++i) {
1032 const MCOperand &MO = MI.getOperand(i);
1033 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1034 REX |= 1 << 2; // set REX.R
1041 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1042 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
1043 unsigned &CurByte, int MemOperand,
1045 raw_ostream &OS) const {
1046 switch (TSFlags & X86II::SegOvrMask) {
1047 default: llvm_unreachable("Invalid segment!");
1049 // No segment override, check for explicit one on memory operand.
1050 if (MemOperand != -1) { // If the instruction has a memory operand.
1051 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
1052 default: llvm_unreachable("Unknown segment register!");
1054 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1055 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1056 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1057 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1058 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1059 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1064 EmitByte(0x64, CurByte, OS);
1067 EmitByte(0x65, CurByte, OS);
1072 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1074 /// MemOperand is the operand # of the start of a memory operand if present. If
1075 /// Not present, it is -1.
1076 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1077 int MemOperand, const MCInst &MI,
1078 const MCInstrDesc &Desc,
1079 raw_ostream &OS) const {
1081 // Emit the lock opcode prefix as needed.
1082 if (TSFlags & X86II::LOCK)
1083 EmitByte(0xF0, CurByte, OS);
1085 // Emit segment override opcode prefix as needed.
1086 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
1088 // Emit the repeat opcode prefix as needed.
1089 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
1090 EmitByte(0xF3, CurByte, OS);
1092 // Emit the address size opcode prefix as needed.
1093 bool need_address_override;
1094 if (TSFlags & X86II::AdSize) {
1095 need_address_override = true;
1096 } else if (MemOperand == -1) {
1097 need_address_override = false;
1098 } else if (is64BitMode()) {
1099 assert(!Is16BitMemOperand(MI, MemOperand));
1100 need_address_override = Is32BitMemOperand(MI, MemOperand);
1101 } else if (is32BitMode()) {
1102 assert(!Is64BitMemOperand(MI, MemOperand));
1103 need_address_override = Is16BitMemOperand(MI, MemOperand);
1105 need_address_override = false;
1108 if (need_address_override)
1109 EmitByte(0x67, CurByte, OS);
1111 // Emit the operand size opcode prefix as needed.
1112 if (TSFlags & X86II::OpSize)
1113 EmitByte(0x66, CurByte, OS);
1115 bool Need0FPrefix = false;
1116 switch (TSFlags & X86II::Op0Mask) {
1117 default: llvm_unreachable("Invalid prefix!");
1118 case 0: break; // No prefix!
1119 case X86II::REP: break; // already handled.
1120 case X86II::TB: // Two-byte opcode prefix
1121 case X86II::T8: // 0F 38
1122 case X86II::TA: // 0F 3A
1123 case X86II::A6: // 0F A6
1124 case X86II::A7: // 0F A7
1125 Need0FPrefix = true;
1127 case X86II::XS: // F3 0F
1128 case X86II::T8XS: // F3 0F 38
1129 EmitByte(0xF3, CurByte, OS);
1130 Need0FPrefix = true;
1132 case X86II::XD: // F2 0F
1133 case X86II::T8XD: // F2 0F 38
1134 case X86II::TAXD: // F2 0F 3A
1135 EmitByte(0xF2, CurByte, OS);
1136 Need0FPrefix = true;
1146 EmitByte(0xD8+(((TSFlags & X86II::Op0Mask) - X86II::D8) >> X86II::Op0Shift),
1151 // Handle REX prefix.
1152 // FIXME: Can this come before F2 etc to simplify emission?
1153 if (is64BitMode()) {
1154 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
1155 EmitByte(0x40 | REX, CurByte, OS);
1158 // 0x0F escape code must be emitted just before the opcode.
1160 EmitByte(0x0F, CurByte, OS);
1162 // FIXME: Pull this up into previous switch if REX can be moved earlier.
1163 switch (TSFlags & X86II::Op0Mask) {
1164 case X86II::T8XS: // F3 0F 38
1165 case X86II::T8XD: // F2 0F 38
1166 case X86II::T8: // 0F 38
1167 EmitByte(0x38, CurByte, OS);
1169 case X86II::TAXD: // F2 0F 3A
1170 case X86II::TA: // 0F 3A
1171 EmitByte(0x3A, CurByte, OS);
1173 case X86II::A6: // 0F A6
1174 EmitByte(0xA6, CurByte, OS);
1176 case X86II::A7: // 0F A7
1177 EmitByte(0xA7, CurByte, OS);
1182 void X86MCCodeEmitter::
1183 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1184 SmallVectorImpl<MCFixup> &Fixups) const {
1185 unsigned Opcode = MI.getOpcode();
1186 const MCInstrDesc &Desc = MCII.get(Opcode);
1187 uint64_t TSFlags = Desc.TSFlags;
1189 // Pseudo instructions don't get encoded.
1190 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1193 unsigned NumOps = Desc.getNumOperands();
1194 unsigned CurOp = X86II::getOperandBias(Desc);
1196 // Keep track of the current byte being emitted.
1197 unsigned CurByte = 0;
1199 // Is this instruction encoded using the AVX VEX prefix?
1200 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX;
1202 // It uses the VEX.VVVV field?
1203 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
1204 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
1205 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
1206 const unsigned MemOp4_I8IMMOperand = 2;
1208 // It uses the EVEX.aaa field?
1209 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
1210 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
1212 // Determine where the memory operand starts, if present.
1213 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1214 if (MemoryOperand != -1) MemoryOperand += CurOp;
1217 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1219 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1221 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1223 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1224 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1226 unsigned SrcRegNum = 0;
1227 switch (TSFlags & X86II::FormMask) {
1228 case X86II::MRMInitReg:
1229 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
1230 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1231 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1233 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1235 EmitByte(BaseOpcode, CurByte, OS);
1237 case X86II::RawFrmImm8:
1238 EmitByte(BaseOpcode, CurByte, OS);
1239 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1240 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1241 CurByte, OS, Fixups);
1242 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1245 case X86II::RawFrmImm16:
1246 EmitByte(BaseOpcode, CurByte, OS);
1247 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1248 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1249 CurByte, OS, Fixups);
1250 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1254 case X86II::AddRegFrm:
1255 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1258 case X86II::MRMDestReg:
1259 EmitByte(BaseOpcode, CurByte, OS);
1260 SrcRegNum = CurOp + 1;
1262 if (HasEVEX_K) // Skip writemask
1265 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1268 EmitRegModRMByte(MI.getOperand(CurOp),
1269 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1270 CurOp = SrcRegNum + 1;
1273 case X86II::MRMDestMem:
1274 EmitByte(BaseOpcode, CurByte, OS);
1275 SrcRegNum = CurOp + X86::AddrNumOperands;
1277 if (HasEVEX_K) // Skip writemask
1280 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1283 EmitMemModRMByte(MI, CurOp,
1284 GetX86RegNum(MI.getOperand(SrcRegNum)),
1285 TSFlags, CurByte, OS, Fixups);
1286 CurOp = SrcRegNum + 1;
1289 case X86II::MRMSrcReg:
1290 EmitByte(BaseOpcode, CurByte, OS);
1291 SrcRegNum = CurOp + 1;
1293 if (HasEVEX_K) // Skip writemask
1296 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1299 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1302 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1303 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1305 // 2 operands skipped with HasMemOp4, compensate accordingly
1306 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1311 case X86II::MRMSrcMem: {
1312 int AddrOperands = X86::AddrNumOperands;
1313 unsigned FirstMemOp = CurOp+1;
1315 if (HasEVEX_K) { // Skip writemask
1322 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1324 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1327 EmitByte(BaseOpcode, CurByte, OS);
1329 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1330 TSFlags, CurByte, OS, Fixups);
1331 CurOp += AddrOperands + 1;
1337 case X86II::MRM0r: case X86II::MRM1r:
1338 case X86II::MRM2r: case X86II::MRM3r:
1339 case X86II::MRM4r: case X86II::MRM5r:
1340 case X86II::MRM6r: case X86II::MRM7r:
1341 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1343 EmitByte(BaseOpcode, CurByte, OS);
1344 EmitRegModRMByte(MI.getOperand(CurOp++),
1345 (TSFlags & X86II::FormMask)-X86II::MRM0r,
1348 case X86II::MRM0m: case X86II::MRM1m:
1349 case X86II::MRM2m: case X86II::MRM3m:
1350 case X86II::MRM4m: case X86II::MRM5m:
1351 case X86II::MRM6m: case X86II::MRM7m:
1352 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1354 EmitByte(BaseOpcode, CurByte, OS);
1355 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
1356 TSFlags, CurByte, OS, Fixups);
1357 CurOp += X86::AddrNumOperands;
1359 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
1360 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
1361 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
1362 case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5:
1363 case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9:
1364 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
1365 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
1366 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
1368 EmitByte(BaseOpcode, CurByte, OS);
1371 switch (TSFlags & X86II::FormMask) {
1372 default: llvm_unreachable("Invalid Form");
1373 case X86II::MRM_C1: MRM = 0xC1; break;
1374 case X86II::MRM_C2: MRM = 0xC2; break;
1375 case X86II::MRM_C3: MRM = 0xC3; break;
1376 case X86II::MRM_C4: MRM = 0xC4; break;
1377 case X86II::MRM_C8: MRM = 0xC8; break;
1378 case X86II::MRM_C9: MRM = 0xC9; break;
1379 case X86II::MRM_CA: MRM = 0xCA; break;
1380 case X86II::MRM_CB: MRM = 0xCB; break;
1381 case X86II::MRM_D0: MRM = 0xD0; break;
1382 case X86II::MRM_D1: MRM = 0xD1; break;
1383 case X86II::MRM_D4: MRM = 0xD4; break;
1384 case X86II::MRM_D5: MRM = 0xD5; break;
1385 case X86II::MRM_D6: MRM = 0xD6; break;
1386 case X86II::MRM_D8: MRM = 0xD8; break;
1387 case X86II::MRM_D9: MRM = 0xD9; break;
1388 case X86II::MRM_DA: MRM = 0xDA; break;
1389 case X86II::MRM_DB: MRM = 0xDB; break;
1390 case X86II::MRM_DC: MRM = 0xDC; break;
1391 case X86II::MRM_DD: MRM = 0xDD; break;
1392 case X86II::MRM_DE: MRM = 0xDE; break;
1393 case X86II::MRM_DF: MRM = 0xDF; break;
1394 case X86II::MRM_E8: MRM = 0xE8; break;
1395 case X86II::MRM_F0: MRM = 0xF0; break;
1396 case X86II::MRM_F8: MRM = 0xF8; break;
1397 case X86II::MRM_F9: MRM = 0xF9; break;
1399 EmitByte(MRM, CurByte, OS);
1403 // If there is a remaining operand, it must be a trailing immediate. Emit it
1404 // according to the right size for the instruction. Some instructions
1405 // (SSE4a extrq and insertq) have two trailing immediates.
1406 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1407 // The last source register of a 4 operand instruction in AVX is encoded
1408 // in bits[7:4] of a immediate byte.
1409 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1410 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1413 unsigned RegNum = GetX86RegNum(MO) << 4;
1414 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1416 // If there is an additional 5th operand it must be an immediate, which
1417 // is encoded in bits[3:0]
1418 if (CurOp != NumOps) {
1419 const MCOperand &MIMM = MI.getOperand(CurOp++);
1421 unsigned Val = MIMM.getImm();
1422 assert(Val < 16 && "Immediate operand value out of range");
1426 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1427 CurByte, OS, Fixups);
1430 // FIXME: Is there a better way to know that we need a signed relocation?
1431 if (MI.getOpcode() == X86::ADD64ri32 ||
1432 MI.getOpcode() == X86::MOV64ri32 ||
1433 MI.getOpcode() == X86::MOV64mi32 ||
1434 MI.getOpcode() == X86::PUSH64i32)
1435 FixupKind = X86::reloc_signed_4byte;
1437 FixupKind = getImmFixupKind(TSFlags);
1438 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1439 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1440 CurByte, OS, Fixups);
1444 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1445 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1449 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1450 errs() << "Cannot encode all operands of: ";