1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/raw_ostream.h"
30 class X86MCCodeEmitter : public MCCodeEmitter {
31 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
33 const MCInstrInfo &MCII;
34 const MCSubtargetInfo &STI;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
39 : MCII(mcii), STI(sti), Ctx(ctx) {
42 ~X86MCCodeEmitter() {}
44 bool is64BitMode() const {
45 // FIXME: Can tablegen auto-generate this?
46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
49 static unsigned GetX86RegNum(const MCOperand &MO) {
50 return X86_MC::getX86RegNum(MO.getReg());
53 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
54 // 0-7 and the difference between the 2 groups is given by the REX prefix.
55 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
56 // in 1's complement form, example:
58 // ModRM field => XMM9 => 1
59 // VEX.VVVV => XMM9 => ~9
61 // See table 4-35 of Intel AVX Programming Reference for details.
62 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
64 unsigned SrcReg = MI.getOperand(OpNum).getReg();
65 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
66 if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
67 (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
70 // The registers represented through VEX_VVVV should
71 // be encoded in 1's complement form.
72 return (~SrcRegNum) & 0xf;
75 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
80 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
81 raw_ostream &OS) const {
82 // Output the constant in little endian byte order.
83 for (unsigned i = 0; i != Size; ++i) {
84 EmitByte(Val & 255, CurByte, OS);
89 void EmitImmediate(const MCOperand &Disp,
90 unsigned ImmSize, MCFixupKind FixupKind,
91 unsigned &CurByte, raw_ostream &OS,
92 SmallVectorImpl<MCFixup> &Fixups,
93 int ImmOffset = 0) const;
95 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
97 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
98 return RM | (RegOpcode << 3) | (Mod << 6);
101 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
102 unsigned &CurByte, raw_ostream &OS) const {
103 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
106 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
107 unsigned &CurByte, raw_ostream &OS) const {
108 // SIB byte is in the same format as the ModRMByte.
109 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
113 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
114 unsigned RegOpcodeField,
115 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
116 SmallVectorImpl<MCFixup> &Fixups) const;
118 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
119 SmallVectorImpl<MCFixup> &Fixups) const;
121 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
122 const MCInst &MI, const MCInstrDesc &Desc,
123 raw_ostream &OS) const;
125 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
126 int MemOperand, const MCInst &MI,
127 raw_ostream &OS) const;
129 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
130 const MCInst &MI, const MCInstrDesc &Desc,
131 raw_ostream &OS) const;
134 } // end anonymous namespace
137 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
138 const MCSubtargetInfo &STI,
140 return new X86MCCodeEmitter(MCII, STI, Ctx);
143 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
144 /// sign-extended field.
145 static bool isDisp8(int Value) {
146 return Value == (signed char)Value;
149 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
150 /// in an instruction with the specified TSFlags.
151 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
152 unsigned Size = X86II::getSizeOfImm(TSFlags);
153 bool isPCRel = X86II::isImmPCRel(TSFlags);
155 return MCFixup::getKindForSize(Size, isPCRel);
158 /// Is32BitMemOperand - Return true if the specified instruction with a memory
159 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
160 /// memory operand. Op specifies the operand # of the memoperand.
161 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
162 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
163 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
165 if ((BaseReg.getReg() != 0 &&
166 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
167 (IndexReg.getReg() != 0 &&
168 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
173 /// StartsWithGlobalOffsetTable - Return true for the simple cases where this
174 /// expression starts with _GLOBAL_OFFSET_TABLE_. This is a needed to support
175 /// PIC on ELF i386 as that symbol is magic. We check only simple case that
176 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
177 /// of a binary expression.
178 static bool StartsWithGlobalOffsetTable(const MCExpr *Expr) {
179 if (Expr->getKind() == MCExpr::Binary) {
180 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
184 if (Expr->getKind() != MCExpr::SymbolRef)
187 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
188 const MCSymbol &S = Ref->getSymbol();
189 return S.getName() == "_GLOBAL_OFFSET_TABLE_";
192 void X86MCCodeEmitter::
193 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
194 unsigned &CurByte, raw_ostream &OS,
195 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
196 const MCExpr *Expr = NULL;
197 if (DispOp.isImm()) {
198 // If this is a simple integer displacement that doesn't require a
199 // relocation, emit it now.
200 if (FixupKind != FK_PCRel_1 &&
201 FixupKind != FK_PCRel_2 &&
202 FixupKind != FK_PCRel_4) {
203 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
206 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
208 Expr = DispOp.getExpr();
211 // If we have an immoffset, add it to the expression.
212 if ((FixupKind == FK_Data_4 ||
213 FixupKind == MCFixupKind(X86::reloc_signed_4byte)) &&
214 StartsWithGlobalOffsetTable(Expr)) {
215 assert(ImmOffset == 0);
217 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
221 // If the fixup is pc-relative, we need to bias the value to be relative to
222 // the start of the field, not the end of the field.
223 if (FixupKind == FK_PCRel_4 ||
224 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
225 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
227 if (FixupKind == FK_PCRel_2)
229 if (FixupKind == FK_PCRel_1)
233 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
236 // Emit a symbolic constant as a fixup and 4 zeros.
237 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
238 EmitConstant(0, Size, CurByte, OS);
241 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
242 unsigned RegOpcodeField,
243 uint64_t TSFlags, unsigned &CurByte,
245 SmallVectorImpl<MCFixup> &Fixups) const{
246 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
247 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
248 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
249 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
250 unsigned BaseReg = Base.getReg();
252 // Handle %rip relative addressing.
253 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
254 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
255 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
256 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
258 unsigned FixupKind = X86::reloc_riprel_4byte;
260 // movq loads are handled with a special relocation form which allows the
261 // linker to eliminate some loads for GOT references which end up in the
262 // same linkage unit.
263 if (MI.getOpcode() == X86::MOV64rm)
264 FixupKind = X86::reloc_riprel_4byte_movq_load;
266 // rip-relative addressing is actually relative to the *next* instruction.
267 // Since an immediate can follow the mod/rm byte for an instruction, this
268 // means that we need to bias the immediate field of the instruction with
269 // the size of the immediate field. If we have this case, add it into the
270 // expression to emit.
271 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
273 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
274 CurByte, OS, Fixups, -ImmSize);
278 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
280 // Determine whether a SIB byte is needed.
281 // If no BaseReg, issue a RIP relative instruction only if the MCE can
282 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
283 // 2-7) and absolute references.
285 if (// The SIB byte must be used if there is an index register.
286 IndexReg.getReg() == 0 &&
287 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
288 // encode to an R/M value of 4, which indicates that a SIB byte is
290 BaseRegNo != N86::ESP &&
291 // If there is no base register and we're in 64-bit mode, we need a SIB
292 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
293 (!is64BitMode() || BaseReg != 0)) {
295 if (BaseReg == 0) { // [disp32] in X86-32 mode
296 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
297 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
301 // If the base is not EBP/ESP and there is no displacement, use simple
302 // indirect register encoding, this handles addresses like [EAX]. The
303 // encoding for [EBP] with no displacement means [disp32] so we handle it
304 // by emitting a displacement of 0 below.
305 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
306 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
310 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
311 if (Disp.isImm() && isDisp8(Disp.getImm())) {
312 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
313 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
317 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
318 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
319 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
324 // We need a SIB byte, so start by outputting the ModR/M byte first
325 assert(IndexReg.getReg() != X86::ESP &&
326 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
328 bool ForceDisp32 = false;
329 bool ForceDisp8 = false;
331 // If there is no base register, we emit the special case SIB byte with
332 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
333 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
335 } else if (!Disp.isImm()) {
336 // Emit the normal disp32 encoding.
337 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
339 } else if (Disp.getImm() == 0 &&
340 // Base reg can't be anything that ends up with '5' as the base
341 // reg, it is the magic [*] nomenclature that indicates no base.
342 BaseRegNo != N86::EBP) {
343 // Emit no displacement ModR/M byte
344 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
345 } else if (isDisp8(Disp.getImm())) {
346 // Emit the disp8 encoding.
347 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
348 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
350 // Emit the normal disp32 encoding.
351 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
354 // Calculate what the SS field value should be...
355 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
356 unsigned SS = SSTable[Scale.getImm()];
359 // Handle the SIB byte for the case where there is no base, see Intel
360 // Manual 2A, table 2-7. The displacement has already been output.
362 if (IndexReg.getReg())
363 IndexRegNo = GetX86RegNum(IndexReg);
364 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
366 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
369 if (IndexReg.getReg())
370 IndexRegNo = GetX86RegNum(IndexReg);
372 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
373 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
376 // Do we need to output a displacement?
378 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
379 else if (ForceDisp32 || Disp.getImm() != 0)
380 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
384 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
386 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
387 int MemOperand, const MCInst &MI,
388 const MCInstrDesc &Desc,
389 raw_ostream &OS) const {
390 bool HasVEX_4V = false;
391 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
394 // VEX_R: opcode externsion equivalent to REX.R in
395 // 1's complement (inverted) form
397 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
398 // 0: Same as REX_R=1 (64 bit mode only)
400 unsigned char VEX_R = 0x1;
402 // VEX_X: equivalent to REX.X, only used when a
403 // register is used for index in SIB Byte.
405 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
406 // 0: Same as REX.X=1 (64-bit mode only)
407 unsigned char VEX_X = 0x1;
411 // 1: Same as REX_B=0 (ignored in 32-bit mode)
412 // 0: Same as REX_B=1 (64 bit mode only)
414 unsigned char VEX_B = 0x1;
416 // VEX_W: opcode specific (use like REX.W, or used for
417 // opcode extension, or ignored, depending on the opcode byte)
418 unsigned char VEX_W = 0;
420 // VEX_5M (VEX m-mmmmm field):
422 // 0b00000: Reserved for future use
423 // 0b00001: implied 0F leading opcode
424 // 0b00010: implied 0F 38 leading opcode bytes
425 // 0b00011: implied 0F 3A leading opcode bytes
426 // 0b00100-0b11111: Reserved for future use
428 unsigned char VEX_5M = 0x1;
430 // VEX_4V (VEX vvvv field): a register specifier
431 // (in 1's complement form) or 1111 if unused.
432 unsigned char VEX_4V = 0xf;
434 // VEX_L (Vector Length):
436 // 0: scalar or 128-bit vector
439 unsigned char VEX_L = 0;
441 // VEX_PP: opcode extension providing equivalent
442 // functionality of a SIMD prefix
449 unsigned char VEX_PP = 0;
451 // Encode the operand size opcode prefix as needed.
452 if (TSFlags & X86II::OpSize)
455 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
458 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
461 switch (TSFlags & X86II::Op0Mask) {
462 default: assert(0 && "Invalid prefix!");
463 case X86II::T8: // 0F 38
466 case X86II::TA: // 0F 3A
469 case X86II::TF: // F2 0F 38
473 case X86II::XS: // F3 0F
476 case X86II::XD: // F2 0F
479 case X86II::A6: // Bypass: Not used by VEX
480 case X86II::A7: // Bypass: Not used by VEX
481 case X86II::TB: // Bypass: Not used by VEX
486 // Set the vector length to 256-bit if YMM0-YMM15 is used
487 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
488 if (!MI.getOperand(i).isReg())
490 unsigned SrcReg = MI.getOperand(i).getReg();
491 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
495 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
497 switch (TSFlags & X86II::FormMask) {
498 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
499 case X86II::MRMDestMem: {
500 // MRMDestMem instructions forms:
501 // MemAddr, src1(ModR/M)
502 // MemAddr, src1(VEX_4V), src2(ModR/M)
503 // MemAddr, src1(ModR/M), imm8
505 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
507 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
510 CurOp = X86::AddrNumOperands;
512 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
514 const MCOperand &MO = MI.getOperand(CurOp);
515 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
519 case X86II::MRMSrcMem: {
520 // MRMSrcMem instructions forms:
521 // src1(ModR/M), MemAddr
522 // src1(ModR/M), src2(VEX_4V), MemAddr
523 // src1(ModR/M), MemAddr, imm8
524 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
526 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
529 unsigned MemAddrOffset = 1;
531 VEX_4V = getVEXRegisterEncoding(MI, 1);
535 if (X86II::isX86_64ExtendedReg(
536 MI.getOperand(MemAddrOffset+X86::AddrBaseReg).getReg()))
538 if (X86II::isX86_64ExtendedReg(
539 MI.getOperand(MemAddrOffset+X86::AddrIndexReg).getReg()))
543 case X86II::MRM0m: case X86II::MRM1m:
544 case X86II::MRM2m: case X86II::MRM3m:
545 case X86II::MRM4m: case X86II::MRM5m:
546 case X86II::MRM6m: case X86II::MRM7m:
547 // MRM[0-9]m instructions forms:
549 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
551 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
554 case X86II::MRMSrcReg:
555 // MRMSrcReg instructions forms:
556 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
557 // dst(ModR/M), src1(ModR/M)
558 // dst(ModR/M), src1(ModR/M), imm8
560 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
565 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
566 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
569 case X86II::MRMDestReg:
570 // MRMDestReg instructions forms:
571 // dst(ModR/M), src(ModR/M)
572 // dst(ModR/M), src(ModR/M), imm8
573 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
575 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
578 case X86II::MRM0r: case X86II::MRM1r:
579 case X86II::MRM2r: case X86II::MRM3r:
580 case X86II::MRM4r: case X86II::MRM5r:
581 case X86II::MRM6r: case X86II::MRM7r:
582 // MRM0r-MRM7r instructions forms:
583 // dst(VEX_4V), src(ModR/M), imm8
584 VEX_4V = getVEXRegisterEncoding(MI, 0);
585 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
592 // Emit segment override opcode prefix as needed.
593 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
595 // VEX opcode prefix can have 2 or 3 bytes
598 // +-----+ +--------------+ +-------------------+
599 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
600 // +-----+ +--------------+ +-------------------+
602 // +-----+ +-------------------+
603 // | C5h | | R | vvvv | L | pp |
604 // +-----+ +-------------------+
606 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
608 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
609 EmitByte(0xC5, CurByte, OS);
610 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
615 EmitByte(0xC4, CurByte, OS);
616 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
617 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
620 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
621 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
622 /// size, and 3) use of X86-64 extended registers.
623 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
624 const MCInstrDesc &Desc) {
626 if (TSFlags & X86II::REX_W)
627 REX |= 1 << 3; // set REX.W
629 if (MI.getNumOperands() == 0) return REX;
631 unsigned NumOps = MI.getNumOperands();
632 // FIXME: MCInst should explicitize the two-addrness.
633 bool isTwoAddr = NumOps > 1 &&
634 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
636 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
637 unsigned i = isTwoAddr ? 1 : 0;
638 for (; i != NumOps; ++i) {
639 const MCOperand &MO = MI.getOperand(i);
640 if (!MO.isReg()) continue;
641 unsigned Reg = MO.getReg();
642 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
643 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
644 // that returns non-zero.
645 REX |= 0x40; // REX fixed encoding prefix
649 switch (TSFlags & X86II::FormMask) {
650 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
651 case X86II::MRMSrcReg:
652 if (MI.getOperand(0).isReg() &&
653 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
654 REX |= 1 << 2; // set REX.R
655 i = isTwoAddr ? 2 : 1;
656 for (; i != NumOps; ++i) {
657 const MCOperand &MO = MI.getOperand(i);
658 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
659 REX |= 1 << 0; // set REX.B
662 case X86II::MRMSrcMem: {
663 if (MI.getOperand(0).isReg() &&
664 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
665 REX |= 1 << 2; // set REX.R
667 i = isTwoAddr ? 2 : 1;
668 for (; i != NumOps; ++i) {
669 const MCOperand &MO = MI.getOperand(i);
671 if (X86II::isX86_64ExtendedReg(MO.getReg()))
672 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
678 case X86II::MRM0m: case X86II::MRM1m:
679 case X86II::MRM2m: case X86II::MRM3m:
680 case X86II::MRM4m: case X86II::MRM5m:
681 case X86II::MRM6m: case X86II::MRM7m:
682 case X86II::MRMDestMem: {
683 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
684 i = isTwoAddr ? 1 : 0;
685 if (NumOps > e && MI.getOperand(e).isReg() &&
686 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
687 REX |= 1 << 2; // set REX.R
689 for (; i != e; ++i) {
690 const MCOperand &MO = MI.getOperand(i);
692 if (X86II::isX86_64ExtendedReg(MO.getReg()))
693 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
700 if (MI.getOperand(0).isReg() &&
701 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
702 REX |= 1 << 0; // set REX.B
703 i = isTwoAddr ? 2 : 1;
704 for (unsigned e = NumOps; i != e; ++i) {
705 const MCOperand &MO = MI.getOperand(i);
706 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
707 REX |= 1 << 2; // set REX.R
714 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
715 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
716 unsigned &CurByte, int MemOperand,
718 raw_ostream &OS) const {
719 switch (TSFlags & X86II::SegOvrMask) {
720 default: assert(0 && "Invalid segment!");
722 // No segment override, check for explicit one on memory operand.
723 if (MemOperand != -1) { // If the instruction has a memory operand.
724 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
725 default: assert(0 && "Unknown segment register!");
727 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
728 case X86::SS: EmitByte(0x36, CurByte, OS); break;
729 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
730 case X86::ES: EmitByte(0x26, CurByte, OS); break;
731 case X86::FS: EmitByte(0x64, CurByte, OS); break;
732 case X86::GS: EmitByte(0x65, CurByte, OS); break;
737 EmitByte(0x64, CurByte, OS);
740 EmitByte(0x65, CurByte, OS);
745 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
747 /// MemOperand is the operand # of the start of a memory operand if present. If
748 /// Not present, it is -1.
749 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
750 int MemOperand, const MCInst &MI,
751 const MCInstrDesc &Desc,
752 raw_ostream &OS) const {
754 // Emit the lock opcode prefix as needed.
755 if (TSFlags & X86II::LOCK)
756 EmitByte(0xF0, CurByte, OS);
758 // Emit segment override opcode prefix as needed.
759 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
761 // Emit the repeat opcode prefix as needed.
762 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
763 EmitByte(0xF3, CurByte, OS);
765 // Emit the address size opcode prefix as needed.
766 if ((TSFlags & X86II::AdSize) ||
767 (MemOperand != -1 && is64BitMode() && Is32BitMemOperand(MI, MemOperand)))
768 EmitByte(0x67, CurByte, OS);
770 // Emit the operand size opcode prefix as needed.
771 if (TSFlags & X86II::OpSize)
772 EmitByte(0x66, CurByte, OS);
774 bool Need0FPrefix = false;
775 switch (TSFlags & X86II::Op0Mask) {
776 default: assert(0 && "Invalid prefix!");
777 case 0: break; // No prefix!
778 case X86II::REP: break; // already handled.
779 case X86II::TB: // Two-byte opcode prefix
780 case X86II::T8: // 0F 38
781 case X86II::TA: // 0F 3A
782 case X86II::A6: // 0F A6
783 case X86II::A7: // 0F A7
786 case X86II::TF: // F2 0F 38
787 EmitByte(0xF2, CurByte, OS);
790 case X86II::XS: // F3 0F
791 EmitByte(0xF3, CurByte, OS);
794 case X86II::XD: // F2 0F
795 EmitByte(0xF2, CurByte, OS);
798 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
799 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
800 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
801 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
802 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
803 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
804 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
805 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
808 // Handle REX prefix.
809 // FIXME: Can this come before F2 etc to simplify emission?
811 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
812 EmitByte(0x40 | REX, CurByte, OS);
815 // 0x0F escape code must be emitted just before the opcode.
817 EmitByte(0x0F, CurByte, OS);
819 // FIXME: Pull this up into previous switch if REX can be moved earlier.
820 switch (TSFlags & X86II::Op0Mask) {
821 case X86II::TF: // F2 0F 38
822 case X86II::T8: // 0F 38
823 EmitByte(0x38, CurByte, OS);
825 case X86II::TA: // 0F 3A
826 EmitByte(0x3A, CurByte, OS);
828 case X86II::A6: // 0F A6
829 EmitByte(0xA6, CurByte, OS);
831 case X86II::A7: // 0F A7
832 EmitByte(0xA7, CurByte, OS);
837 void X86MCCodeEmitter::
838 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
839 SmallVectorImpl<MCFixup> &Fixups) const {
840 unsigned Opcode = MI.getOpcode();
841 const MCInstrDesc &Desc = MCII.get(Opcode);
842 uint64_t TSFlags = Desc.TSFlags;
844 // Pseudo instructions don't get encoded.
845 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
848 // If this is a two-address instruction, skip one of the register operands.
849 // FIXME: This should be handled during MCInst lowering.
850 unsigned NumOps = Desc.getNumOperands();
852 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1)
854 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0)
855 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
858 // Keep track of the current byte being emitted.
859 unsigned CurByte = 0;
861 // Is this instruction encoded using the AVX VEX prefix?
862 bool HasVEXPrefix = false;
864 // It uses the VEX.VVVV field?
865 bool HasVEX_4V = false;
867 if ((TSFlags >> X86II::VEXShift) & X86II::VEX)
869 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
873 // Determine where the memory operand starts, if present.
874 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
875 if (MemoryOperand != -1) MemoryOperand += CurOp;
878 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
880 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
883 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
885 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
886 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
888 unsigned SrcRegNum = 0;
889 switch (TSFlags & X86II::FormMask) {
890 case X86II::MRMInitReg:
891 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
892 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
893 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
895 assert(0 && "Pseudo instruction shouldn't be emitted");
897 EmitByte(BaseOpcode, CurByte, OS);
900 case X86II::RawFrmImm8:
901 EmitByte(BaseOpcode, CurByte, OS);
902 EmitImmediate(MI.getOperand(CurOp++),
903 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
904 CurByte, OS, Fixups);
905 EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups);
907 case X86II::RawFrmImm16:
908 EmitByte(BaseOpcode, CurByte, OS);
909 EmitImmediate(MI.getOperand(CurOp++),
910 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
911 CurByte, OS, Fixups);
912 EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups);
915 case X86II::AddRegFrm:
916 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
919 case X86II::MRMDestReg:
920 EmitByte(BaseOpcode, CurByte, OS);
921 EmitRegModRMByte(MI.getOperand(CurOp),
922 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
926 case X86II::MRMDestMem:
927 EmitByte(BaseOpcode, CurByte, OS);
928 SrcRegNum = CurOp + X86::AddrNumOperands;
930 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
933 EmitMemModRMByte(MI, CurOp,
934 GetX86RegNum(MI.getOperand(SrcRegNum)),
935 TSFlags, CurByte, OS, Fixups);
936 CurOp = SrcRegNum + 1;
939 case X86II::MRMSrcReg:
940 EmitByte(BaseOpcode, CurByte, OS);
941 SrcRegNum = CurOp + 1;
943 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
946 EmitRegModRMByte(MI.getOperand(SrcRegNum),
947 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
948 CurOp = SrcRegNum + 1;
951 case X86II::MRMSrcMem: {
952 int AddrOperands = X86::AddrNumOperands;
953 unsigned FirstMemOp = CurOp+1;
956 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
959 EmitByte(BaseOpcode, CurByte, OS);
961 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
962 TSFlags, CurByte, OS, Fixups);
963 CurOp += AddrOperands + 1;
967 case X86II::MRM0r: case X86II::MRM1r:
968 case X86II::MRM2r: case X86II::MRM3r:
969 case X86II::MRM4r: case X86II::MRM5r:
970 case X86II::MRM6r: case X86II::MRM7r:
971 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
973 EmitByte(BaseOpcode, CurByte, OS);
974 EmitRegModRMByte(MI.getOperand(CurOp++),
975 (TSFlags & X86II::FormMask)-X86II::MRM0r,
978 case X86II::MRM0m: case X86II::MRM1m:
979 case X86II::MRM2m: case X86II::MRM3m:
980 case X86II::MRM4m: case X86II::MRM5m:
981 case X86II::MRM6m: case X86II::MRM7m:
982 EmitByte(BaseOpcode, CurByte, OS);
983 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
984 TSFlags, CurByte, OS, Fixups);
985 CurOp += X86::AddrNumOperands;
988 EmitByte(BaseOpcode, CurByte, OS);
989 EmitByte(0xC1, CurByte, OS);
992 EmitByte(BaseOpcode, CurByte, OS);
993 EmitByte(0xC2, CurByte, OS);
996 EmitByte(BaseOpcode, CurByte, OS);
997 EmitByte(0xC3, CurByte, OS);
1000 EmitByte(BaseOpcode, CurByte, OS);
1001 EmitByte(0xC4, CurByte, OS);
1004 EmitByte(BaseOpcode, CurByte, OS);
1005 EmitByte(0xC8, CurByte, OS);
1008 EmitByte(BaseOpcode, CurByte, OS);
1009 EmitByte(0xC9, CurByte, OS);
1012 EmitByte(BaseOpcode, CurByte, OS);
1013 EmitByte(0xE8, CurByte, OS);
1016 EmitByte(BaseOpcode, CurByte, OS);
1017 EmitByte(0xF0, CurByte, OS);
1020 EmitByte(BaseOpcode, CurByte, OS);
1021 EmitByte(0xF8, CurByte, OS);
1024 EmitByte(BaseOpcode, CurByte, OS);
1025 EmitByte(0xF9, CurByte, OS);
1028 EmitByte(BaseOpcode, CurByte, OS);
1029 EmitByte(0xD0, CurByte, OS);
1032 EmitByte(BaseOpcode, CurByte, OS);
1033 EmitByte(0xD1, CurByte, OS);
1037 // If there is a remaining operand, it must be a trailing immediate. Emit it
1038 // according to the right size for the instruction.
1039 if (CurOp != NumOps) {
1040 // The last source register of a 4 operand instruction in AVX is encoded
1041 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
1042 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1043 const MCOperand &MO = MI.getOperand(CurOp++);
1044 bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg());
1045 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
1046 RegNum |= GetX86RegNum(MO) << 4;
1047 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
1051 // FIXME: Is there a better way to know that we need a signed relocation?
1052 if (MI.getOpcode() == X86::ADD64ri32 ||
1053 MI.getOpcode() == X86::MOV64ri32 ||
1054 MI.getOpcode() == X86::MOV64mi32 ||
1055 MI.getOpcode() == X86::PUSH64i32)
1056 FixupKind = X86::reloc_signed_4byte;
1058 FixupKind = getImmFixupKind(TSFlags);
1059 EmitImmediate(MI.getOperand(CurOp++),
1060 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1061 CurByte, OS, Fixups);
1065 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1066 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1071 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1072 errs() << "Cannot encode all operands of: ";