1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Support/raw_ostream.h"
31 class X86MCCodeEmitter : public MCCodeEmitter {
32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 const MCInstrInfo &MCII;
35 const MCSubtargetInfo &STI;
38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
40 : MCII(mcii), STI(sti), Ctx(ctx) {
43 ~X86MCCodeEmitter() {}
45 bool is64BitMode() const {
46 // FIXME: Can tablegen auto-generate this?
47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
50 bool is32BitMode() const {
51 // FIXME: Can tablegen auto-generate this?
52 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
55 bool is16BitMode() const {
56 // FIXME: Can tablegen auto-generate this?
57 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
60 /// Is16BitMemOperand - Return true if the specified instruction has
61 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
62 bool Is16BitMemOperand(const MCInst &MI, unsigned Op) const {
63 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
64 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
65 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
67 if (is16BitMode() && BaseReg.getReg() == 0 &&
68 Disp.isImm() && Disp.getImm() < 0x10000)
70 if ((BaseReg.getReg() != 0 &&
71 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
72 (IndexReg.getReg() != 0 &&
73 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
78 unsigned GetX86RegNum(const MCOperand &MO) const {
79 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
82 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
83 // 0-7 and the difference between the 2 groups is given by the REX prefix.
84 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
85 // in 1's complement form, example:
87 // ModRM field => XMM9 => 1
88 // VEX.VVVV => XMM9 => ~9
90 // See table 4-35 of Intel AVX Programming Reference for details.
91 unsigned char getVEXRegisterEncoding(const MCInst &MI,
92 unsigned OpNum) const {
93 unsigned SrcReg = MI.getOperand(OpNum).getReg();
94 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
95 if (X86II::isX86_64ExtendedReg(SrcReg))
98 // The registers represented through VEX_VVVV should
99 // be encoded in 1's complement form.
100 return (~SrcRegNum) & 0xf;
103 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
104 unsigned OpNum) const {
105 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
106 "Invalid mask register as write-mask!");
107 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
111 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
116 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
117 raw_ostream &OS) const {
118 // Output the constant in little endian byte order.
119 for (unsigned i = 0; i != Size; ++i) {
120 EmitByte(Val & 255, CurByte, OS);
125 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
126 unsigned ImmSize, MCFixupKind FixupKind,
127 unsigned &CurByte, raw_ostream &OS,
128 SmallVectorImpl<MCFixup> &Fixups,
129 int ImmOffset = 0) const;
131 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
133 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
134 return RM | (RegOpcode << 3) | (Mod << 6);
137 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
138 unsigned &CurByte, raw_ostream &OS) const {
139 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
142 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
143 unsigned &CurByte, raw_ostream &OS) const {
144 // SIB byte is in the same format as the ModRMByte.
145 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
149 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
150 unsigned RegOpcodeField,
151 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
152 SmallVectorImpl<MCFixup> &Fixups) const;
154 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
155 SmallVectorImpl<MCFixup> &Fixups) const;
157 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
158 const MCInst &MI, const MCInstrDesc &Desc,
159 raw_ostream &OS) const;
161 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
162 const MCInst &MI, raw_ostream &OS) const;
164 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
165 const MCInst &MI, const MCInstrDesc &Desc,
166 raw_ostream &OS) const;
169 } // end anonymous namespace
172 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
173 const MCRegisterInfo &MRI,
174 const MCSubtargetInfo &STI,
176 return new X86MCCodeEmitter(MCII, STI, Ctx);
179 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
180 /// sign-extended field.
181 static bool isDisp8(int Value) {
182 return Value == (signed char)Value;
185 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
186 /// compressed dispacement field.
187 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
188 assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) &&
189 "Compressed 8-bit displacement is only valid for EVEX inst.");
191 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask;
192 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask;
194 if (CD8V == 0 && CD8E == 0) {
196 return isDisp8(Value);
199 unsigned MemObjSize = 1U << CD8E;
201 // Fixed vector length
202 MemObjSize *= 1U << (CD8V & 0x3);
204 // Modified vector length
205 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B;
207 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0;
208 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0;
209 assert(EVEX_LL < 3 && "");
211 unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize;
212 NumElems /= 1U << (CD8V & 0x3);
214 MemObjSize *= NumElems;
218 unsigned MemObjMask = MemObjSize - 1;
219 assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size.");
221 if (Value & MemObjMask) // Unaligned offset
224 bool Ret = (Value == (signed char)Value);
231 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
232 /// in an instruction with the specified TSFlags.
233 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
234 unsigned Size = X86II::getSizeOfImm(TSFlags);
235 bool isPCRel = X86II::isImmPCRel(TSFlags);
237 return MCFixup::getKindForSize(Size, isPCRel);
240 /// Is32BitMemOperand - Return true if the specified instruction has
241 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
242 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
243 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
244 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
246 if ((BaseReg.getReg() != 0 &&
247 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
248 (IndexReg.getReg() != 0 &&
249 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
254 /// Is64BitMemOperand - Return true if the specified instruction has
255 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
257 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
258 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
259 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
261 if ((BaseReg.getReg() != 0 &&
262 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
263 (IndexReg.getReg() != 0 &&
264 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
270 /// StartsWithGlobalOffsetTable - Check if this expression starts with
271 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
272 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
273 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
274 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
275 /// of a binary expression.
276 enum GlobalOffsetTableExprKind {
281 static GlobalOffsetTableExprKind
282 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
283 const MCExpr *RHS = 0;
284 if (Expr->getKind() == MCExpr::Binary) {
285 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
290 if (Expr->getKind() != MCExpr::SymbolRef)
293 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
294 const MCSymbol &S = Ref->getSymbol();
295 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
297 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
302 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
303 if (Expr->getKind() == MCExpr::SymbolRef) {
304 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
305 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
310 void X86MCCodeEmitter::
311 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
312 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
313 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
314 const MCExpr *Expr = NULL;
315 if (DispOp.isImm()) {
316 // If this is a simple integer displacement that doesn't require a
317 // relocation, emit it now.
318 if (FixupKind != FK_PCRel_1 &&
319 FixupKind != FK_PCRel_2 &&
320 FixupKind != FK_PCRel_4) {
321 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
324 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
326 Expr = DispOp.getExpr();
329 // If we have an immoffset, add it to the expression.
330 if ((FixupKind == FK_Data_4 ||
331 FixupKind == FK_Data_8 ||
332 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
333 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
334 if (Kind != GOT_None) {
335 assert(ImmOffset == 0);
337 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
338 if (Kind == GOT_Normal)
340 } else if (Expr->getKind() == MCExpr::SymbolRef) {
341 if (HasSecRelSymbolRef(Expr)) {
342 FixupKind = MCFixupKind(FK_SecRel_4);
344 } else if (Expr->getKind() == MCExpr::Binary) {
345 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
346 if (HasSecRelSymbolRef(Bin->getLHS())
347 || HasSecRelSymbolRef(Bin->getRHS())) {
348 FixupKind = MCFixupKind(FK_SecRel_4);
353 // If the fixup is pc-relative, we need to bias the value to be relative to
354 // the start of the field, not the end of the field.
355 if (FixupKind == FK_PCRel_4 ||
356 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
357 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
359 if (FixupKind == FK_PCRel_2)
361 if (FixupKind == FK_PCRel_1)
365 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
368 // Emit a symbolic constant as a fixup and 4 zeros.
369 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
370 EmitConstant(0, Size, CurByte, OS);
373 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
374 unsigned RegOpcodeField,
375 uint64_t TSFlags, unsigned &CurByte,
377 SmallVectorImpl<MCFixup> &Fixups) const{
378 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
379 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
380 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
381 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
382 unsigned BaseReg = Base.getReg();
383 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
385 // Handle %rip relative addressing.
386 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
387 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
388 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
389 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
391 unsigned FixupKind = X86::reloc_riprel_4byte;
393 // movq loads are handled with a special relocation form which allows the
394 // linker to eliminate some loads for GOT references which end up in the
395 // same linkage unit.
396 if (MI.getOpcode() == X86::MOV64rm)
397 FixupKind = X86::reloc_riprel_4byte_movq_load;
399 // rip-relative addressing is actually relative to the *next* instruction.
400 // Since an immediate can follow the mod/rm byte for an instruction, this
401 // means that we need to bias the immediate field of the instruction with
402 // the size of the immediate field. If we have this case, add it into the
403 // expression to emit.
404 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
406 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
407 CurByte, OS, Fixups, -ImmSize);
411 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
413 // 16-bit addressing forms of the ModR/M byte have a different encoding for
414 // the R/M field and are far more limited in which registers can be used.
415 if (Is16BitMemOperand(MI, Op)) {
417 // For 32-bit addressing, the row and column values in Table 2-2 are
418 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
419 // some special cases. And GetX86RegNum reflects that numbering.
420 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
421 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
422 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
423 // while values 0-3 indicate the allowed combinations (base+index) of
424 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
426 // R16Table[] is a lookup from the normal RegNo, to the row values from
427 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
428 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
429 unsigned RMfield = R16Table[BaseRegNo];
431 assert(RMfield && "invalid 16-bit base register");
433 if (IndexReg.getReg()) {
434 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
436 assert(IndexReg16 && "invalid 16-bit index register");
437 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
438 assert(((IndexReg16 ^ RMfield) & 2) &&
439 "invalid 16-bit base/index register combination");
440 assert(Scale.getImm() == 1 &&
441 "invalid scale for 16-bit memory reference");
443 // Allow base/index to appear in either order (although GAS doesn't).
445 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
447 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
450 if (Disp.isImm() && isDisp8(Disp.getImm())) {
451 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
452 // There is no displacement; just the register.
453 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
456 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
457 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
458 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
461 // This is the [REG]+disp16 case.
462 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
464 // There is no BaseReg; this is the plain [disp16] case.
465 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
468 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
469 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
473 // Determine whether a SIB byte is needed.
474 // If no BaseReg, issue a RIP relative instruction only if the MCE can
475 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
476 // 2-7) and absolute references.
478 if (// The SIB byte must be used if there is an index register.
479 IndexReg.getReg() == 0 &&
480 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
481 // encode to an R/M value of 4, which indicates that a SIB byte is
483 BaseRegNo != N86::ESP &&
484 // If there is no base register and we're in 64-bit mode, we need a SIB
485 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
486 (!is64BitMode() || BaseReg != 0)) {
488 if (BaseReg == 0) { // [disp32] in X86-32 mode
489 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
490 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
494 // If the base is not EBP/ESP and there is no displacement, use simple
495 // indirect register encoding, this handles addresses like [EAX]. The
496 // encoding for [EBP] with no displacement means [disp32] so we handle it
497 // by emitting a displacement of 0 below.
498 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
499 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
503 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
505 if (!HasEVEX && isDisp8(Disp.getImm())) {
506 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
507 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
510 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
511 // 32-bit displacement.
513 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
514 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
515 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
516 CDisp8 - Disp.getImm());
521 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
522 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
523 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
528 // We need a SIB byte, so start by outputting the ModR/M byte first
529 assert(IndexReg.getReg() != X86::ESP &&
530 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
532 bool ForceDisp32 = false;
533 bool ForceDisp8 = false;
537 // If there is no base register, we emit the special case SIB byte with
538 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
539 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
541 } else if (!Disp.isImm()) {
542 // Emit the normal disp32 encoding.
543 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
545 } else if (Disp.getImm() == 0 &&
546 // Base reg can't be anything that ends up with '5' as the base
547 // reg, it is the magic [*] nomenclature that indicates no base.
548 BaseRegNo != N86::EBP) {
549 // Emit no displacement ModR/M byte
550 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
551 } else if (!HasEVEX && isDisp8(Disp.getImm())) {
552 // Emit the disp8 encoding.
553 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
554 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
555 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
556 // Emit the disp8 encoding.
557 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
558 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
559 ImmOffset = CDisp8 - Disp.getImm();
561 // Emit the normal disp32 encoding.
562 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
565 // Calculate what the SS field value should be...
566 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
567 unsigned SS = SSTable[Scale.getImm()];
570 // Handle the SIB byte for the case where there is no base, see Intel
571 // Manual 2A, table 2-7. The displacement has already been output.
573 if (IndexReg.getReg())
574 IndexRegNo = GetX86RegNum(IndexReg);
575 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
577 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
580 if (IndexReg.getReg())
581 IndexRegNo = GetX86RegNum(IndexReg);
583 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
584 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
587 // Do we need to output a displacement?
589 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
590 else if (ForceDisp32 || Disp.getImm() != 0)
591 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
592 CurByte, OS, Fixups);
595 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
597 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
598 int MemOperand, const MCInst &MI,
599 const MCInstrDesc &Desc,
600 raw_ostream &OS) const {
601 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
602 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
603 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
604 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
605 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
606 bool HasEVEX_RC = (TSFlags >> X86II::VEXShift) & X86II::EVEX_RC;
608 // VEX_R: opcode externsion equivalent to REX.R in
609 // 1's complement (inverted) form
611 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
612 // 0: Same as REX_R=1 (64 bit mode only)
614 unsigned char VEX_R = 0x1;
615 unsigned char EVEX_R2 = 0x1;
617 // VEX_X: equivalent to REX.X, only used when a
618 // register is used for index in SIB Byte.
620 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
621 // 0: Same as REX.X=1 (64-bit mode only)
622 unsigned char VEX_X = 0x1;
626 // 1: Same as REX_B=0 (ignored in 32-bit mode)
627 // 0: Same as REX_B=1 (64 bit mode only)
629 unsigned char VEX_B = 0x1;
631 // VEX_W: opcode specific (use like REX.W, or used for
632 // opcode extension, or ignored, depending on the opcode byte)
633 unsigned char VEX_W = 0;
635 // XOP: Use XOP prefix byte 0x8f instead of VEX.
636 bool XOP = (TSFlags >> X86II::VEXShift) & X86II::XOP;
638 // VEX_5M (VEX m-mmmmm field):
640 // 0b00000: Reserved for future use
641 // 0b00001: implied 0F leading opcode
642 // 0b00010: implied 0F 38 leading opcode bytes
643 // 0b00011: implied 0F 3A leading opcode bytes
644 // 0b00100-0b11111: Reserved for future use
645 // 0b01000: XOP map select - 08h instructions with imm byte
646 // 0b01001: XOP map select - 09h instructions with no imm byte
647 // 0b01010: XOP map select - 0Ah instructions with imm dword
648 unsigned char VEX_5M = 0x1;
650 // VEX_4V (VEX vvvv field): a register specifier
651 // (in 1's complement form) or 1111 if unused.
652 unsigned char VEX_4V = 0xf;
653 unsigned char EVEX_V2 = 0x1;
655 // VEX_L (Vector Length):
657 // 0: scalar or 128-bit vector
660 unsigned char VEX_L = 0;
661 unsigned char EVEX_L2 = 0;
663 // VEX_PP: opcode extension providing equivalent
664 // functionality of a SIMD prefix
671 unsigned char VEX_PP = 0;
674 unsigned char EVEX_U = 1; // Always '1' so far
677 unsigned char EVEX_z = 0;
680 unsigned char EVEX_b = 0;
683 unsigned char EVEX_rc = 0;
686 unsigned char EVEX_aaa = 0;
688 bool EncodeRC = false;
690 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
693 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
695 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
698 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z))
701 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_B))
704 switch (TSFlags & X86II::Op0Mask) {
705 default: llvm_unreachable("Invalid prefix!");
706 case X86II::T8: // 0F 38
709 case X86II::TA: // 0F 3A
712 case X86II::T8PD: // 66 0F 38
716 case X86II::T8XS: // F3 0F 38
720 case X86II::T8XD: // F2 0F 38
724 case X86II::TAPD: // 66 0F 3A
728 case X86II::TAXD: // F2 0F 3A
732 case X86II::PD: // 66 0F
735 case X86II::XS: // F3 0F
738 case X86II::XD: // F2 0F
750 case X86II::TB: // VEX_5M/VEX_PP already correct
755 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
756 unsigned NumOps = Desc.getNumOperands();
757 unsigned CurOp = X86II::getOperandBias(Desc);
759 switch (TSFlags & X86II::FormMask) {
760 default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!");
763 case X86II::MRMDestMem: {
764 // MRMDestMem instructions forms:
765 // MemAddr, src1(ModR/M)
766 // MemAddr, src1(VEX_4V), src2(ModR/M)
767 // MemAddr, src1(ModR/M), imm8
769 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
770 X86::AddrBaseReg).getReg()))
772 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
773 X86::AddrIndexReg).getReg()))
775 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
776 X86::AddrIndexReg).getReg()))
779 CurOp += X86::AddrNumOperands;
782 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
785 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
786 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
791 const MCOperand &MO = MI.getOperand(CurOp);
793 if (X86II::isX86_64ExtendedReg(MO.getReg()))
795 if (HasEVEX && X86II::is32ExtendedReg(MO.getReg()))
800 case X86II::MRMSrcMem:
801 // MRMSrcMem instructions forms:
802 // src1(ModR/M), MemAddr
803 // src1(ModR/M), src2(VEX_4V), MemAddr
804 // src1(ModR/M), MemAddr, imm8
805 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
808 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
809 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
810 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
812 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
817 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
820 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
821 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
826 if (X86II::isX86_64ExtendedReg(
827 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
829 if (X86II::isX86_64ExtendedReg(
830 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
832 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
833 X86::AddrIndexReg).getReg()))
837 // Instruction format for 4VOp3:
838 // src1(ModR/M), MemAddr, src3(VEX_4V)
839 // CurOp points to start of the MemoryOperand,
840 // it skips TIED_TO operands if exist, then increments past src1.
841 // CurOp + X86::AddrNumOperands will point to src3.
842 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
844 case X86II::MRM0m: case X86II::MRM1m:
845 case X86II::MRM2m: case X86II::MRM3m:
846 case X86II::MRM4m: case X86II::MRM5m:
847 case X86II::MRM6m: case X86II::MRM7m: {
848 // MRM[0-9]m instructions forms:
850 // src1(VEX_4V), MemAddr
852 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
853 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
859 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
861 if (X86II::isX86_64ExtendedReg(
862 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
864 if (X86II::isX86_64ExtendedReg(
865 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
869 case X86II::MRMSrcReg:
870 // MRMSrcReg instructions forms:
871 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
872 // dst(ModR/M), src1(ModR/M)
873 // dst(ModR/M), src1(ModR/M), imm8
876 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
877 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
878 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
880 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
885 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
888 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
889 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
894 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
897 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
899 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
903 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
906 unsigned RcOperand = NumOps-1;
907 assert(RcOperand >= CurOp);
908 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
913 case X86II::MRMDestReg:
914 // MRMDestReg instructions forms:
915 // dst(ModR/M), src(ModR/M)
916 // dst(ModR/M), src(ModR/M), imm8
917 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
918 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
920 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
925 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
928 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
929 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
934 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
936 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
941 case X86II::MRM0r: case X86II::MRM1r:
942 case X86II::MRM2r: case X86II::MRM3r:
943 case X86II::MRM4r: case X86II::MRM5r:
944 case X86II::MRM6r: case X86II::MRM7r:
945 // MRM0r-MRM7r instructions forms:
946 // dst(VEX_4V), src(ModR/M), imm8
948 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
949 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
954 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
956 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
958 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
963 // Emit segment override opcode prefix as needed.
965 EmitSegmentOverridePrefix(CurByte, MemOperand+X86::AddrSegmentReg, MI, OS);
968 // VEX opcode prefix can have 2 or 3 bytes
971 // +-----+ +--------------+ +-------------------+
972 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
973 // +-----+ +--------------+ +-------------------+
975 // +-----+ +-------------------+
976 // | C5h | | R | vvvv | L | pp |
977 // +-----+ +-------------------+
979 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
981 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
982 EmitByte(0xC5, CurByte, OS);
983 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
988 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
989 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
990 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
992 // EVEX opcode prefix can have 4 bytes
994 // +-----+ +--------------+ +-------------------+ +------------------------+
995 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
996 // +-----+ +--------------+ +-------------------+ +------------------------+
997 assert((VEX_5M & 0x3) == VEX_5M
998 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
1002 EmitByte(0x62, CurByte, OS);
1003 EmitByte((VEX_R << 7) |
1007 VEX_5M, CurByte, OS);
1008 EmitByte((VEX_W << 7) |
1011 VEX_PP, CurByte, OS);
1013 EmitByte((EVEX_z << 7) |
1017 EVEX_aaa, CurByte, OS);
1019 EmitByte((EVEX_z << 7) |
1024 EVEX_aaa, CurByte, OS);
1028 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
1029 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
1030 /// size, and 3) use of X86-64 extended registers.
1031 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1032 const MCInstrDesc &Desc) {
1034 if (TSFlags & X86II::REX_W)
1035 REX |= 1 << 3; // set REX.W
1037 if (MI.getNumOperands() == 0) return REX;
1039 unsigned NumOps = MI.getNumOperands();
1040 // FIXME: MCInst should explicitize the two-addrness.
1041 bool isTwoAddr = NumOps > 1 &&
1042 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
1044 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1045 unsigned i = isTwoAddr ? 1 : 0;
1046 for (; i != NumOps; ++i) {
1047 const MCOperand &MO = MI.getOperand(i);
1048 if (!MO.isReg()) continue;
1049 unsigned Reg = MO.getReg();
1050 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
1051 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1052 // that returns non-zero.
1053 REX |= 0x40; // REX fixed encoding prefix
1057 switch (TSFlags & X86II::FormMask) {
1058 case X86II::MRMSrcReg:
1059 if (MI.getOperand(0).isReg() &&
1060 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1061 REX |= 1 << 2; // set REX.R
1062 i = isTwoAddr ? 2 : 1;
1063 for (; i != NumOps; ++i) {
1064 const MCOperand &MO = MI.getOperand(i);
1065 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1066 REX |= 1 << 0; // set REX.B
1069 case X86II::MRMSrcMem: {
1070 if (MI.getOperand(0).isReg() &&
1071 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1072 REX |= 1 << 2; // set REX.R
1074 i = isTwoAddr ? 2 : 1;
1075 for (; i != NumOps; ++i) {
1076 const MCOperand &MO = MI.getOperand(i);
1078 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1079 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
1085 case X86II::MRM0m: case X86II::MRM1m:
1086 case X86II::MRM2m: case X86II::MRM3m:
1087 case X86II::MRM4m: case X86II::MRM5m:
1088 case X86II::MRM6m: case X86II::MRM7m:
1089 case X86II::MRMDestMem: {
1090 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
1091 i = isTwoAddr ? 1 : 0;
1092 if (NumOps > e && MI.getOperand(e).isReg() &&
1093 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
1094 REX |= 1 << 2; // set REX.R
1096 for (; i != e; ++i) {
1097 const MCOperand &MO = MI.getOperand(i);
1099 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1100 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
1107 if (MI.getOperand(0).isReg() &&
1108 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1109 REX |= 1 << 0; // set REX.B
1110 i = isTwoAddr ? 2 : 1;
1111 for (unsigned e = NumOps; i != e; ++i) {
1112 const MCOperand &MO = MI.getOperand(i);
1113 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1114 REX |= 1 << 2; // set REX.R
1121 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1122 void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1123 unsigned SegOperand,
1125 raw_ostream &OS) const {
1126 // Check for explicit segment override on memory operand.
1127 switch (MI.getOperand(SegOperand).getReg()) {
1128 default: llvm_unreachable("Unknown segment register!");
1130 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1131 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1132 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1133 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1134 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1135 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1139 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1141 /// MemOperand is the operand # of the start of a memory operand if present. If
1142 /// Not present, it is -1.
1143 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1144 int MemOperand, const MCInst &MI,
1145 const MCInstrDesc &Desc,
1146 raw_ostream &OS) const {
1148 // Emit the lock opcode prefix as needed.
1149 if (TSFlags & X86II::LOCK)
1150 EmitByte(0xF0, CurByte, OS);
1152 // Emit segment override opcode prefix as needed.
1153 if (MemOperand >= 0)
1154 EmitSegmentOverridePrefix(CurByte, MemOperand+X86::AddrSegmentReg, MI, OS);
1156 // Emit the repeat opcode prefix as needed.
1157 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
1158 EmitByte(0xF3, CurByte, OS);
1160 // Emit the address size opcode prefix as needed.
1161 bool need_address_override;
1162 // The AdSize prefix is only for 32-bit and 64-bit modes. Hm, perhaps we
1163 // should introduce an AdSize16 bit instead of having seven special cases?
1164 if ((!is16BitMode() && TSFlags & X86II::AdSize) ||
1165 (is16BitMode() && (MI.getOpcode() == X86::JECXZ_32 ||
1166 MI.getOpcode() == X86::MOV8o8a ||
1167 MI.getOpcode() == X86::MOV16o16a ||
1168 MI.getOpcode() == X86::MOV32o32a ||
1169 MI.getOpcode() == X86::MOV8ao8 ||
1170 MI.getOpcode() == X86::MOV16ao16 ||
1171 MI.getOpcode() == X86::MOV32ao32))) {
1172 need_address_override = true;
1173 } else if (MemOperand == -1) {
1174 need_address_override = false;
1175 } else if (is64BitMode()) {
1176 assert(!Is16BitMemOperand(MI, MemOperand));
1177 need_address_override = Is32BitMemOperand(MI, MemOperand);
1178 } else if (is32BitMode()) {
1179 assert(!Is64BitMemOperand(MI, MemOperand));
1180 need_address_override = Is16BitMemOperand(MI, MemOperand);
1182 assert(is16BitMode());
1183 assert(!Is64BitMemOperand(MI, MemOperand));
1184 need_address_override = !Is16BitMemOperand(MI, MemOperand);
1187 if (need_address_override)
1188 EmitByte(0x67, CurByte, OS);
1190 // Emit the operand size opcode prefix as needed.
1191 if (TSFlags & (is16BitMode() ? X86II::OpSize16 : X86II::OpSize))
1192 EmitByte(0x66, CurByte, OS);
1194 bool Need0FPrefix = false;
1195 switch (TSFlags & X86II::Op0Mask) {
1196 default: llvm_unreachable("Invalid prefix!");
1197 case 0: break; // No prefix!
1198 case X86II::REP: break; // already handled.
1199 case X86II::TB: // Two-byte opcode prefix
1200 case X86II::T8: // 0F 38
1201 case X86II::TA: // 0F 3A
1202 case X86II::A6: // 0F A6
1203 case X86II::A7: // 0F A7
1204 Need0FPrefix = true;
1206 case X86II::PD: // 66 0F
1207 case X86II::T8PD: // 66 0F 38
1208 case X86II::TAPD: // 66 0F 3A
1209 EmitByte(0x66, CurByte, OS);
1210 Need0FPrefix = true;
1212 case X86II::XS: // F3 0F
1213 case X86II::T8XS: // F3 0F 38
1214 EmitByte(0xF3, CurByte, OS);
1215 Need0FPrefix = true;
1217 case X86II::XD: // F2 0F
1218 case X86II::T8XD: // F2 0F 38
1219 case X86II::TAXD: // F2 0F 3A
1220 EmitByte(0xF2, CurByte, OS);
1221 Need0FPrefix = true;
1231 EmitByte(0xD8+(((TSFlags & X86II::Op0Mask) - X86II::D8) >> X86II::Op0Shift),
1236 // Handle REX prefix.
1237 // FIXME: Can this come before F2 etc to simplify emission?
1238 if (is64BitMode()) {
1239 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
1240 EmitByte(0x40 | REX, CurByte, OS);
1243 // 0x0F escape code must be emitted just before the opcode.
1245 EmitByte(0x0F, CurByte, OS);
1247 // FIXME: Pull this up into previous switch if REX can be moved earlier.
1248 switch (TSFlags & X86II::Op0Mask) {
1249 case X86II::T8PD: // 66 0F 38
1250 case X86II::T8XS: // F3 0F 38
1251 case X86II::T8XD: // F2 0F 38
1252 case X86II::T8: // 0F 38
1253 EmitByte(0x38, CurByte, OS);
1255 case X86II::TAPD: // 66 0F 3A
1256 case X86II::TAXD: // F2 0F 3A
1257 case X86II::TA: // 0F 3A
1258 EmitByte(0x3A, CurByte, OS);
1260 case X86II::A6: // 0F A6
1261 EmitByte(0xA6, CurByte, OS);
1263 case X86II::A7: // 0F A7
1264 EmitByte(0xA7, CurByte, OS);
1269 void X86MCCodeEmitter::
1270 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1271 SmallVectorImpl<MCFixup> &Fixups) const {
1272 unsigned Opcode = MI.getOpcode();
1273 const MCInstrDesc &Desc = MCII.get(Opcode);
1274 uint64_t TSFlags = Desc.TSFlags;
1276 // Pseudo instructions don't get encoded.
1277 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1280 unsigned NumOps = Desc.getNumOperands();
1281 unsigned CurOp = X86II::getOperandBias(Desc);
1283 // Keep track of the current byte being emitted.
1284 unsigned CurByte = 0;
1286 // Is this instruction encoded using the AVX VEX prefix?
1287 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX;
1289 // It uses the VEX.VVVV field?
1290 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
1291 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
1292 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
1293 const unsigned MemOp4_I8IMMOperand = 2;
1295 // It uses the EVEX.aaa field?
1296 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
1297 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
1298 bool HasEVEX_RC = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_RC);
1300 // Determine where the memory operand starts, if present.
1301 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1302 if (MemoryOperand != -1) MemoryOperand += CurOp;
1305 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1307 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1309 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1311 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1312 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1314 unsigned SrcRegNum = 0;
1315 switch (TSFlags & X86II::FormMask) {
1316 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1317 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1319 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1320 case X86II::RawFrmDstSrc: {
1321 unsigned diReg = MI.getOperand(0).getReg();
1322 unsigned siReg = MI.getOperand(1).getReg();
1323 assert(((siReg == X86::SI && diReg == X86::DI) ||
1324 (siReg == X86::ESI && diReg == X86::EDI) ||
1325 (siReg == X86::RSI && diReg == X86::RDI)) &&
1326 "SI and DI register sizes do not match");
1327 // Emit segment override opcode prefix as needed (not for %ds).
1328 if (MI.getOperand(2).getReg() != X86::DS)
1329 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1330 // Emit OpSize prefix as needed.
1331 if ((!is32BitMode() && siReg == X86::ESI) ||
1332 (is32BitMode() && siReg == X86::SI))
1333 EmitByte(0x67, CurByte, OS);
1334 CurOp += 3; // Consume operands.
1335 EmitByte(BaseOpcode, CurByte, OS);
1338 case X86II::RawFrmSrc: {
1339 unsigned siReg = MI.getOperand(0).getReg();
1340 // Emit segment override opcode prefix as needed (not for %ds).
1341 if (MI.getOperand(1).getReg() != X86::DS)
1342 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1343 // Emit OpSize prefix as needed.
1344 if ((!is32BitMode() && siReg == X86::ESI) ||
1345 (is32BitMode() && siReg == X86::SI))
1346 EmitByte(0x67, CurByte, OS);
1347 CurOp += 2; // Consume operands.
1348 EmitByte(BaseOpcode, CurByte, OS);
1351 case X86II::RawFrmDst: {
1352 unsigned siReg = MI.getOperand(0).getReg();
1353 // Emit OpSize prefix as needed.
1354 if ((!is32BitMode() && siReg == X86::EDI) ||
1355 (is32BitMode() && siReg == X86::DI))
1356 EmitByte(0x67, CurByte, OS);
1357 ++CurOp; // Consume operand.
1358 EmitByte(BaseOpcode, CurByte, OS);
1362 EmitByte(BaseOpcode, CurByte, OS);
1364 case X86II::RawFrmMemOffs:
1365 // Emit segment override opcode prefix as needed.
1366 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1367 EmitByte(BaseOpcode, CurByte, OS);
1368 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1369 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1370 CurByte, OS, Fixups);
1371 ++CurOp; // skip segment operand
1373 case X86II::RawFrmImm8:
1374 EmitByte(BaseOpcode, CurByte, OS);
1375 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1376 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1377 CurByte, OS, Fixups);
1378 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1381 case X86II::RawFrmImm16:
1382 EmitByte(BaseOpcode, CurByte, OS);
1383 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1384 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1385 CurByte, OS, Fixups);
1386 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1390 case X86II::AddRegFrm:
1391 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1394 case X86II::MRMDestReg:
1395 EmitByte(BaseOpcode, CurByte, OS);
1396 SrcRegNum = CurOp + 1;
1398 if (HasEVEX_K) // Skip writemask
1401 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1404 EmitRegModRMByte(MI.getOperand(CurOp),
1405 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1406 CurOp = SrcRegNum + 1;
1409 case X86II::MRMDestMem:
1410 EmitByte(BaseOpcode, CurByte, OS);
1411 SrcRegNum = CurOp + X86::AddrNumOperands;
1413 if (HasEVEX_K) // Skip writemask
1416 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1419 EmitMemModRMByte(MI, CurOp,
1420 GetX86RegNum(MI.getOperand(SrcRegNum)),
1421 TSFlags, CurByte, OS, Fixups);
1422 CurOp = SrcRegNum + 1;
1425 case X86II::MRMSrcReg:
1426 EmitByte(BaseOpcode, CurByte, OS);
1427 SrcRegNum = CurOp + 1;
1429 if (HasEVEX_K) // Skip writemask
1432 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1435 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1438 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1439 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1441 // 2 operands skipped with HasMemOp4, compensate accordingly
1442 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1445 // do not count the rounding control operand
1450 case X86II::MRMSrcMem: {
1451 int AddrOperands = X86::AddrNumOperands;
1452 unsigned FirstMemOp = CurOp+1;
1454 if (HasEVEX_K) { // Skip writemask
1461 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1463 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1466 EmitByte(BaseOpcode, CurByte, OS);
1468 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1469 TSFlags, CurByte, OS, Fixups);
1470 CurOp += AddrOperands + 1;
1476 case X86II::MRM0r: case X86II::MRM1r:
1477 case X86II::MRM2r: case X86II::MRM3r:
1478 case X86II::MRM4r: case X86II::MRM5r:
1479 case X86II::MRM6r: case X86II::MRM7r:
1480 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1482 EmitByte(BaseOpcode, CurByte, OS);
1483 EmitRegModRMByte(MI.getOperand(CurOp++),
1484 (TSFlags & X86II::FormMask)-X86II::MRM0r,
1487 case X86II::MRM0m: case X86II::MRM1m:
1488 case X86II::MRM2m: case X86II::MRM3m:
1489 case X86II::MRM4m: case X86II::MRM5m:
1490 case X86II::MRM6m: case X86II::MRM7m:
1491 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1493 EmitByte(BaseOpcode, CurByte, OS);
1494 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
1495 TSFlags, CurByte, OS, Fixups);
1496 CurOp += X86::AddrNumOperands;
1498 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
1499 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
1500 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
1501 case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5:
1502 case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9:
1503 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
1504 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
1505 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
1507 EmitByte(BaseOpcode, CurByte, OS);
1510 switch (TSFlags & X86II::FormMask) {
1511 default: llvm_unreachable("Invalid Form");
1512 case X86II::MRM_C1: MRM = 0xC1; break;
1513 case X86II::MRM_C2: MRM = 0xC2; break;
1514 case X86II::MRM_C3: MRM = 0xC3; break;
1515 case X86II::MRM_C4: MRM = 0xC4; break;
1516 case X86II::MRM_C8: MRM = 0xC8; break;
1517 case X86II::MRM_C9: MRM = 0xC9; break;
1518 case X86II::MRM_CA: MRM = 0xCA; break;
1519 case X86II::MRM_CB: MRM = 0xCB; break;
1520 case X86II::MRM_D0: MRM = 0xD0; break;
1521 case X86II::MRM_D1: MRM = 0xD1; break;
1522 case X86II::MRM_D4: MRM = 0xD4; break;
1523 case X86II::MRM_D5: MRM = 0xD5; break;
1524 case X86II::MRM_D6: MRM = 0xD6; break;
1525 case X86II::MRM_D8: MRM = 0xD8; break;
1526 case X86II::MRM_D9: MRM = 0xD9; break;
1527 case X86II::MRM_DA: MRM = 0xDA; break;
1528 case X86II::MRM_DB: MRM = 0xDB; break;
1529 case X86II::MRM_DC: MRM = 0xDC; break;
1530 case X86II::MRM_DD: MRM = 0xDD; break;
1531 case X86II::MRM_DE: MRM = 0xDE; break;
1532 case X86II::MRM_DF: MRM = 0xDF; break;
1533 case X86II::MRM_E8: MRM = 0xE8; break;
1534 case X86II::MRM_F0: MRM = 0xF0; break;
1535 case X86II::MRM_F8: MRM = 0xF8; break;
1536 case X86II::MRM_F9: MRM = 0xF9; break;
1538 EmitByte(MRM, CurByte, OS);
1542 // If there is a remaining operand, it must be a trailing immediate. Emit it
1543 // according to the right size for the instruction. Some instructions
1544 // (SSE4a extrq and insertq) have two trailing immediates.
1545 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1546 // The last source register of a 4 operand instruction in AVX is encoded
1547 // in bits[7:4] of a immediate byte.
1548 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1549 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1552 unsigned RegNum = GetX86RegNum(MO) << 4;
1553 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1555 // If there is an additional 5th operand it must be an immediate, which
1556 // is encoded in bits[3:0]
1557 if (CurOp != NumOps) {
1558 const MCOperand &MIMM = MI.getOperand(CurOp++);
1560 unsigned Val = MIMM.getImm();
1561 assert(Val < 16 && "Immediate operand value out of range");
1565 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1566 CurByte, OS, Fixups);
1569 // FIXME: Is there a better way to know that we need a signed relocation?
1570 if (MI.getOpcode() == X86::ADD64ri32 ||
1571 MI.getOpcode() == X86::MOV64ri32 ||
1572 MI.getOpcode() == X86::MOV64mi32 ||
1573 MI.getOpcode() == X86::PUSH64i32)
1574 FixupKind = X86::reloc_signed_4byte;
1576 FixupKind = getImmFixupKind(TSFlags);
1577 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1578 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1579 CurByte, OS, Fixups);
1583 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1584 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1588 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1589 errs() << "Cannot encode all operands of: ";