1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/raw_ostream.h"
30 class X86MCCodeEmitter : public MCCodeEmitter {
31 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
32 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 const MCInstrInfo &MCII;
34 const MCSubtargetInfo &STI;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
39 : MCII(mcii), STI(sti), Ctx(ctx) {
42 ~X86MCCodeEmitter() {}
44 bool is64BitMode() const {
45 // FIXME: Can tablegen auto-generate this?
46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
49 bool is32BitMode() const {
50 // FIXME: Can tablegen auto-generate this?
51 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
54 static unsigned GetX86RegNum(const MCOperand &MO) {
55 return X86_MC::getX86RegNum(MO.getReg());
58 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
59 // 0-7 and the difference between the 2 groups is given by the REX prefix.
60 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
61 // in 1's complement form, example:
63 // ModRM field => XMM9 => 1
64 // VEX.VVVV => XMM9 => ~9
66 // See table 4-35 of Intel AVX Programming Reference for details.
67 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
69 unsigned SrcReg = MI.getOperand(OpNum).getReg();
70 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
71 if (X86II::isX86_64ExtendedReg(SrcReg))
74 // The registers represented through VEX_VVVV should
75 // be encoded in 1's complement form.
76 return (~SrcRegNum) & 0xf;
79 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
84 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
85 raw_ostream &OS) const {
86 // Output the constant in little endian byte order.
87 for (unsigned i = 0; i != Size; ++i) {
88 EmitByte(Val & 255, CurByte, OS);
93 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
94 unsigned ImmSize, MCFixupKind FixupKind,
95 unsigned &CurByte, raw_ostream &OS,
96 SmallVectorImpl<MCFixup> &Fixups,
97 int ImmOffset = 0) const;
99 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
101 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
102 return RM | (RegOpcode << 3) | (Mod << 6);
105 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
106 unsigned &CurByte, raw_ostream &OS) const {
107 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
110 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
111 unsigned &CurByte, raw_ostream &OS) const {
112 // SIB byte is in the same format as the ModRMByte.
113 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
117 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
118 unsigned RegOpcodeField,
119 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
123 SmallVectorImpl<MCFixup> &Fixups) const;
125 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
126 const MCInst &MI, const MCInstrDesc &Desc,
127 raw_ostream &OS) const;
129 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
130 int MemOperand, const MCInst &MI,
131 raw_ostream &OS) const;
133 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
134 const MCInst &MI, const MCInstrDesc &Desc,
135 raw_ostream &OS) const;
138 } // end anonymous namespace
141 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
142 const MCRegisterInfo &MRI,
143 const MCSubtargetInfo &STI,
145 return new X86MCCodeEmitter(MCII, STI, Ctx);
148 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
149 /// sign-extended field.
150 static bool isDisp8(int Value) {
151 return Value == (signed char)Value;
154 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
155 /// in an instruction with the specified TSFlags.
156 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
157 unsigned Size = X86II::getSizeOfImm(TSFlags);
158 bool isPCRel = X86II::isImmPCRel(TSFlags);
160 return MCFixup::getKindForSize(Size, isPCRel);
163 /// Is32BitMemOperand - Return true if the specified instruction has
164 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
165 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
167 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
169 if ((BaseReg.getReg() != 0 &&
170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
171 (IndexReg.getReg() != 0 &&
172 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
177 /// Is64BitMemOperand - Return true if the specified instruction has
178 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
180 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
181 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
182 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
184 if ((BaseReg.getReg() != 0 &&
185 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
186 (IndexReg.getReg() != 0 &&
187 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
193 /// Is16BitMemOperand - Return true if the specified instruction has
194 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
195 static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) {
196 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
197 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
199 if ((BaseReg.getReg() != 0 &&
200 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
201 (IndexReg.getReg() != 0 &&
202 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
207 /// StartsWithGlobalOffsetTable - Check if this expression starts with
208 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
209 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
210 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
211 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
212 /// of a binary expression.
213 enum GlobalOffsetTableExprKind {
218 static GlobalOffsetTableExprKind
219 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
220 const MCExpr *RHS = 0;
221 if (Expr->getKind() == MCExpr::Binary) {
222 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
227 if (Expr->getKind() != MCExpr::SymbolRef)
230 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
231 const MCSymbol &S = Ref->getSymbol();
232 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
234 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
239 void X86MCCodeEmitter::
240 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
241 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
242 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
243 const MCExpr *Expr = NULL;
244 if (DispOp.isImm()) {
245 // If this is a simple integer displacement that doesn't require a
246 // relocation, emit it now.
247 if (FixupKind != FK_PCRel_1 &&
248 FixupKind != FK_PCRel_2 &&
249 FixupKind != FK_PCRel_4) {
250 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
253 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
255 Expr = DispOp.getExpr();
258 // If we have an immoffset, add it to the expression.
259 if ((FixupKind == FK_Data_4 ||
260 FixupKind == FK_Data_8 ||
261 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
262 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
263 if (Kind != GOT_None) {
264 assert(ImmOffset == 0);
266 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
267 if (Kind == GOT_Normal)
269 } else if (Expr->getKind() == MCExpr::SymbolRef) {
270 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
271 if (Ref->getKind() == MCSymbolRefExpr::VK_SECREL) {
272 FixupKind = MCFixupKind(FK_SecRel_4);
277 // If the fixup is pc-relative, we need to bias the value to be relative to
278 // the start of the field, not the end of the field.
279 if (FixupKind == FK_PCRel_4 ||
280 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
281 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
283 if (FixupKind == FK_PCRel_2)
285 if (FixupKind == FK_PCRel_1)
289 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
292 // Emit a symbolic constant as a fixup and 4 zeros.
293 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
294 EmitConstant(0, Size, CurByte, OS);
297 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
298 unsigned RegOpcodeField,
299 uint64_t TSFlags, unsigned &CurByte,
301 SmallVectorImpl<MCFixup> &Fixups) const{
302 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
303 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
304 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
305 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
306 unsigned BaseReg = Base.getReg();
308 // Handle %rip relative addressing.
309 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
310 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
311 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
312 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
314 unsigned FixupKind = X86::reloc_riprel_4byte;
316 // movq loads are handled with a special relocation form which allows the
317 // linker to eliminate some loads for GOT references which end up in the
318 // same linkage unit.
319 if (MI.getOpcode() == X86::MOV64rm)
320 FixupKind = X86::reloc_riprel_4byte_movq_load;
322 // rip-relative addressing is actually relative to the *next* instruction.
323 // Since an immediate can follow the mod/rm byte for an instruction, this
324 // means that we need to bias the immediate field of the instruction with
325 // the size of the immediate field. If we have this case, add it into the
326 // expression to emit.
327 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
329 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
330 CurByte, OS, Fixups, -ImmSize);
334 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
336 // Determine whether a SIB byte is needed.
337 // If no BaseReg, issue a RIP relative instruction only if the MCE can
338 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
339 // 2-7) and absolute references.
341 if (// The SIB byte must be used if there is an index register.
342 IndexReg.getReg() == 0 &&
343 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
344 // encode to an R/M value of 4, which indicates that a SIB byte is
346 BaseRegNo != N86::ESP &&
347 // If there is no base register and we're in 64-bit mode, we need a SIB
348 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
349 (!is64BitMode() || BaseReg != 0)) {
351 if (BaseReg == 0) { // [disp32] in X86-32 mode
352 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
353 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
357 // If the base is not EBP/ESP and there is no displacement, use simple
358 // indirect register encoding, this handles addresses like [EAX]. The
359 // encoding for [EBP] with no displacement means [disp32] so we handle it
360 // by emitting a displacement of 0 below.
361 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
362 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
366 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
367 if (Disp.isImm() && isDisp8(Disp.getImm())) {
368 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
369 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
373 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
374 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
375 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
380 // We need a SIB byte, so start by outputting the ModR/M byte first
381 assert(IndexReg.getReg() != X86::ESP &&
382 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
384 bool ForceDisp32 = false;
385 bool ForceDisp8 = false;
387 // If there is no base register, we emit the special case SIB byte with
388 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
389 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
391 } else if (!Disp.isImm()) {
392 // Emit the normal disp32 encoding.
393 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
395 } else if (Disp.getImm() == 0 &&
396 // Base reg can't be anything that ends up with '5' as the base
397 // reg, it is the magic [*] nomenclature that indicates no base.
398 BaseRegNo != N86::EBP) {
399 // Emit no displacement ModR/M byte
400 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
401 } else if (isDisp8(Disp.getImm())) {
402 // Emit the disp8 encoding.
403 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
404 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
406 // Emit the normal disp32 encoding.
407 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
410 // Calculate what the SS field value should be...
411 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
412 unsigned SS = SSTable[Scale.getImm()];
415 // Handle the SIB byte for the case where there is no base, see Intel
416 // Manual 2A, table 2-7. The displacement has already been output.
418 if (IndexReg.getReg())
419 IndexRegNo = GetX86RegNum(IndexReg);
420 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
422 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
425 if (IndexReg.getReg())
426 IndexRegNo = GetX86RegNum(IndexReg);
428 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
429 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
432 // Do we need to output a displacement?
434 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
435 else if (ForceDisp32 || Disp.getImm() != 0)
436 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
437 CurByte, OS, Fixups);
440 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
442 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
443 int MemOperand, const MCInst &MI,
444 const MCInstrDesc &Desc,
445 raw_ostream &OS) const {
446 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
447 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
449 // VEX_R: opcode externsion equivalent to REX.R in
450 // 1's complement (inverted) form
452 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
453 // 0: Same as REX_R=1 (64 bit mode only)
455 unsigned char VEX_R = 0x1;
457 // VEX_X: equivalent to REX.X, only used when a
458 // register is used for index in SIB Byte.
460 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
461 // 0: Same as REX.X=1 (64-bit mode only)
462 unsigned char VEX_X = 0x1;
466 // 1: Same as REX_B=0 (ignored in 32-bit mode)
467 // 0: Same as REX_B=1 (64 bit mode only)
469 unsigned char VEX_B = 0x1;
471 // VEX_W: opcode specific (use like REX.W, or used for
472 // opcode extension, or ignored, depending on the opcode byte)
473 unsigned char VEX_W = 0;
475 // XOP: Use XOP prefix byte 0x8f instead of VEX.
476 unsigned char XOP = 0;
478 // VEX_5M (VEX m-mmmmm field):
480 // 0b00000: Reserved for future use
481 // 0b00001: implied 0F leading opcode
482 // 0b00010: implied 0F 38 leading opcode bytes
483 // 0b00011: implied 0F 3A leading opcode bytes
484 // 0b00100-0b11111: Reserved for future use
485 // 0b01000: XOP map select - 08h instructions with imm byte
486 // 0b10001: XOP map select - 09h instructions with no imm byte
487 unsigned char VEX_5M = 0x1;
489 // VEX_4V (VEX vvvv field): a register specifier
490 // (in 1's complement form) or 1111 if unused.
491 unsigned char VEX_4V = 0xf;
493 // VEX_L (Vector Length):
495 // 0: scalar or 128-bit vector
498 unsigned char VEX_L = 0;
500 // VEX_PP: opcode extension providing equivalent
501 // functionality of a SIMD prefix
508 unsigned char VEX_PP = 0;
510 // Encode the operand size opcode prefix as needed.
511 if (TSFlags & X86II::OpSize)
514 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
517 if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
520 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
523 switch (TSFlags & X86II::Op0Mask) {
524 default: llvm_unreachable("Invalid prefix!");
525 case X86II::T8: // 0F 38
528 case X86II::TA: // 0F 3A
531 case X86II::T8XS: // F3 0F 38
535 case X86II::T8XD: // F2 0F 38
539 case X86II::TAXD: // F2 0F 3A
543 case X86II::XS: // F3 0F
546 case X86II::XD: // F2 0F
555 case X86II::A6: // Bypass: Not used by VEX
556 case X86II::A7: // Bypass: Not used by VEX
557 case X86II::TB: // Bypass: Not used by VEX
563 // Set the vector length to 256-bit if YMM0-YMM15 is used
564 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
565 if (!MI.getOperand(i).isReg())
567 unsigned SrcReg = MI.getOperand(i).getReg();
568 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
572 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
573 unsigned NumOps = Desc.getNumOperands();
575 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
577 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) {
578 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
579 // Special case for GATHER with 2 TIED_TO operands
580 // Skip the first 2 operands: dst, mask_wb
584 switch (TSFlags & X86II::FormMask) {
585 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!");
586 case X86II::MRMDestMem: {
587 // MRMDestMem instructions forms:
588 // MemAddr, src1(ModR/M)
589 // MemAddr, src1(VEX_4V), src2(ModR/M)
590 // MemAddr, src1(ModR/M), imm8
592 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
594 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
597 CurOp = X86::AddrNumOperands;
599 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
601 const MCOperand &MO = MI.getOperand(CurOp);
602 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
606 case X86II::MRMSrcMem:
607 // MRMSrcMem instructions forms:
608 // src1(ModR/M), MemAddr
609 // src1(ModR/M), src2(VEX_4V), MemAddr
610 // src1(ModR/M), MemAddr, imm8
611 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
614 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
615 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
616 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp++).getReg()))
620 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
622 if (X86II::isX86_64ExtendedReg(
623 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
625 if (X86II::isX86_64ExtendedReg(
626 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
630 // Instruction format for 4VOp3:
631 // src1(ModR/M), MemAddr, src3(VEX_4V)
632 // CurOp points to start of the MemoryOperand,
633 // it skips TIED_TO operands if exist, then increments past src1.
634 // CurOp + X86::AddrNumOperands will point to src3.
635 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
637 case X86II::MRM0m: case X86II::MRM1m:
638 case X86II::MRM2m: case X86II::MRM3m:
639 case X86II::MRM4m: case X86II::MRM5m:
640 case X86II::MRM6m: case X86II::MRM7m: {
641 // MRM[0-9]m instructions forms:
643 // src1(VEX_4V), MemAddr
645 VEX_4V = getVEXRegisterEncoding(MI, 0);
647 if (X86II::isX86_64ExtendedReg(
648 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
650 if (X86II::isX86_64ExtendedReg(
651 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
655 case X86II::MRMSrcReg:
656 // MRMSrcReg instructions forms:
657 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
658 // dst(ModR/M), src1(ModR/M)
659 // dst(ModR/M), src1(ModR/M), imm8
661 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
666 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
667 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
671 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
673 case X86II::MRMDestReg:
674 // MRMDestReg instructions forms:
675 // dst(ModR/M), src(ModR/M)
676 // dst(ModR/M), src(ModR/M), imm8
677 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
679 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
682 case X86II::MRM0r: case X86II::MRM1r:
683 case X86II::MRM2r: case X86II::MRM3r:
684 case X86II::MRM4r: case X86II::MRM5r:
685 case X86II::MRM6r: case X86II::MRM7r:
686 // MRM0r-MRM7r instructions forms:
687 // dst(VEX_4V), src(ModR/M), imm8
688 VEX_4V = getVEXRegisterEncoding(MI, 0);
689 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
696 // Emit segment override opcode prefix as needed.
697 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
699 // VEX opcode prefix can have 2 or 3 bytes
702 // +-----+ +--------------+ +-------------------+
703 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
704 // +-----+ +--------------+ +-------------------+
706 // +-----+ +-------------------+
707 // | C5h | | R | vvvv | L | pp |
708 // +-----+ +-------------------+
710 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
712 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
713 EmitByte(0xC5, CurByte, OS);
714 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
719 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
720 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
721 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
724 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
725 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
726 /// size, and 3) use of X86-64 extended registers.
727 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
728 const MCInstrDesc &Desc) {
730 if (TSFlags & X86II::REX_W)
731 REX |= 1 << 3; // set REX.W
733 if (MI.getNumOperands() == 0) return REX;
735 unsigned NumOps = MI.getNumOperands();
736 // FIXME: MCInst should explicitize the two-addrness.
737 bool isTwoAddr = NumOps > 1 &&
738 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
740 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
741 unsigned i = isTwoAddr ? 1 : 0;
742 for (; i != NumOps; ++i) {
743 const MCOperand &MO = MI.getOperand(i);
744 if (!MO.isReg()) continue;
745 unsigned Reg = MO.getReg();
746 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
747 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
748 // that returns non-zero.
749 REX |= 0x40; // REX fixed encoding prefix
753 switch (TSFlags & X86II::FormMask) {
754 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!");
755 case X86II::MRMSrcReg:
756 if (MI.getOperand(0).isReg() &&
757 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
758 REX |= 1 << 2; // set REX.R
759 i = isTwoAddr ? 2 : 1;
760 for (; i != NumOps; ++i) {
761 const MCOperand &MO = MI.getOperand(i);
762 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
763 REX |= 1 << 0; // set REX.B
766 case X86II::MRMSrcMem: {
767 if (MI.getOperand(0).isReg() &&
768 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
769 REX |= 1 << 2; // set REX.R
771 i = isTwoAddr ? 2 : 1;
772 for (; i != NumOps; ++i) {
773 const MCOperand &MO = MI.getOperand(i);
775 if (X86II::isX86_64ExtendedReg(MO.getReg()))
776 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
782 case X86II::MRM0m: case X86II::MRM1m:
783 case X86II::MRM2m: case X86II::MRM3m:
784 case X86II::MRM4m: case X86II::MRM5m:
785 case X86II::MRM6m: case X86II::MRM7m:
786 case X86II::MRMDestMem: {
787 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
788 i = isTwoAddr ? 1 : 0;
789 if (NumOps > e && MI.getOperand(e).isReg() &&
790 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
791 REX |= 1 << 2; // set REX.R
793 for (; i != e; ++i) {
794 const MCOperand &MO = MI.getOperand(i);
796 if (X86II::isX86_64ExtendedReg(MO.getReg()))
797 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
804 if (MI.getOperand(0).isReg() &&
805 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
806 REX |= 1 << 0; // set REX.B
807 i = isTwoAddr ? 2 : 1;
808 for (unsigned e = NumOps; i != e; ++i) {
809 const MCOperand &MO = MI.getOperand(i);
810 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
811 REX |= 1 << 2; // set REX.R
818 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
819 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
820 unsigned &CurByte, int MemOperand,
822 raw_ostream &OS) const {
823 switch (TSFlags & X86II::SegOvrMask) {
824 default: llvm_unreachable("Invalid segment!");
826 // No segment override, check for explicit one on memory operand.
827 if (MemOperand != -1) { // If the instruction has a memory operand.
828 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
829 default: llvm_unreachable("Unknown segment register!");
831 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
832 case X86::SS: EmitByte(0x36, CurByte, OS); break;
833 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
834 case X86::ES: EmitByte(0x26, CurByte, OS); break;
835 case X86::FS: EmitByte(0x64, CurByte, OS); break;
836 case X86::GS: EmitByte(0x65, CurByte, OS); break;
841 EmitByte(0x64, CurByte, OS);
844 EmitByte(0x65, CurByte, OS);
849 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
851 /// MemOperand is the operand # of the start of a memory operand if present. If
852 /// Not present, it is -1.
853 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
854 int MemOperand, const MCInst &MI,
855 const MCInstrDesc &Desc,
856 raw_ostream &OS) const {
858 // Emit the lock opcode prefix as needed.
859 if (TSFlags & X86II::LOCK)
860 EmitByte(0xF0, CurByte, OS);
862 // Emit segment override opcode prefix as needed.
863 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
865 // Emit the repeat opcode prefix as needed.
866 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
867 EmitByte(0xF3, CurByte, OS);
869 // Emit the address size opcode prefix as needed.
870 bool need_address_override;
871 if (TSFlags & X86II::AdSize) {
872 need_address_override = true;
873 } else if (MemOperand == -1) {
874 need_address_override = false;
875 } else if (is64BitMode()) {
876 assert(!Is16BitMemOperand(MI, MemOperand));
877 need_address_override = Is32BitMemOperand(MI, MemOperand);
878 } else if (is32BitMode()) {
879 assert(!Is64BitMemOperand(MI, MemOperand));
880 need_address_override = Is16BitMemOperand(MI, MemOperand);
882 need_address_override = false;
885 if (need_address_override)
886 EmitByte(0x67, CurByte, OS);
888 // Emit the operand size opcode prefix as needed.
889 if (TSFlags & X86II::OpSize)
890 EmitByte(0x66, CurByte, OS);
892 bool Need0FPrefix = false;
893 switch (TSFlags & X86II::Op0Mask) {
894 default: llvm_unreachable("Invalid prefix!");
895 case 0: break; // No prefix!
896 case X86II::REP: break; // already handled.
897 case X86II::TB: // Two-byte opcode prefix
898 case X86II::T8: // 0F 38
899 case X86II::TA: // 0F 3A
900 case X86II::A6: // 0F A6
901 case X86II::A7: // 0F A7
904 case X86II::T8XS: // F3 0F 38
905 EmitByte(0xF3, CurByte, OS);
908 case X86II::T8XD: // F2 0F 38
909 EmitByte(0xF2, CurByte, OS);
912 case X86II::TAXD: // F2 0F 3A
913 EmitByte(0xF2, CurByte, OS);
916 case X86II::XS: // F3 0F
917 EmitByte(0xF3, CurByte, OS);
920 case X86II::XD: // F2 0F
921 EmitByte(0xF2, CurByte, OS);
924 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
925 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
926 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
927 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
928 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
929 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
930 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
931 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
934 // Handle REX prefix.
935 // FIXME: Can this come before F2 etc to simplify emission?
937 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
938 EmitByte(0x40 | REX, CurByte, OS);
941 // 0x0F escape code must be emitted just before the opcode.
943 EmitByte(0x0F, CurByte, OS);
945 // FIXME: Pull this up into previous switch if REX can be moved earlier.
946 switch (TSFlags & X86II::Op0Mask) {
947 case X86II::T8XS: // F3 0F 38
948 case X86II::T8XD: // F2 0F 38
949 case X86II::T8: // 0F 38
950 EmitByte(0x38, CurByte, OS);
952 case X86II::TAXD: // F2 0F 3A
953 case X86II::TA: // 0F 3A
954 EmitByte(0x3A, CurByte, OS);
956 case X86II::A6: // 0F A6
957 EmitByte(0xA6, CurByte, OS);
959 case X86II::A7: // 0F A7
960 EmitByte(0xA7, CurByte, OS);
965 void X86MCCodeEmitter::
966 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
967 SmallVectorImpl<MCFixup> &Fixups) const {
968 unsigned Opcode = MI.getOpcode();
969 const MCInstrDesc &Desc = MCII.get(Opcode);
970 uint64_t TSFlags = Desc.TSFlags;
972 // Pseudo instructions don't get encoded.
973 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
976 // If this is a two-address instruction, skip one of the register operands.
977 // FIXME: This should be handled during MCInst lowering.
978 unsigned NumOps = Desc.getNumOperands();
980 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
982 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) {
983 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
984 // Special case for GATHER with 2 TIED_TO operands
985 // Skip the first 2 operands: dst, mask_wb
989 // Keep track of the current byte being emitted.
990 unsigned CurByte = 0;
992 // Is this instruction encoded using the AVX VEX prefix?
993 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX;
995 // It uses the VEX.VVVV field?
996 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
997 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
998 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
999 const unsigned MemOp4_I8IMMOperand = 2;
1001 // Determine where the memory operand starts, if present.
1002 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1003 if (MemoryOperand != -1) MemoryOperand += CurOp;
1006 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1008 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1010 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1012 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1013 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1015 unsigned SrcRegNum = 0;
1016 switch (TSFlags & X86II::FormMask) {
1017 case X86II::MRMInitReg:
1018 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
1019 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1020 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1022 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1024 EmitByte(BaseOpcode, CurByte, OS);
1026 case X86II::RawFrmImm8:
1027 EmitByte(BaseOpcode, CurByte, OS);
1028 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1029 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1030 CurByte, OS, Fixups);
1031 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1034 case X86II::RawFrmImm16:
1035 EmitByte(BaseOpcode, CurByte, OS);
1036 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1037 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1038 CurByte, OS, Fixups);
1039 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1043 case X86II::AddRegFrm:
1044 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1047 case X86II::MRMDestReg:
1048 EmitByte(BaseOpcode, CurByte, OS);
1049 EmitRegModRMByte(MI.getOperand(CurOp),
1050 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
1054 case X86II::MRMDestMem:
1055 EmitByte(BaseOpcode, CurByte, OS);
1056 SrcRegNum = CurOp + X86::AddrNumOperands;
1058 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1061 EmitMemModRMByte(MI, CurOp,
1062 GetX86RegNum(MI.getOperand(SrcRegNum)),
1063 TSFlags, CurByte, OS, Fixups);
1064 CurOp = SrcRegNum + 1;
1067 case X86II::MRMSrcReg:
1068 EmitByte(BaseOpcode, CurByte, OS);
1069 SrcRegNum = CurOp + 1;
1071 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1074 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1077 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1078 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1080 // 2 operands skipped with HasMemOp4, compensate accordingly
1081 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1086 case X86II::MRMSrcMem: {
1087 int AddrOperands = X86::AddrNumOperands;
1088 unsigned FirstMemOp = CurOp+1;
1091 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1093 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1096 EmitByte(BaseOpcode, CurByte, OS);
1098 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1099 TSFlags, CurByte, OS, Fixups);
1100 CurOp += AddrOperands + 1;
1106 case X86II::MRM0r: case X86II::MRM1r:
1107 case X86II::MRM2r: case X86II::MRM3r:
1108 case X86II::MRM4r: case X86II::MRM5r:
1109 case X86II::MRM6r: case X86II::MRM7r:
1110 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1112 EmitByte(BaseOpcode, CurByte, OS);
1113 EmitRegModRMByte(MI.getOperand(CurOp++),
1114 (TSFlags & X86II::FormMask)-X86II::MRM0r,
1117 case X86II::MRM0m: case X86II::MRM1m:
1118 case X86II::MRM2m: case X86II::MRM3m:
1119 case X86II::MRM4m: case X86II::MRM5m:
1120 case X86II::MRM6m: case X86II::MRM7m:
1121 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1123 EmitByte(BaseOpcode, CurByte, OS);
1124 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
1125 TSFlags, CurByte, OS, Fixups);
1126 CurOp += X86::AddrNumOperands;
1128 case X86II::MRM_C1: case X86II::MRM_C2:
1129 case X86II::MRM_C3: case X86II::MRM_C4:
1130 case X86II::MRM_C8: case X86II::MRM_C9:
1131 case X86II::MRM_D0: case X86II::MRM_D1:
1132 case X86II::MRM_D4: case X86II::MRM_D8:
1133 case X86II::MRM_D9: case X86II::MRM_DA:
1134 case X86II::MRM_DB: case X86II::MRM_DC:
1135 case X86II::MRM_DD: case X86II::MRM_DE:
1136 case X86II::MRM_DF: case X86II::MRM_E8:
1137 case X86II::MRM_F0: case X86II::MRM_F8:
1139 EmitByte(BaseOpcode, CurByte, OS);
1142 switch (TSFlags & X86II::FormMask) {
1143 default: llvm_unreachable("Invalid Form");
1144 case X86II::MRM_C1: MRM = 0xC1; break;
1145 case X86II::MRM_C2: MRM = 0xC2; break;
1146 case X86II::MRM_C3: MRM = 0xC3; break;
1147 case X86II::MRM_C4: MRM = 0xC4; break;
1148 case X86II::MRM_C8: MRM = 0xC8; break;
1149 case X86II::MRM_C9: MRM = 0xC9; break;
1150 case X86II::MRM_D0: MRM = 0xD0; break;
1151 case X86II::MRM_D1: MRM = 0xD1; break;
1152 case X86II::MRM_D4: MRM = 0xD4; break;
1153 case X86II::MRM_D8: MRM = 0xD8; break;
1154 case X86II::MRM_D9: MRM = 0xD9; break;
1155 case X86II::MRM_DA: MRM = 0xDA; break;
1156 case X86II::MRM_DB: MRM = 0xDB; break;
1157 case X86II::MRM_DC: MRM = 0xDC; break;
1158 case X86II::MRM_DD: MRM = 0xDD; break;
1159 case X86II::MRM_DE: MRM = 0xDE; break;
1160 case X86II::MRM_DF: MRM = 0xDF; break;
1161 case X86II::MRM_E8: MRM = 0xE8; break;
1162 case X86II::MRM_F0: MRM = 0xF0; break;
1163 case X86II::MRM_F8: MRM = 0xF8; break;
1164 case X86II::MRM_F9: MRM = 0xF9; break;
1166 EmitByte(MRM, CurByte, OS);
1170 // If there is a remaining operand, it must be a trailing immediate. Emit it
1171 // according to the right size for the instruction. Some instructions
1172 // (SSE4a extrq and insertq) have two trailing immediates.
1173 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1174 // The last source register of a 4 operand instruction in AVX is encoded
1175 // in bits[7:4] of a immediate byte.
1176 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1177 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1180 unsigned RegNum = GetX86RegNum(MO) << 4;
1181 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1183 // If there is an additional 5th operand it must be an immediate, which
1184 // is encoded in bits[3:0]
1185 if (CurOp != NumOps) {
1186 const MCOperand &MIMM = MI.getOperand(CurOp++);
1188 unsigned Val = MIMM.getImm();
1189 assert(Val < 16 && "Immediate operand value out of range");
1193 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1194 CurByte, OS, Fixups);
1197 // FIXME: Is there a better way to know that we need a signed relocation?
1198 if (MI.getOpcode() == X86::ADD64ri32 ||
1199 MI.getOpcode() == X86::MOV64ri32 ||
1200 MI.getOpcode() == X86::MOV64mi32 ||
1201 MI.getOpcode() == X86::PUSH64i32)
1202 FixupKind = X86::reloc_signed_4byte;
1204 FixupKind = getImmFixupKind(TSFlags);
1205 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1206 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1207 CurByte, OS, Fixups);
1211 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1212 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1216 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1217 errs() << "Cannot encode all operands of: ";