1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "MCTargetDesc/X86FixupKinds.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCAsmBackend.h"
14 #include "llvm/MC/MCELFObjectWriter.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSectionCOFF.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSectionMachO.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ELF.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MachO.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
32 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
33 // is useful when running bitwise comparison experiments on Darwin. We should be
34 // able to remove this once PR9807 is resolved.
36 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
37 cl::desc("Disable relaxation of arithmetic instruction for X86"));
39 static unsigned getFixupKindLog2Size(unsigned Kind) {
42 llvm_unreachable("invalid fixup kind!");
52 case X86::reloc_riprel_4byte:
53 case X86::reloc_riprel_4byte_movq_load:
54 case X86::reloc_signed_4byte:
55 case X86::reloc_global_offset_table:
62 case X86::reloc_global_offset_table8:
69 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
71 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
72 bool HasRelocationAddend, bool foobar)
73 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
76 class X86AsmBackend : public MCAsmBackend {
79 const uint64_t MaxNopLength;
81 X86AsmBackend(const Target &T, StringRef CPU)
82 : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) {
83 HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
84 CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
85 CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
86 CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
87 CPU != "c3" && CPU != "c3-2";
90 unsigned getNumFixupKinds() const override {
91 return X86::NumTargetFixupKinds;
94 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
95 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
96 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
97 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
98 { "reloc_signed_4byte", 0, 4 * 8, 0},
99 { "reloc_global_offset_table", 0, 4 * 8, 0}
102 if (Kind < FirstTargetFixupKind)
103 return MCAsmBackend::getFixupKindInfo(Kind);
105 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
107 return Infos[Kind - FirstTargetFixupKind];
110 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
111 uint64_t Value, bool IsPCRel) const override {
112 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
114 assert(Fixup.getOffset() + Size <= DataSize &&
115 "Invalid fixup offset!");
117 // Check that uppper bits are either all zeros or all ones.
118 // Specifically ignore overflow/underflow as long as the leakage is
119 // limited to the lower bits. This is to remain compatible with
121 assert(isIntN(Size * 8 + 1, Value) &&
122 "Value does not fit in the Fixup field");
124 for (unsigned i = 0; i != Size; ++i)
125 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
128 bool mayNeedRelaxation(const MCInst &Inst) const override;
130 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
131 const MCRelaxableFragment *DF,
132 const MCAsmLayout &Layout) const override;
134 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
136 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
138 } // end anonymous namespace
140 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
145 case X86::JAE_1: return X86::JAE_4;
146 case X86::JA_1: return X86::JA_4;
147 case X86::JBE_1: return X86::JBE_4;
148 case X86::JB_1: return X86::JB_4;
149 case X86::JE_1: return X86::JE_4;
150 case X86::JGE_1: return X86::JGE_4;
151 case X86::JG_1: return X86::JG_4;
152 case X86::JLE_1: return X86::JLE_4;
153 case X86::JL_1: return X86::JL_4;
154 case X86::JMP_1: return X86::JMP_4;
155 case X86::JNE_1: return X86::JNE_4;
156 case X86::JNO_1: return X86::JNO_4;
157 case X86::JNP_1: return X86::JNP_4;
158 case X86::JNS_1: return X86::JNS_4;
159 case X86::JO_1: return X86::JO_4;
160 case X86::JP_1: return X86::JP_4;
161 case X86::JS_1: return X86::JS_4;
165 static unsigned getRelaxedOpcodeArith(unsigned Op) {
171 case X86::IMUL16rri8: return X86::IMUL16rri;
172 case X86::IMUL16rmi8: return X86::IMUL16rmi;
173 case X86::IMUL32rri8: return X86::IMUL32rri;
174 case X86::IMUL32rmi8: return X86::IMUL32rmi;
175 case X86::IMUL64rri8: return X86::IMUL64rri32;
176 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
179 case X86::AND16ri8: return X86::AND16ri;
180 case X86::AND16mi8: return X86::AND16mi;
181 case X86::AND32ri8: return X86::AND32ri;
182 case X86::AND32mi8: return X86::AND32mi;
183 case X86::AND64ri8: return X86::AND64ri32;
184 case X86::AND64mi8: return X86::AND64mi32;
187 case X86::OR16ri8: return X86::OR16ri;
188 case X86::OR16mi8: return X86::OR16mi;
189 case X86::OR32ri8: return X86::OR32ri;
190 case X86::OR32mi8: return X86::OR32mi;
191 case X86::OR64ri8: return X86::OR64ri32;
192 case X86::OR64mi8: return X86::OR64mi32;
195 case X86::XOR16ri8: return X86::XOR16ri;
196 case X86::XOR16mi8: return X86::XOR16mi;
197 case X86::XOR32ri8: return X86::XOR32ri;
198 case X86::XOR32mi8: return X86::XOR32mi;
199 case X86::XOR64ri8: return X86::XOR64ri32;
200 case X86::XOR64mi8: return X86::XOR64mi32;
203 case X86::ADD16ri8: return X86::ADD16ri;
204 case X86::ADD16mi8: return X86::ADD16mi;
205 case X86::ADD32ri8: return X86::ADD32ri;
206 case X86::ADD32mi8: return X86::ADD32mi;
207 case X86::ADD64ri8: return X86::ADD64ri32;
208 case X86::ADD64mi8: return X86::ADD64mi32;
211 case X86::SUB16ri8: return X86::SUB16ri;
212 case X86::SUB16mi8: return X86::SUB16mi;
213 case X86::SUB32ri8: return X86::SUB32ri;
214 case X86::SUB32mi8: return X86::SUB32mi;
215 case X86::SUB64ri8: return X86::SUB64ri32;
216 case X86::SUB64mi8: return X86::SUB64mi32;
219 case X86::CMP16ri8: return X86::CMP16ri;
220 case X86::CMP16mi8: return X86::CMP16mi;
221 case X86::CMP32ri8: return X86::CMP32ri;
222 case X86::CMP32mi8: return X86::CMP32mi;
223 case X86::CMP64ri8: return X86::CMP64ri32;
224 case X86::CMP64mi8: return X86::CMP64mi32;
227 case X86::PUSH32i8: return X86::PUSHi32;
228 case X86::PUSH16i8: return X86::PUSHi16;
229 case X86::PUSH64i8: return X86::PUSH64i32;
230 case X86::PUSH64i16: return X86::PUSH64i32;
234 static unsigned getRelaxedOpcode(unsigned Op) {
235 unsigned R = getRelaxedOpcodeArith(Op);
238 return getRelaxedOpcodeBranch(Op);
241 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
242 // Branches can always be relaxed.
243 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
246 if (MCDisableArithRelaxation)
249 // Check if this instruction is ever relaxable.
250 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
254 // Check if it has an expression and is not RIP relative.
257 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
258 const MCOperand &Op = Inst.getOperand(i);
262 if (Op.isReg() && Op.getReg() == X86::RIP)
266 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
267 // how we do relaxations?
268 return hasExp && !hasRIP;
271 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
273 const MCRelaxableFragment *DF,
274 const MCAsmLayout &Layout) const {
275 // Relax if the value is too big for a (signed) i8.
276 return int64_t(Value) != int64_t(int8_t(Value));
279 // FIXME: Can tblgen help at all here to verify there aren't other instructions
281 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
282 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
283 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
285 if (RelaxedOp == Inst.getOpcode()) {
286 SmallString<256> Tmp;
287 raw_svector_ostream OS(Tmp);
288 Inst.dump_pretty(OS);
290 report_fatal_error("unexpected instruction to relax: " + OS.str());
294 Res.setOpcode(RelaxedOp);
297 /// \brief Write a sequence of optimal nops to the output, covering \p Count
299 /// \return - true on success, false on failure
300 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
301 static const uint8_t Nops[10][10] = {
309 {0x0f, 0x1f, 0x40, 0x00},
310 // nopl 0(%[re]ax,%[re]ax,1)
311 {0x0f, 0x1f, 0x44, 0x00, 0x00},
312 // nopw 0(%[re]ax,%[re]ax,1)
313 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
315 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
316 // nopl 0L(%[re]ax,%[re]ax,1)
317 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
318 // nopw 0L(%[re]ax,%[re]ax,1)
319 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
320 // nopw %cs:0L(%[re]ax,%[re]ax,1)
321 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
324 // This CPU doesn't support long nops. If needed add more.
325 // FIXME: Can we get this from the subtarget somehow?
326 // FIXME: We could generated something better than plain 0x90.
328 for (uint64_t i = 0; i < Count; ++i)
333 // 15 is the longest single nop instruction. Emit as many 15-byte nops as
334 // needed, then emit a nop of the remaining length.
336 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
337 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
338 for (uint8_t i = 0; i < Prefixes; i++)
340 const uint8_t Rest = ThisNopLength - Prefixes;
341 for (uint8_t i = 0; i < Rest; i++)
342 OW->write8(Nops[Rest - 1][i]);
343 Count -= ThisNopLength;
344 } while (Count != 0);
353 class ELFX86AsmBackend : public X86AsmBackend {
356 ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
357 : X86AsmBackend(T, CPU), OSABI(OSABI) {}
360 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
362 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
363 : ELFX86AsmBackend(T, OSABI, CPU) {}
365 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
366 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
370 class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
372 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
373 : ELFX86AsmBackend(T, OSABI, CPU) {}
375 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
376 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
381 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
383 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
384 : ELFX86AsmBackend(T, OSABI, CPU) {}
386 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
387 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
391 class WindowsX86AsmBackend : public X86AsmBackend {
395 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
396 : X86AsmBackend(T, CPU)
400 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
401 return createX86WinCOFFObjectWriter(OS, Is64Bit);
407 /// Compact unwind encoding values.
408 enum CompactUnwindEncodings {
409 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
410 /// the return address, then [RE]SP is moved to [RE]BP.
411 UNWIND_MODE_BP_FRAME = 0x01000000,
413 /// A frameless function with a small constant stack size.
414 UNWIND_MODE_STACK_IMMD = 0x02000000,
416 /// A frameless function with a large constant stack size.
417 UNWIND_MODE_STACK_IND = 0x03000000,
419 /// No compact unwind encoding is available.
420 UNWIND_MODE_DWARF = 0x04000000,
422 /// Mask for encoding the frame registers.
423 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
425 /// Mask for encoding the frameless registers.
426 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
431 class DarwinX86AsmBackend : public X86AsmBackend {
432 const MCRegisterInfo &MRI;
434 /// \brief Number of registers that can be saved in a compact unwind encoding.
435 enum { CU_NUM_SAVED_REGS = 6 };
437 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
440 unsigned OffsetSize; ///< Offset of a "push" instruction.
441 unsigned MoveInstrSize; ///< Size of a "move" instruction.
442 unsigned StackDivide; ///< Amount to adjust stack size by.
444 /// \brief Size of a "push" instruction for the given register.
445 unsigned PushInstrSize(unsigned Reg) const {
465 /// \brief Implementation of algorithm to generate the compact unwind encoding
466 /// for the CFI instructions.
468 generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
469 if (Instrs.empty()) return 0;
471 // Reset the saved registers.
472 unsigned SavedRegIdx = 0;
473 memset(SavedRegs, 0, sizeof(SavedRegs));
477 // Encode that we are using EBP/RBP as the frame pointer.
478 uint32_t CompactUnwindEncoding = 0;
480 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
481 unsigned InstrOffset = 0;
482 unsigned StackAdjust = 0;
483 unsigned StackSize = 0;
484 unsigned PrevStackSize = 0;
485 unsigned NumDefCFAOffsets = 0;
487 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
488 const MCCFIInstruction &Inst = Instrs[i];
490 switch (Inst.getOperation()) {
492 // Any other CFI directives indicate a frame that we aren't prepared
493 // to represent via compact unwind, so just bail out.
495 case MCCFIInstruction::OpDefCfaRegister: {
496 // Defines a frame pointer. E.g.
500 // .cfi_def_cfa_register %rbp
503 assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
504 (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
507 memset(SavedRegs, 0, sizeof(SavedRegs));
510 InstrOffset += MoveInstrSize;
513 case MCCFIInstruction::OpDefCfaOffset: {
514 // Defines a new offset for the CFA. E.g.
520 // .cfi_def_cfa_offset 16
526 // .cfi_def_cfa_offset 80
528 PrevStackSize = StackSize;
529 StackSize = std::abs(Inst.getOffset()) / StackDivide;
533 case MCCFIInstruction::OpOffset: {
534 // Defines a "push" of a callee-saved register. E.g.
542 // .cfi_offset %rbx, -40
543 // .cfi_offset %r14, -32
544 // .cfi_offset %r15, -24
546 if (SavedRegIdx == CU_NUM_SAVED_REGS)
547 // If there are too many saved registers, we cannot use a compact
549 return CU::UNWIND_MODE_DWARF;
551 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
552 SavedRegs[SavedRegIdx++] = Reg;
553 StackAdjust += OffsetSize;
554 InstrOffset += PushInstrSize(Reg);
560 StackAdjust /= StackDivide;
563 if ((StackAdjust & 0xFF) != StackAdjust)
564 // Offset was too big for a compact unwind encoding.
565 return CU::UNWIND_MODE_DWARF;
567 // Get the encoding of the saved registers when we have a frame pointer.
568 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
569 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
571 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
572 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
573 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
575 // If the amount of the stack allocation is the size of a register, then
576 // we "push" the RAX/EAX register onto the stack instead of adjusting the
577 // stack pointer with a SUB instruction. We don't support the push of the
578 // RAX/EAX register with compact unwind. So we check for that situation
580 if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
581 StackSize - PrevStackSize == 1) ||
582 (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
583 return CU::UNWIND_MODE_DWARF;
585 SubtractInstrIdx += InstrOffset;
588 if ((StackSize & 0xFF) == StackSize) {
589 // Frameless stack with a small stack size.
590 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
592 // Encode the stack size.
593 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
595 if ((StackAdjust & 0x7) != StackAdjust)
596 // The extra stack adjustments are too big for us to handle.
597 return CU::UNWIND_MODE_DWARF;
599 // Frameless stack with an offset too large for us to encode compactly.
600 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
602 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
604 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
606 // Encode any extra stack stack adjustments (done via push
608 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
611 // Encode the number of registers saved. (Reverse the list first.)
612 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
613 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
615 // Get the encoding of the saved registers when we don't have a frame
617 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
618 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
620 // Encode the register encoding.
621 CompactUnwindEncoding |=
622 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
625 return CompactUnwindEncoding;
629 /// \brief Get the compact unwind number for a given register. The number
630 /// corresponds to the enum lists in compact_unwind_encoding.h.
631 int getCompactUnwindRegNum(unsigned Reg) const {
632 static const uint16_t CU32BitRegs[7] = {
633 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
635 static const uint16_t CU64BitRegs[] = {
636 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
638 const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
639 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
646 /// \brief Return the registers encoded for a compact encoding with a frame
648 uint32_t encodeCompactUnwindRegistersWithFrame() const {
649 // Encode the registers in the order they were saved --- 3-bits per
650 // register. The list of saved registers is assumed to be in reverse
651 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
653 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
654 unsigned Reg = SavedRegs[i];
657 int CURegNum = getCompactUnwindRegNum(Reg);
658 if (CURegNum == -1) return ~0U;
660 // Encode the 3-bit register number in order, skipping over 3-bits for
662 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
665 assert((RegEnc & 0x3FFFF) == RegEnc &&
666 "Invalid compact register encoding!");
670 /// \brief Create the permutation encoding used with frameless stacks. It is
671 /// passed the number of registers to be saved and an array of the registers
673 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
674 // The saved registers are numbered from 1 to 6. In order to encode the
675 // order in which they were saved, we re-number them according to their
676 // place in the register order. The re-numbering is relative to the last
677 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
687 for (unsigned i = 0; i < RegCount; ++i) {
688 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
689 if (CUReg == -1) return ~0U;
690 SavedRegs[i] = CUReg;
694 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
696 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
697 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
698 unsigned Countless = 0;
699 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
700 if (SavedRegs[j] < SavedRegs[i])
703 RenumRegs[i] = SavedRegs[i] - Countless - 1;
706 // Take the renumbered values and encode them into a 10-bit number.
707 uint32_t permutationEncoding = 0;
710 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
711 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
715 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
716 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
720 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
721 + 3 * RenumRegs[4] + RenumRegs[5];
724 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
728 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
731 permutationEncoding |= RenumRegs[5];
735 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
736 "Invalid compact register encoding!");
737 return permutationEncoding;
741 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
743 : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
744 memset(SavedRegs, 0, sizeof(SavedRegs));
745 OffsetSize = Is64Bit ? 8 : 4;
746 MoveInstrSize = Is64Bit ? 3 : 2;
747 StackDivide = Is64Bit ? 8 : 4;
751 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
753 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
755 : DarwinX86AsmBackend(T, MRI, CPU, false) {}
757 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
758 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
759 MachO::CPU_TYPE_I386,
760 MachO::CPU_SUBTYPE_I386_ALL);
763 /// \brief Generate the compact unwind encoding for the CFI instructions.
764 uint32_t generateCompactUnwindEncoding(
765 ArrayRef<MCCFIInstruction> Instrs) const override {
766 return generateCompactUnwindEncodingImpl(Instrs);
770 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
771 const MachO::CPUSubTypeX86 Subtype;
773 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
774 StringRef CPU, MachO::CPUSubTypeX86 st)
775 : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
777 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
778 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
779 MachO::CPU_TYPE_X86_64, Subtype);
782 /// \brief Generate the compact unwind encoding for the CFI instructions.
783 uint32_t generateCompactUnwindEncoding(
784 ArrayRef<MCCFIInstruction> Instrs) const override {
785 return generateCompactUnwindEncodingImpl(Instrs);
789 } // end anonymous namespace
791 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
792 const MCRegisterInfo &MRI,
793 const Triple &TheTriple,
795 if (TheTriple.isOSBinFormatMachO())
796 return new DarwinX86_32AsmBackend(T, MRI, CPU);
798 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
799 return new WindowsX86AsmBackend(T, false, CPU);
801 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
802 return new ELFX86_32AsmBackend(T, OSABI, CPU);
805 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
806 const MCRegisterInfo &MRI,
807 const Triple &TheTriple,
809 if (TheTriple.isOSBinFormatMachO()) {
810 MachO::CPUSubTypeX86 CS =
811 StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
812 .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
813 .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
814 return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
817 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
818 return new WindowsX86AsmBackend(T, true, CPU);
820 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
822 if (TheTriple.getEnvironment() == Triple::GNUX32)
823 return new ELFX86_X32AsmBackend(T, OSABI, CPU);
824 return new ELFX86_64AsmBackend(T, OSABI, CPU);