1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "MCTargetDesc/X86FixupKinds.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCELFObjectWriter.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCMachObjectWriter.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionCOFF.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/ELF.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MachO.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
32 /// Compact unwind encoding values.
33 enum CompactUnwindEncodings {
34 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
35 /// the return address, then [RE]SP is moved to [RE]BP.
36 UNWIND_MODE_BP_FRAME = 0x01000000,
38 /// A frameless function with a small constant stack size.
39 UNWIND_MODE_STACK_IMMD = 0x02000000,
41 /// A frameless function with a large constant stack size.
42 UNWIND_MODE_STACK_IND = 0x03000000,
44 /// No compact unwind encoding is available.
45 UNWIND_MODE_DWARF = 0x04000000,
47 /// Mask for encoding the frame registers.
48 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
50 /// Mask for encoding the frameless registers.
51 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
56 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
57 // is useful when running bitwise comparison experiments on Darwin. We should be
58 // able to remove this once PR9807 is resolved.
60 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
61 cl::desc("Disable relaxation of arithmetic instruction for X86"));
63 static unsigned getFixupKindLog2Size(unsigned Kind) {
65 default: llvm_unreachable("invalid fixup kind!");
68 case FK_Data_1: return 0;
71 case FK_Data_2: return 1;
73 case X86::reloc_riprel_4byte:
74 case X86::reloc_riprel_4byte_movq_load:
75 case X86::reloc_signed_4byte:
76 case X86::reloc_global_offset_table:
78 case FK_Data_4: return 2;
81 case FK_Data_8: return 3;
87 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
89 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
90 bool HasRelocationAddend, bool foobar)
91 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
94 class X86AsmBackend : public MCAsmBackend {
97 X86AsmBackend(const Target &T, StringRef _CPU)
98 : MCAsmBackend(), CPU(_CPU) {}
100 unsigned getNumFixupKinds() const {
101 return X86::NumTargetFixupKinds;
104 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
105 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
106 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
107 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
108 { "reloc_signed_4byte", 0, 4 * 8, 0},
109 { "reloc_global_offset_table", 0, 4 * 8, 0}
112 if (Kind < FirstTargetFixupKind)
113 return MCAsmBackend::getFixupKindInfo(Kind);
115 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
117 return Infos[Kind - FirstTargetFixupKind];
120 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
121 uint64_t Value) const {
122 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
124 assert(Fixup.getOffset() + Size <= DataSize &&
125 "Invalid fixup offset!");
127 // Check that uppper bits are either all zeros or all ones.
128 // Specifically ignore overflow/underflow as long as the leakage is
129 // limited to the lower bits. This is to remain compatible with
131 assert(isIntN(Size * 8 + 1, Value) &&
132 "Value does not fit in the Fixup field");
134 for (unsigned i = 0; i != Size; ++i)
135 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
138 bool mayNeedRelaxation(const MCInst &Inst) const;
140 bool fixupNeedsRelaxation(const MCFixup &Fixup,
142 const MCRelaxableFragment *DF,
143 const MCAsmLayout &Layout) const;
145 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
147 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
149 } // end anonymous namespace
151 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
156 case X86::JAE_1: return X86::JAE_4;
157 case X86::JA_1: return X86::JA_4;
158 case X86::JBE_1: return X86::JBE_4;
159 case X86::JB_1: return X86::JB_4;
160 case X86::JE_1: return X86::JE_4;
161 case X86::JGE_1: return X86::JGE_4;
162 case X86::JG_1: return X86::JG_4;
163 case X86::JLE_1: return X86::JLE_4;
164 case X86::JL_1: return X86::JL_4;
165 case X86::JMP_1: return X86::JMP_4;
166 case X86::JNE_1: return X86::JNE_4;
167 case X86::JNO_1: return X86::JNO_4;
168 case X86::JNP_1: return X86::JNP_4;
169 case X86::JNS_1: return X86::JNS_4;
170 case X86::JO_1: return X86::JO_4;
171 case X86::JP_1: return X86::JP_4;
172 case X86::JS_1: return X86::JS_4;
176 static unsigned getRelaxedOpcodeArith(unsigned Op) {
182 case X86::IMUL16rri8: return X86::IMUL16rri;
183 case X86::IMUL16rmi8: return X86::IMUL16rmi;
184 case X86::IMUL32rri8: return X86::IMUL32rri;
185 case X86::IMUL32rmi8: return X86::IMUL32rmi;
186 case X86::IMUL64rri8: return X86::IMUL64rri32;
187 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
190 case X86::AND16ri8: return X86::AND16ri;
191 case X86::AND16mi8: return X86::AND16mi;
192 case X86::AND32ri8: return X86::AND32ri;
193 case X86::AND32mi8: return X86::AND32mi;
194 case X86::AND64ri8: return X86::AND64ri32;
195 case X86::AND64mi8: return X86::AND64mi32;
198 case X86::OR16ri8: return X86::OR16ri;
199 case X86::OR16mi8: return X86::OR16mi;
200 case X86::OR32ri8: return X86::OR32ri;
201 case X86::OR32mi8: return X86::OR32mi;
202 case X86::OR64ri8: return X86::OR64ri32;
203 case X86::OR64mi8: return X86::OR64mi32;
206 case X86::XOR16ri8: return X86::XOR16ri;
207 case X86::XOR16mi8: return X86::XOR16mi;
208 case X86::XOR32ri8: return X86::XOR32ri;
209 case X86::XOR32mi8: return X86::XOR32mi;
210 case X86::XOR64ri8: return X86::XOR64ri32;
211 case X86::XOR64mi8: return X86::XOR64mi32;
214 case X86::ADD16ri8: return X86::ADD16ri;
215 case X86::ADD16mi8: return X86::ADD16mi;
216 case X86::ADD32ri8: return X86::ADD32ri;
217 case X86::ADD32mi8: return X86::ADD32mi;
218 case X86::ADD64ri8: return X86::ADD64ri32;
219 case X86::ADD64mi8: return X86::ADD64mi32;
222 case X86::SUB16ri8: return X86::SUB16ri;
223 case X86::SUB16mi8: return X86::SUB16mi;
224 case X86::SUB32ri8: return X86::SUB32ri;
225 case X86::SUB32mi8: return X86::SUB32mi;
226 case X86::SUB64ri8: return X86::SUB64ri32;
227 case X86::SUB64mi8: return X86::SUB64mi32;
230 case X86::CMP16ri8: return X86::CMP16ri;
231 case X86::CMP16mi8: return X86::CMP16mi;
232 case X86::CMP32ri8: return X86::CMP32ri;
233 case X86::CMP32mi8: return X86::CMP32mi;
234 case X86::CMP64ri8: return X86::CMP64ri32;
235 case X86::CMP64mi8: return X86::CMP64mi32;
238 case X86::PUSHi8: return X86::PUSHi32;
239 case X86::PUSHi16: return X86::PUSHi32;
240 case X86::PUSH64i8: return X86::PUSH64i32;
241 case X86::PUSH64i16: return X86::PUSH64i32;
245 static unsigned getRelaxedOpcode(unsigned Op) {
246 unsigned R = getRelaxedOpcodeArith(Op);
249 return getRelaxedOpcodeBranch(Op);
252 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
253 // Branches can always be relaxed.
254 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
257 if (MCDisableArithRelaxation)
260 // Check if this instruction is ever relaxable.
261 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
265 // Check if it has an expression and is not RIP relative.
268 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
269 const MCOperand &Op = Inst.getOperand(i);
273 if (Op.isReg() && Op.getReg() == X86::RIP)
277 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
278 // how we do relaxations?
279 return hasExp && !hasRIP;
282 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
284 const MCRelaxableFragment *DF,
285 const MCAsmLayout &Layout) const {
286 // Relax if the value is too big for a (signed) i8.
287 return int64_t(Value) != int64_t(int8_t(Value));
290 // FIXME: Can tblgen help at all here to verify there aren't other instructions
292 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
293 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
294 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
296 if (RelaxedOp == Inst.getOpcode()) {
297 SmallString<256> Tmp;
298 raw_svector_ostream OS(Tmp);
299 Inst.dump_pretty(OS);
301 report_fatal_error("unexpected instruction to relax: " + OS.str());
305 Res.setOpcode(RelaxedOp);
308 /// \brief Write a sequence of optimal nops to the output, covering \p Count
310 /// \return - true on success, false on failure
311 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
312 static const uint8_t Nops[10][10] = {
320 {0x0f, 0x1f, 0x40, 0x00},
321 // nopl 0(%[re]ax,%[re]ax,1)
322 {0x0f, 0x1f, 0x44, 0x00, 0x00},
323 // nopw 0(%[re]ax,%[re]ax,1)
324 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
326 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
327 // nopl 0L(%[re]ax,%[re]ax,1)
328 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
329 // nopw 0L(%[re]ax,%[re]ax,1)
330 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
331 // nopw %cs:0L(%[re]ax,%[re]ax,1)
332 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
335 // This CPU doesnt support long nops. If needed add more.
336 // FIXME: Can we get this from the subtarget somehow?
337 if (CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" ||
338 CPU == "pentium" || CPU == "pentium-mmx" || CPU == "geode") {
339 for (uint64_t i = 0; i < Count; ++i)
344 // 15 is the longest single nop instruction. Emit as many 15-byte nops as
345 // needed, then emit a nop of the remaining length.
347 const uint8_t ThisNopLength = (uint8_t) std::min(Count, (uint64_t) 15);
348 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
349 for (uint8_t i = 0; i < Prefixes; i++)
351 const uint8_t Rest = ThisNopLength - Prefixes;
352 for (uint8_t i = 0; i < Rest; i++)
353 OW->Write8(Nops[Rest - 1][i]);
354 Count -= ThisNopLength;
355 } while (Count != 0);
363 class ELFX86AsmBackend : public X86AsmBackend {
366 ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU)
367 : X86AsmBackend(T, CPU), OSABI(_OSABI) {
368 HasReliableSymbolDifference = true;
371 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
372 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
373 return ES.getFlags() & ELF::SHF_MERGE;
377 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
379 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
380 : ELFX86AsmBackend(T, OSABI, CPU) {}
382 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
383 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
387 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
389 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
390 : ELFX86AsmBackend(T, OSABI, CPU) {}
392 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
393 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
397 class WindowsX86AsmBackend : public X86AsmBackend {
401 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
402 : X86AsmBackend(T, CPU)
406 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
407 return createX86WinCOFFObjectWriter(OS, Is64Bit);
411 class DarwinX86AsmBackend : public X86AsmBackend {
412 const MCRegisterInfo &MRI;
414 /// \brief Number of registers that can be saved in a compact unwind encoding.
415 enum { CU_NUM_SAVED_REGS = 6 };
417 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
420 unsigned OffsetSize; ///< Offset of a "push" instruction.
421 unsigned PushInstrSize; ///< Size of a "push" instruction.
422 unsigned MoveInstrSize; ///< Size of a "move" instruction.
423 unsigned StackDivide; ///< Amount to adjust stack stize by.
425 /// \brief Implementation of algorithm to generate the compact unwind encoding
426 /// for the CFI instructions.
428 generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
429 if (Instrs.empty()) return 0;
431 // Reset the saved registers.
432 unsigned SavedRegIdx = 0;
433 memset(SavedRegs, 0, sizeof(SavedRegs));
437 // Encode that we are using EBP/RBP as the frame pointer.
438 uint32_t CompactUnwindEncoding = 0;
440 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
441 unsigned InstrOffset = 0;
442 unsigned StackAdjust = 0;
443 unsigned StackSize = 0;
444 unsigned PrevStackSize = 0;
445 unsigned NumDefCFAOffsets = 0;
447 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
448 const MCCFIInstruction &Inst = Instrs[i];
450 switch (Inst.getOperation()) {
452 llvm_unreachable("cannot handle CFI directive for compact unwind!");
453 case MCCFIInstruction::OpDefCfaRegister: {
454 // Defines a frame pointer. E.g.
458 // .cfi_def_cfa_register %rbp
461 assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
462 (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
465 memset(SavedRegs, 0, sizeof(SavedRegs));
468 InstrOffset += MoveInstrSize;
471 case MCCFIInstruction::OpDefCfaOffset: {
472 // Defines a new offset for the CFA. E.g.
478 // .cfi_def_cfa_offset 16
484 // .cfi_def_cfa_offset 80
486 PrevStackSize = StackSize;
487 StackSize = std::abs(Inst.getOffset()) / StackDivide;
491 case MCCFIInstruction::OpOffset: {
492 // Defines a "push" of a callee-saved register. E.g.
500 // .cfi_offset %rbx, -40
501 // .cfi_offset %r14, -32
502 // .cfi_offset %r15, -24
504 if (SavedRegIdx == CU_NUM_SAVED_REGS)
505 // If there are too many saved registers, we cannot use a compact
507 return CU::UNWIND_MODE_DWARF;
509 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
510 SavedRegs[SavedRegIdx++] = Reg;
511 StackAdjust += OffsetSize;
512 InstrOffset += PushInstrSize;
518 StackAdjust /= StackDivide;
521 if ((StackAdjust & 0xFF) != StackAdjust)
522 // Offset was too big for a compact unwind encoding.
523 return CU::UNWIND_MODE_DWARF;
525 // Get the encoding of the saved registers when we have a frame pointer.
526 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
527 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
529 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
530 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
531 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
533 // If the amount of the stack allocation is the size of a register, then
534 // we "push" the RAX/EAX register onto the stack instead of adjusting the
535 // stack pointer with a SUB instruction. We don't support the push of the
536 // RAX/EAX register with compact unwind. So we check for that situation
538 if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
539 StackSize - PrevStackSize == 1) ||
540 (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
541 return CU::UNWIND_MODE_DWARF;
543 SubtractInstrIdx += InstrOffset;
546 if ((StackSize & 0xFF) == StackSize) {
547 // Frameless stack with a small stack size.
548 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
550 // Encode the stack size.
551 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
553 if ((StackAdjust & 0x7) != StackAdjust)
554 // The extra stack adjustments are too big for us to handle.
555 return CU::UNWIND_MODE_DWARF;
557 // Frameless stack with an offset too large for us to encode compactly.
558 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
560 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
562 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
564 // Encode any extra stack stack adjustments (done via push
566 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
569 // Encode the number of registers saved. (Reverse the list first.)
570 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
571 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
573 // Get the encoding of the saved registers when we don't have a frame
575 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
576 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
578 // Encode the register encoding.
579 CompactUnwindEncoding |=
580 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
583 return CompactUnwindEncoding;
587 /// \brief Get the compact unwind number for a given register. The number
588 /// corresponds to the enum lists in compact_unwind_encoding.h.
589 int getCompactUnwindRegNum(unsigned Reg) const {
590 static const uint16_t CU32BitRegs[7] = {
591 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
593 static const uint16_t CU64BitRegs[] = {
594 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
596 const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
597 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
604 /// \brief Return the registers encoded for a compact encoding with a frame
606 uint32_t encodeCompactUnwindRegistersWithFrame() const {
607 // Encode the registers in the order they were saved --- 3-bits per
608 // register. The list of saved registers is assumed to be in reverse
609 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
611 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
612 unsigned Reg = SavedRegs[i];
615 int CURegNum = getCompactUnwindRegNum(Reg);
616 if (CURegNum == -1) return ~0U;
618 // Encode the 3-bit register number in order, skipping over 3-bits for
620 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
623 assert((RegEnc & 0x3FFFF) == RegEnc &&
624 "Invalid compact register encoding!");
628 /// \brief Create the permutation encoding used with frameless stacks. It is
629 /// passed the number of registers to be saved and an array of the registers
631 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
632 // The saved registers are numbered from 1 to 6. In order to encode the
633 // order in which they were saved, we re-number them according to their
634 // place in the register order. The re-numbering is relative to the last
635 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
645 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
646 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
647 if (CUReg == -1) return ~0U;
648 SavedRegs[i] = CUReg;
652 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
654 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
655 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
656 unsigned Countless = 0;
657 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
658 if (SavedRegs[j] < SavedRegs[i])
661 RenumRegs[i] = SavedRegs[i] - Countless - 1;
664 // Take the renumbered values and encode them into a 10-bit number.
665 uint32_t permutationEncoding = 0;
668 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
669 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
673 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
674 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
678 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
679 + 3 * RenumRegs[4] + RenumRegs[5];
682 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
686 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
689 permutationEncoding |= RenumRegs[5];
693 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
694 "Invalid compact register encoding!");
695 return permutationEncoding;
699 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
701 : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
702 memset(SavedRegs, 0, sizeof(SavedRegs));
703 OffsetSize = Is64Bit ? 8 : 4;
704 MoveInstrSize = Is64Bit ? 3 : 2;
705 StackDivide = Is64Bit ? 8 : 4;
710 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
713 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
714 StringRef CPU, bool SupportsCU)
715 : DarwinX86AsmBackend(T, MRI, CPU, false), SupportsCU(SupportsCU) {}
717 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
718 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
719 MachO::CPU_TYPE_I386,
720 MachO::CPU_SUBTYPE_I386_ALL);
723 /// \brief Generate the compact unwind encoding for the CFI instructions.
725 generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const {
726 return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
730 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
733 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
734 StringRef CPU, bool SupportsCU)
735 : DarwinX86AsmBackend(T, MRI, CPU, true), SupportsCU(SupportsCU) {
736 HasReliableSymbolDifference = true;
739 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
740 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
741 MachO::CPU_TYPE_X86_64,
742 MachO::CPU_SUBTYPE_X86_64_ALL);
745 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
746 // Temporary labels in the string literals sections require symbols. The
747 // issue is that the x86_64 relocation format does not allow symbol +
748 // offset, and so the linker does not have enough information to resolve the
749 // access to the appropriate atom unless an external relocation is used. For
750 // non-cstring sections, we expect the compiler to use a non-temporary label
751 // for anything that could have an addend pointing outside the symbol.
753 // See <rdar://problem/4765733>.
754 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
755 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
758 virtual bool isSectionAtomizable(const MCSection &Section) const {
759 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
760 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
761 switch (SMO.getType()) {
765 case MCSectionMachO::S_4BYTE_LITERALS:
766 case MCSectionMachO::S_8BYTE_LITERALS:
767 case MCSectionMachO::S_16BYTE_LITERALS:
768 case MCSectionMachO::S_LITERAL_POINTERS:
769 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
770 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
771 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
772 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
773 case MCSectionMachO::S_INTERPOSING:
778 /// \brief Generate the compact unwind encoding for the CFI instructions.
780 generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const {
781 return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
785 } // end anonymous namespace
787 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
788 const MCRegisterInfo &MRI,
791 Triple TheTriple(TT);
793 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
794 return new DarwinX86_32AsmBackend(T, MRI, CPU,
795 TheTriple.isMacOSX() &&
796 !TheTriple.isMacOSXVersionLT(10, 7));
798 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
799 return new WindowsX86AsmBackend(T, false, CPU);
801 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
802 return new ELFX86_32AsmBackend(T, OSABI, CPU);
805 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
806 const MCRegisterInfo &MRI,
809 Triple TheTriple(TT);
811 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
812 return new DarwinX86_64AsmBackend(T, MRI, CPU,
813 TheTriple.isMacOSX() &&
814 !TheTriple.isMacOSXVersionLT(10, 7));
816 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
817 return new WindowsX86AsmBackend(T, true, CPU);
819 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
820 return new ELFX86_64AsmBackend(T, OSABI, CPU);