1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "MCTargetDesc/X86FixupKinds.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCAsmBackend.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCELFObjectWriter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCFixupKindInfo.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSectionCOFF.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ELF.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/MachO.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
31 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
32 // is useful when running bitwise comparison experiments on Darwin. We should be
33 // able to remove this once PR9807 is resolved.
35 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
36 cl::desc("Disable relaxation of arithmetic instruction for X86"));
38 static unsigned getFixupKindLog2Size(unsigned Kind) {
40 default: llvm_unreachable("invalid fixup kind!");
43 case FK_Data_1: return 0;
46 case FK_Data_2: return 1;
48 case X86::reloc_riprel_4byte:
49 case X86::reloc_riprel_4byte_movq_load:
50 case X86::reloc_signed_4byte:
51 case X86::reloc_global_offset_table:
53 case FK_Data_4: return 2;
56 case FK_Data_8: return 3;
62 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
64 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
65 bool HasRelocationAddend, bool foobar)
66 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
69 class X86AsmBackend : public MCAsmBackend {
73 X86AsmBackend(const Target &T, StringRef _CPU)
74 : MCAsmBackend(), CPU(_CPU) {
75 HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
76 CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
77 CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
78 CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
79 CPU != "c3" && CPU != "c3-2";
82 unsigned getNumFixupKinds() const {
83 return X86::NumTargetFixupKinds;
86 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
87 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
88 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
89 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
90 { "reloc_signed_4byte", 0, 4 * 8, 0},
91 { "reloc_global_offset_table", 0, 4 * 8, 0}
94 if (Kind < FirstTargetFixupKind)
95 return MCAsmBackend::getFixupKindInfo(Kind);
97 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
99 return Infos[Kind - FirstTargetFixupKind];
102 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
103 uint64_t Value) const {
104 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
106 assert(Fixup.getOffset() + Size <= DataSize &&
107 "Invalid fixup offset!");
109 // Check that uppper bits are either all zeros or all ones.
110 // Specifically ignore overflow/underflow as long as the leakage is
111 // limited to the lower bits. This is to remain compatible with
113 assert(isIntN(Size * 8 + 1, Value) &&
114 "Value does not fit in the Fixup field");
116 for (unsigned i = 0; i != Size; ++i)
117 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
120 bool mayNeedRelaxation(const MCInst &Inst) const;
122 bool fixupNeedsRelaxation(const MCFixup &Fixup,
124 const MCRelaxableFragment *DF,
125 const MCAsmLayout &Layout) const;
127 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
129 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
131 } // end anonymous namespace
133 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
138 case X86::JAE_1: return X86::JAE_4;
139 case X86::JA_1: return X86::JA_4;
140 case X86::JBE_1: return X86::JBE_4;
141 case X86::JB_1: return X86::JB_4;
142 case X86::JE_1: return X86::JE_4;
143 case X86::JGE_1: return X86::JGE_4;
144 case X86::JG_1: return X86::JG_4;
145 case X86::JLE_1: return X86::JLE_4;
146 case X86::JL_1: return X86::JL_4;
147 case X86::JMP_1: return X86::JMP_4;
148 case X86::JNE_1: return X86::JNE_4;
149 case X86::JNO_1: return X86::JNO_4;
150 case X86::JNP_1: return X86::JNP_4;
151 case X86::JNS_1: return X86::JNS_4;
152 case X86::JO_1: return X86::JO_4;
153 case X86::JP_1: return X86::JP_4;
154 case X86::JS_1: return X86::JS_4;
158 static unsigned getRelaxedOpcodeArith(unsigned Op) {
164 case X86::IMUL16rri8: return X86::IMUL16rri;
165 case X86::IMUL16rmi8: return X86::IMUL16rmi;
166 case X86::IMUL32rri8: return X86::IMUL32rri;
167 case X86::IMUL32rmi8: return X86::IMUL32rmi;
168 case X86::IMUL64rri8: return X86::IMUL64rri32;
169 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
172 case X86::AND16ri8: return X86::AND16ri;
173 case X86::AND16mi8: return X86::AND16mi;
174 case X86::AND32ri8: return X86::AND32ri;
175 case X86::AND32mi8: return X86::AND32mi;
176 case X86::AND64ri8: return X86::AND64ri32;
177 case X86::AND64mi8: return X86::AND64mi32;
180 case X86::OR16ri8: return X86::OR16ri;
181 case X86::OR16mi8: return X86::OR16mi;
182 case X86::OR32ri8: return X86::OR32ri;
183 case X86::OR32mi8: return X86::OR32mi;
184 case X86::OR64ri8: return X86::OR64ri32;
185 case X86::OR64mi8: return X86::OR64mi32;
188 case X86::XOR16ri8: return X86::XOR16ri;
189 case X86::XOR16mi8: return X86::XOR16mi;
190 case X86::XOR32ri8: return X86::XOR32ri;
191 case X86::XOR32mi8: return X86::XOR32mi;
192 case X86::XOR64ri8: return X86::XOR64ri32;
193 case X86::XOR64mi8: return X86::XOR64mi32;
196 case X86::ADD16ri8: return X86::ADD16ri;
197 case X86::ADD16mi8: return X86::ADD16mi;
198 case X86::ADD32ri8: return X86::ADD32ri;
199 case X86::ADD32mi8: return X86::ADD32mi;
200 case X86::ADD64ri8: return X86::ADD64ri32;
201 case X86::ADD64mi8: return X86::ADD64mi32;
204 case X86::SUB16ri8: return X86::SUB16ri;
205 case X86::SUB16mi8: return X86::SUB16mi;
206 case X86::SUB32ri8: return X86::SUB32ri;
207 case X86::SUB32mi8: return X86::SUB32mi;
208 case X86::SUB64ri8: return X86::SUB64ri32;
209 case X86::SUB64mi8: return X86::SUB64mi32;
212 case X86::CMP16ri8: return X86::CMP16ri;
213 case X86::CMP16mi8: return X86::CMP16mi;
214 case X86::CMP32ri8: return X86::CMP32ri;
215 case X86::CMP32mi8: return X86::CMP32mi;
216 case X86::CMP64ri8: return X86::CMP64ri32;
217 case X86::CMP64mi8: return X86::CMP64mi32;
220 case X86::PUSH32i8: return X86::PUSHi32;
221 case X86::PUSH16i8: return X86::PUSHi16;
222 case X86::PUSH64i8: return X86::PUSH64i32;
223 case X86::PUSH64i16: return X86::PUSH64i32;
227 static unsigned getRelaxedOpcode(unsigned Op) {
228 unsigned R = getRelaxedOpcodeArith(Op);
231 return getRelaxedOpcodeBranch(Op);
234 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
235 // Branches can always be relaxed.
236 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
239 if (MCDisableArithRelaxation)
242 // Check if this instruction is ever relaxable.
243 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
247 // Check if it has an expression and is not RIP relative.
250 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
251 const MCOperand &Op = Inst.getOperand(i);
255 if (Op.isReg() && Op.getReg() == X86::RIP)
259 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
260 // how we do relaxations?
261 return hasExp && !hasRIP;
264 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
266 const MCRelaxableFragment *DF,
267 const MCAsmLayout &Layout) const {
268 // Relax if the value is too big for a (signed) i8.
269 return int64_t(Value) != int64_t(int8_t(Value));
272 // FIXME: Can tblgen help at all here to verify there aren't other instructions
274 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
275 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
276 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
278 if (RelaxedOp == Inst.getOpcode()) {
279 SmallString<256> Tmp;
280 raw_svector_ostream OS(Tmp);
281 Inst.dump_pretty(OS);
283 report_fatal_error("unexpected instruction to relax: " + OS.str());
287 Res.setOpcode(RelaxedOp);
290 /// \brief Write a sequence of optimal nops to the output, covering \p Count
292 /// \return - true on success, false on failure
293 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
294 static const uint8_t Nops[10][10] = {
302 {0x0f, 0x1f, 0x40, 0x00},
303 // nopl 0(%[re]ax,%[re]ax,1)
304 {0x0f, 0x1f, 0x44, 0x00, 0x00},
305 // nopw 0(%[re]ax,%[re]ax,1)
306 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
308 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
309 // nopl 0L(%[re]ax,%[re]ax,1)
310 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
311 // nopw 0L(%[re]ax,%[re]ax,1)
312 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
313 // nopw %cs:0L(%[re]ax,%[re]ax,1)
314 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
317 // This CPU doesn't support long nops. If needed add more.
318 // FIXME: Can we get this from the subtarget somehow?
319 // FIXME: We could generated something better than plain 0x90.
321 for (uint64_t i = 0; i < Count; ++i)
326 // 15 is the longest single nop instruction. Emit as many 15-byte nops as
327 // needed, then emit a nop of the remaining length.
329 const uint8_t ThisNopLength = (uint8_t) std::min(Count, (uint64_t) 15);
330 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
331 for (uint8_t i = 0; i < Prefixes; i++)
333 const uint8_t Rest = ThisNopLength - Prefixes;
334 for (uint8_t i = 0; i < Rest; i++)
335 OW->Write8(Nops[Rest - 1][i]);
336 Count -= ThisNopLength;
337 } while (Count != 0);
346 class ELFX86AsmBackend : public X86AsmBackend {
349 ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU)
350 : X86AsmBackend(T, CPU), OSABI(_OSABI) {}
353 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
355 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
356 : ELFX86AsmBackend(T, OSABI, CPU) {}
358 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
359 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
363 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
365 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
366 : ELFX86AsmBackend(T, OSABI, CPU) {}
368 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
369 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
373 class WindowsX86AsmBackend : public X86AsmBackend {
377 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
378 : X86AsmBackend(T, CPU)
382 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
383 return createX86WinCOFFObjectWriter(OS, Is64Bit);
389 /// Compact unwind encoding values.
390 enum CompactUnwindEncodings {
391 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
392 /// the return address, then [RE]SP is moved to [RE]BP.
393 UNWIND_MODE_BP_FRAME = 0x01000000,
395 /// A frameless function with a small constant stack size.
396 UNWIND_MODE_STACK_IMMD = 0x02000000,
398 /// A frameless function with a large constant stack size.
399 UNWIND_MODE_STACK_IND = 0x03000000,
401 /// No compact unwind encoding is available.
402 UNWIND_MODE_DWARF = 0x04000000,
404 /// Mask for encoding the frame registers.
405 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
407 /// Mask for encoding the frameless registers.
408 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
411 } // end CU namespace
413 class DarwinX86AsmBackend : public X86AsmBackend {
414 const MCRegisterInfo &MRI;
416 /// \brief Number of registers that can be saved in a compact unwind encoding.
417 enum { CU_NUM_SAVED_REGS = 6 };
419 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
422 unsigned OffsetSize; ///< Offset of a "push" instruction.
423 unsigned PushInstrSize; ///< Size of a "push" instruction.
424 unsigned MoveInstrSize; ///< Size of a "move" instruction.
425 unsigned StackDivide; ///< Amount to adjust stack stize by.
427 /// \brief Implementation of algorithm to generate the compact unwind encoding
428 /// for the CFI instructions.
430 generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
431 if (Instrs.empty()) return 0;
433 // Reset the saved registers.
434 unsigned SavedRegIdx = 0;
435 memset(SavedRegs, 0, sizeof(SavedRegs));
439 // Encode that we are using EBP/RBP as the frame pointer.
440 uint32_t CompactUnwindEncoding = 0;
442 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
443 unsigned InstrOffset = 0;
444 unsigned StackAdjust = 0;
445 unsigned StackSize = 0;
446 unsigned PrevStackSize = 0;
447 unsigned NumDefCFAOffsets = 0;
449 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
450 const MCCFIInstruction &Inst = Instrs[i];
452 switch (Inst.getOperation()) {
454 // Any other CFI directives indicate a frame that we aren't prepared
455 // to represent via compact unwind, so just bail out.
457 case MCCFIInstruction::OpDefCfaRegister: {
458 // Defines a frame pointer. E.g.
462 // .cfi_def_cfa_register %rbp
465 assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
466 (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
469 memset(SavedRegs, 0, sizeof(SavedRegs));
472 InstrOffset += MoveInstrSize;
475 case MCCFIInstruction::OpDefCfaOffset: {
476 // Defines a new offset for the CFA. E.g.
482 // .cfi_def_cfa_offset 16
488 // .cfi_def_cfa_offset 80
490 PrevStackSize = StackSize;
491 StackSize = std::abs(Inst.getOffset()) / StackDivide;
495 case MCCFIInstruction::OpOffset: {
496 // Defines a "push" of a callee-saved register. E.g.
504 // .cfi_offset %rbx, -40
505 // .cfi_offset %r14, -32
506 // .cfi_offset %r15, -24
508 if (SavedRegIdx == CU_NUM_SAVED_REGS)
509 // If there are too many saved registers, we cannot use a compact
511 return CU::UNWIND_MODE_DWARF;
513 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
514 SavedRegs[SavedRegIdx++] = Reg;
515 StackAdjust += OffsetSize;
516 InstrOffset += PushInstrSize;
522 StackAdjust /= StackDivide;
525 if ((StackAdjust & 0xFF) != StackAdjust)
526 // Offset was too big for a compact unwind encoding.
527 return CU::UNWIND_MODE_DWARF;
529 // Get the encoding of the saved registers when we have a frame pointer.
530 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
531 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
533 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
534 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
535 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
537 // If the amount of the stack allocation is the size of a register, then
538 // we "push" the RAX/EAX register onto the stack instead of adjusting the
539 // stack pointer with a SUB instruction. We don't support the push of the
540 // RAX/EAX register with compact unwind. So we check for that situation
542 if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
543 StackSize - PrevStackSize == 1) ||
544 (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
545 return CU::UNWIND_MODE_DWARF;
547 SubtractInstrIdx += InstrOffset;
550 if ((StackSize & 0xFF) == StackSize) {
551 // Frameless stack with a small stack size.
552 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
554 // Encode the stack size.
555 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
557 if ((StackAdjust & 0x7) != StackAdjust)
558 // The extra stack adjustments are too big for us to handle.
559 return CU::UNWIND_MODE_DWARF;
561 // Frameless stack with an offset too large for us to encode compactly.
562 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
564 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
566 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
568 // Encode any extra stack stack adjustments (done via push
570 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
573 // Encode the number of registers saved. (Reverse the list first.)
574 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
575 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
577 // Get the encoding of the saved registers when we don't have a frame
579 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
580 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
582 // Encode the register encoding.
583 CompactUnwindEncoding |=
584 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
587 return CompactUnwindEncoding;
591 /// \brief Get the compact unwind number for a given register. The number
592 /// corresponds to the enum lists in compact_unwind_encoding.h.
593 int getCompactUnwindRegNum(unsigned Reg) const {
594 static const uint16_t CU32BitRegs[7] = {
595 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
597 static const uint16_t CU64BitRegs[] = {
598 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
600 const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
601 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
608 /// \brief Return the registers encoded for a compact encoding with a frame
610 uint32_t encodeCompactUnwindRegistersWithFrame() const {
611 // Encode the registers in the order they were saved --- 3-bits per
612 // register. The list of saved registers is assumed to be in reverse
613 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
615 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
616 unsigned Reg = SavedRegs[i];
619 int CURegNum = getCompactUnwindRegNum(Reg);
620 if (CURegNum == -1) return ~0U;
622 // Encode the 3-bit register number in order, skipping over 3-bits for
624 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
627 assert((RegEnc & 0x3FFFF) == RegEnc &&
628 "Invalid compact register encoding!");
632 /// \brief Create the permutation encoding used with frameless stacks. It is
633 /// passed the number of registers to be saved and an array of the registers
635 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
636 // The saved registers are numbered from 1 to 6. In order to encode the
637 // order in which they were saved, we re-number them according to their
638 // place in the register order. The re-numbering is relative to the last
639 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
649 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
650 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
651 if (CUReg == -1) return ~0U;
652 SavedRegs[i] = CUReg;
656 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
658 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
659 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
660 unsigned Countless = 0;
661 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
662 if (SavedRegs[j] < SavedRegs[i])
665 RenumRegs[i] = SavedRegs[i] - Countless - 1;
668 // Take the renumbered values and encode them into a 10-bit number.
669 uint32_t permutationEncoding = 0;
672 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
673 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
677 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
678 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
682 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
683 + 3 * RenumRegs[4] + RenumRegs[5];
686 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
690 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
693 permutationEncoding |= RenumRegs[5];
697 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
698 "Invalid compact register encoding!");
699 return permutationEncoding;
703 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
705 : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
706 memset(SavedRegs, 0, sizeof(SavedRegs));
707 OffsetSize = Is64Bit ? 8 : 4;
708 MoveInstrSize = Is64Bit ? 3 : 2;
709 StackDivide = Is64Bit ? 8 : 4;
714 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
717 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
718 StringRef CPU, bool SupportsCU)
719 : DarwinX86AsmBackend(T, MRI, CPU, false), SupportsCU(SupportsCU) {}
721 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
722 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
723 MachO::CPU_TYPE_I386,
724 MachO::CPU_SUBTYPE_I386_ALL);
727 /// \brief Generate the compact unwind encoding for the CFI instructions.
729 generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const {
730 return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
734 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
736 const MachO::CPUSubTypeX86 Subtype;
738 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
739 StringRef CPU, bool SupportsCU,
740 MachO::CPUSubTypeX86 st)
741 : DarwinX86AsmBackend(T, MRI, CPU, true), SupportsCU(SupportsCU),
743 HasReliableSymbolDifference = true;
746 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
747 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
748 MachO::CPU_TYPE_X86_64, Subtype);
751 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
752 // Temporary labels in the string literals sections require symbols. The
753 // issue is that the x86_64 relocation format does not allow symbol +
754 // offset, and so the linker does not have enough information to resolve the
755 // access to the appropriate atom unless an external relocation is used. For
756 // non-cstring sections, we expect the compiler to use a non-temporary label
757 // for anything that could have an addend pointing outside the symbol.
759 // See <rdar://problem/4765733>.
760 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
761 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
764 virtual bool isSectionAtomizable(const MCSection &Section) const {
765 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
766 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
767 switch (SMO.getType()) {
771 case MCSectionMachO::S_4BYTE_LITERALS:
772 case MCSectionMachO::S_8BYTE_LITERALS:
773 case MCSectionMachO::S_16BYTE_LITERALS:
774 case MCSectionMachO::S_LITERAL_POINTERS:
775 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
776 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
777 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
778 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
779 case MCSectionMachO::S_INTERPOSING:
784 /// \brief Generate the compact unwind encoding for the CFI instructions.
786 generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const {
787 return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
791 } // end anonymous namespace
793 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
794 const MCRegisterInfo &MRI,
797 Triple TheTriple(TT);
799 if (TheTriple.isOSBinFormatMachO())
800 return new DarwinX86_32AsmBackend(T, MRI, CPU,
801 TheTriple.isMacOSX() &&
802 !TheTriple.isMacOSXVersionLT(10, 7));
804 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
805 return new WindowsX86AsmBackend(T, false, CPU);
807 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
808 return new ELFX86_32AsmBackend(T, OSABI, CPU);
811 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
812 const MCRegisterInfo &MRI,
815 Triple TheTriple(TT);
817 if (TheTriple.isOSBinFormatMachO()) {
818 MachO::CPUSubTypeX86 CS =
819 StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
820 .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
821 .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
822 return new DarwinX86_64AsmBackend(T, MRI, CPU,
823 TheTriple.isMacOSX() &&
824 !TheTriple.isMacOSXVersionLT(10, 7), CS);
827 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
828 return new WindowsX86AsmBackend(T, true, CPU);
830 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
831 return new ELFX86_64AsmBackend(T, OSABI, CPU);