1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "MCTargetDesc/X86FixupKinds.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCELFObjectWriter.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCMachObjectWriter.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionCOFF.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/ELF.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MachO.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
30 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
31 // is useful when running bitwise comparison experiments on Darwin. We should be
32 // able to remove this once PR9807 is resolved.
34 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
35 cl::desc("Disable relaxation of arithmetic instruction for X86"));
37 static unsigned getFixupKindLog2Size(unsigned Kind) {
39 default: llvm_unreachable("invalid fixup kind!");
42 case FK_Data_1: return 0;
45 case FK_Data_2: return 1;
47 case X86::reloc_riprel_4byte:
48 case X86::reloc_riprel_4byte_movq_load:
49 case X86::reloc_signed_4byte:
50 case X86::reloc_global_offset_table:
52 case FK_Data_4: return 2;
55 case FK_Data_8: return 3;
61 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
63 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
64 bool HasRelocationAddend, bool foobar)
65 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
68 class X86AsmBackend : public MCAsmBackend {
71 X86AsmBackend(const Target &T, StringRef _CPU)
72 : MCAsmBackend(), CPU(_CPU) {}
74 unsigned getNumFixupKinds() const {
75 return X86::NumTargetFixupKinds;
78 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
79 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
80 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
81 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
82 { "reloc_signed_4byte", 0, 4 * 8, 0},
83 { "reloc_global_offset_table", 0, 4 * 8, 0}
86 if (Kind < FirstTargetFixupKind)
87 return MCAsmBackend::getFixupKindInfo(Kind);
89 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
91 return Infos[Kind - FirstTargetFixupKind];
94 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
95 uint64_t Value) const {
96 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
98 assert(Fixup.getOffset() + Size <= DataSize &&
99 "Invalid fixup offset!");
101 // Check that uppper bits are either all zeros or all ones.
102 // Specifically ignore overflow/underflow as long as the leakage is
103 // limited to the lower bits. This is to remain compatible with
105 assert(isIntN(Size * 8 + 1, Value) &&
106 "Value does not fit in the Fixup field");
108 for (unsigned i = 0; i != Size; ++i)
109 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
112 bool mayNeedRelaxation(const MCInst &Inst) const;
114 bool fixupNeedsRelaxation(const MCFixup &Fixup,
116 const MCRelaxableFragment *DF,
117 const MCAsmLayout &Layout) const;
119 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
121 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
123 } // end anonymous namespace
125 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
130 case X86::JAE_1: return X86::JAE_4;
131 case X86::JA_1: return X86::JA_4;
132 case X86::JBE_1: return X86::JBE_4;
133 case X86::JB_1: return X86::JB_4;
134 case X86::JE_1: return X86::JE_4;
135 case X86::JGE_1: return X86::JGE_4;
136 case X86::JG_1: return X86::JG_4;
137 case X86::JLE_1: return X86::JLE_4;
138 case X86::JL_1: return X86::JL_4;
139 case X86::JMP_1: return X86::JMP_4;
140 case X86::JNE_1: return X86::JNE_4;
141 case X86::JNO_1: return X86::JNO_4;
142 case X86::JNP_1: return X86::JNP_4;
143 case X86::JNS_1: return X86::JNS_4;
144 case X86::JO_1: return X86::JO_4;
145 case X86::JP_1: return X86::JP_4;
146 case X86::JS_1: return X86::JS_4;
150 static unsigned getRelaxedOpcodeArith(unsigned Op) {
156 case X86::IMUL16rri8: return X86::IMUL16rri;
157 case X86::IMUL16rmi8: return X86::IMUL16rmi;
158 case X86::IMUL32rri8: return X86::IMUL32rri;
159 case X86::IMUL32rmi8: return X86::IMUL32rmi;
160 case X86::IMUL64rri8: return X86::IMUL64rri32;
161 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
164 case X86::AND16ri8: return X86::AND16ri;
165 case X86::AND16mi8: return X86::AND16mi;
166 case X86::AND32ri8: return X86::AND32ri;
167 case X86::AND32mi8: return X86::AND32mi;
168 case X86::AND64ri8: return X86::AND64ri32;
169 case X86::AND64mi8: return X86::AND64mi32;
172 case X86::OR16ri8: return X86::OR16ri;
173 case X86::OR16mi8: return X86::OR16mi;
174 case X86::OR32ri8: return X86::OR32ri;
175 case X86::OR32mi8: return X86::OR32mi;
176 case X86::OR64ri8: return X86::OR64ri32;
177 case X86::OR64mi8: return X86::OR64mi32;
180 case X86::XOR16ri8: return X86::XOR16ri;
181 case X86::XOR16mi8: return X86::XOR16mi;
182 case X86::XOR32ri8: return X86::XOR32ri;
183 case X86::XOR32mi8: return X86::XOR32mi;
184 case X86::XOR64ri8: return X86::XOR64ri32;
185 case X86::XOR64mi8: return X86::XOR64mi32;
188 case X86::ADD16ri8: return X86::ADD16ri;
189 case X86::ADD16mi8: return X86::ADD16mi;
190 case X86::ADD32ri8: return X86::ADD32ri;
191 case X86::ADD32mi8: return X86::ADD32mi;
192 case X86::ADD64ri8: return X86::ADD64ri32;
193 case X86::ADD64mi8: return X86::ADD64mi32;
196 case X86::SUB16ri8: return X86::SUB16ri;
197 case X86::SUB16mi8: return X86::SUB16mi;
198 case X86::SUB32ri8: return X86::SUB32ri;
199 case X86::SUB32mi8: return X86::SUB32mi;
200 case X86::SUB64ri8: return X86::SUB64ri32;
201 case X86::SUB64mi8: return X86::SUB64mi32;
204 case X86::CMP16ri8: return X86::CMP16ri;
205 case X86::CMP16mi8: return X86::CMP16mi;
206 case X86::CMP32ri8: return X86::CMP32ri;
207 case X86::CMP32mi8: return X86::CMP32mi;
208 case X86::CMP64ri8: return X86::CMP64ri32;
209 case X86::CMP64mi8: return X86::CMP64mi32;
212 case X86::PUSHi8: return X86::PUSHi32;
213 case X86::PUSHi16: return X86::PUSHi32;
214 case X86::PUSH64i8: return X86::PUSH64i32;
215 case X86::PUSH64i16: return X86::PUSH64i32;
219 static unsigned getRelaxedOpcode(unsigned Op) {
220 unsigned R = getRelaxedOpcodeArith(Op);
223 return getRelaxedOpcodeBranch(Op);
226 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
227 // Branches can always be relaxed.
228 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
231 if (MCDisableArithRelaxation)
234 // Check if this instruction is ever relaxable.
235 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
239 // Check if it has an expression and is not RIP relative.
242 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
243 const MCOperand &Op = Inst.getOperand(i);
247 if (Op.isReg() && Op.getReg() == X86::RIP)
251 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
252 // how we do relaxations?
253 return hasExp && !hasRIP;
256 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
258 const MCRelaxableFragment *DF,
259 const MCAsmLayout &Layout) const {
260 // Relax if the value is too big for a (signed) i8.
261 return int64_t(Value) != int64_t(int8_t(Value));
264 // FIXME: Can tblgen help at all here to verify there aren't other instructions
266 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
267 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
268 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
270 if (RelaxedOp == Inst.getOpcode()) {
271 SmallString<256> Tmp;
272 raw_svector_ostream OS(Tmp);
273 Inst.dump_pretty(OS);
275 report_fatal_error("unexpected instruction to relax: " + OS.str());
279 Res.setOpcode(RelaxedOp);
282 /// \brief Write a sequence of optimal nops to the output, covering \p Count
284 /// \return - true on success, false on failure
285 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
286 static const uint8_t Nops[10][10] = {
294 {0x0f, 0x1f, 0x40, 0x00},
295 // nopl 0(%[re]ax,%[re]ax,1)
296 {0x0f, 0x1f, 0x44, 0x00, 0x00},
297 // nopw 0(%[re]ax,%[re]ax,1)
298 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
300 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
301 // nopl 0L(%[re]ax,%[re]ax,1)
302 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
303 // nopw 0L(%[re]ax,%[re]ax,1)
304 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
305 // nopw %cs:0L(%[re]ax,%[re]ax,1)
306 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
309 // This CPU doesnt support long nops. If needed add more.
310 // FIXME: Can we get this from the subtarget somehow?
311 if (CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" ||
312 CPU == "pentium" || CPU == "pentium-mmx" || CPU == "geode") {
313 for (uint64_t i = 0; i < Count; ++i)
318 // 15 is the longest single nop instruction. Emit as many 15-byte nops as
319 // needed, then emit a nop of the remaining length.
321 const uint8_t ThisNopLength = (uint8_t) std::min(Count, (uint64_t) 15);
322 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
323 for (uint8_t i = 0; i < Prefixes; i++)
325 const uint8_t Rest = ThisNopLength - Prefixes;
326 for (uint8_t i = 0; i < Rest; i++)
327 OW->Write8(Nops[Rest - 1][i]);
328 Count -= ThisNopLength;
329 } while (Count != 0);
338 class ELFX86AsmBackend : public X86AsmBackend {
341 ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU)
342 : X86AsmBackend(T, CPU), OSABI(_OSABI) {
343 HasReliableSymbolDifference = true;
346 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
347 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
348 return ES.getFlags() & ELF::SHF_MERGE;
352 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
354 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
355 : ELFX86AsmBackend(T, OSABI, CPU) {}
357 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
358 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
362 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
364 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
365 : ELFX86AsmBackend(T, OSABI, CPU) {}
367 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
368 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
372 class WindowsX86AsmBackend : public X86AsmBackend {
376 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
377 : X86AsmBackend(T, CPU)
381 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
382 return createX86WinCOFFObjectWriter(OS, Is64Bit);
388 /// Compact unwind encoding values.
389 enum CompactUnwindEncodings {
390 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
391 /// the return address, then [RE]SP is moved to [RE]BP.
392 UNWIND_MODE_BP_FRAME = 0x01000000,
394 /// A frameless function with a small constant stack size.
395 UNWIND_MODE_STACK_IMMD = 0x02000000,
397 /// A frameless function with a large constant stack size.
398 UNWIND_MODE_STACK_IND = 0x03000000,
400 /// No compact unwind encoding is available.
401 UNWIND_MODE_DWARF = 0x04000000,
403 /// Mask for encoding the frame registers.
404 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
406 /// Mask for encoding the frameless registers.
407 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
410 } // end CU namespace
412 class DarwinX86AsmBackend : public X86AsmBackend {
413 const MCRegisterInfo &MRI;
415 /// \brief Number of registers that can be saved in a compact unwind encoding.
416 enum { CU_NUM_SAVED_REGS = 6 };
418 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
421 unsigned OffsetSize; ///< Offset of a "push" instruction.
422 unsigned PushInstrSize; ///< Size of a "push" instruction.
423 unsigned MoveInstrSize; ///< Size of a "move" instruction.
424 unsigned StackDivide; ///< Amount to adjust stack stize by.
426 /// \brief Implementation of algorithm to generate the compact unwind encoding
427 /// for the CFI instructions.
429 generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
430 if (Instrs.empty()) return 0;
432 // Reset the saved registers.
433 unsigned SavedRegIdx = 0;
434 memset(SavedRegs, 0, sizeof(SavedRegs));
438 // Encode that we are using EBP/RBP as the frame pointer.
439 uint32_t CompactUnwindEncoding = 0;
441 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
442 unsigned InstrOffset = 0;
443 unsigned StackAdjust = 0;
444 unsigned StackSize = 0;
445 unsigned PrevStackSize = 0;
446 unsigned NumDefCFAOffsets = 0;
448 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
449 const MCCFIInstruction &Inst = Instrs[i];
451 switch (Inst.getOperation()) {
453 llvm_unreachable("cannot handle CFI directive for compact unwind!");
454 case MCCFIInstruction::OpDefCfaRegister: {
455 // Defines a frame pointer. E.g.
459 // .cfi_def_cfa_register %rbp
462 assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
463 (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
466 memset(SavedRegs, 0, sizeof(SavedRegs));
469 InstrOffset += MoveInstrSize;
472 case MCCFIInstruction::OpDefCfaOffset: {
473 // Defines a new offset for the CFA. E.g.
479 // .cfi_def_cfa_offset 16
485 // .cfi_def_cfa_offset 80
487 PrevStackSize = StackSize;
488 StackSize = std::abs(Inst.getOffset()) / StackDivide;
492 case MCCFIInstruction::OpOffset: {
493 // Defines a "push" of a callee-saved register. E.g.
501 // .cfi_offset %rbx, -40
502 // .cfi_offset %r14, -32
503 // .cfi_offset %r15, -24
505 if (SavedRegIdx == CU_NUM_SAVED_REGS)
506 // If there are too many saved registers, we cannot use a compact
508 return CU::UNWIND_MODE_DWARF;
510 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
511 SavedRegs[SavedRegIdx++] = Reg;
512 StackAdjust += OffsetSize;
513 InstrOffset += PushInstrSize;
519 StackAdjust /= StackDivide;
522 if ((StackAdjust & 0xFF) != StackAdjust)
523 // Offset was too big for a compact unwind encoding.
524 return CU::UNWIND_MODE_DWARF;
526 // Get the encoding of the saved registers when we have a frame pointer.
527 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
528 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
530 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
531 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
532 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
534 // If the amount of the stack allocation is the size of a register, then
535 // we "push" the RAX/EAX register onto the stack instead of adjusting the
536 // stack pointer with a SUB instruction. We don't support the push of the
537 // RAX/EAX register with compact unwind. So we check for that situation
539 if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
540 StackSize - PrevStackSize == 1) ||
541 (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
542 return CU::UNWIND_MODE_DWARF;
544 SubtractInstrIdx += InstrOffset;
547 if ((StackSize & 0xFF) == StackSize) {
548 // Frameless stack with a small stack size.
549 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
551 // Encode the stack size.
552 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
554 if ((StackAdjust & 0x7) != StackAdjust)
555 // The extra stack adjustments are too big for us to handle.
556 return CU::UNWIND_MODE_DWARF;
558 // Frameless stack with an offset too large for us to encode compactly.
559 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
561 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
563 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
565 // Encode any extra stack stack adjustments (done via push
567 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
570 // Encode the number of registers saved. (Reverse the list first.)
571 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
572 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
574 // Get the encoding of the saved registers when we don't have a frame
576 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
577 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
579 // Encode the register encoding.
580 CompactUnwindEncoding |=
581 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
584 return CompactUnwindEncoding;
588 /// \brief Get the compact unwind number for a given register. The number
589 /// corresponds to the enum lists in compact_unwind_encoding.h.
590 int getCompactUnwindRegNum(unsigned Reg) const {
591 static const uint16_t CU32BitRegs[7] = {
592 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
594 static const uint16_t CU64BitRegs[] = {
595 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
597 const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
598 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
605 /// \brief Return the registers encoded for a compact encoding with a frame
607 uint32_t encodeCompactUnwindRegistersWithFrame() const {
608 // Encode the registers in the order they were saved --- 3-bits per
609 // register. The list of saved registers is assumed to be in reverse
610 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
612 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
613 unsigned Reg = SavedRegs[i];
616 int CURegNum = getCompactUnwindRegNum(Reg);
617 if (CURegNum == -1) return ~0U;
619 // Encode the 3-bit register number in order, skipping over 3-bits for
621 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
624 assert((RegEnc & 0x3FFFF) == RegEnc &&
625 "Invalid compact register encoding!");
629 /// \brief Create the permutation encoding used with frameless stacks. It is
630 /// passed the number of registers to be saved and an array of the registers
632 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
633 // The saved registers are numbered from 1 to 6. In order to encode the
634 // order in which they were saved, we re-number them according to their
635 // place in the register order. The re-numbering is relative to the last
636 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
646 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
647 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
648 if (CUReg == -1) return ~0U;
649 SavedRegs[i] = CUReg;
653 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
655 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
656 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
657 unsigned Countless = 0;
658 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
659 if (SavedRegs[j] < SavedRegs[i])
662 RenumRegs[i] = SavedRegs[i] - Countless - 1;
665 // Take the renumbered values and encode them into a 10-bit number.
666 uint32_t permutationEncoding = 0;
669 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
670 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
674 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
675 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
679 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
680 + 3 * RenumRegs[4] + RenumRegs[5];
683 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
687 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
690 permutationEncoding |= RenumRegs[5];
694 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
695 "Invalid compact register encoding!");
696 return permutationEncoding;
700 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
702 : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
703 memset(SavedRegs, 0, sizeof(SavedRegs));
704 OffsetSize = Is64Bit ? 8 : 4;
705 MoveInstrSize = Is64Bit ? 3 : 2;
706 StackDivide = Is64Bit ? 8 : 4;
711 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
714 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
715 StringRef CPU, bool SupportsCU)
716 : DarwinX86AsmBackend(T, MRI, CPU, false), SupportsCU(SupportsCU) {}
718 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
719 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
720 MachO::CPU_TYPE_I386,
721 MachO::CPU_SUBTYPE_I386_ALL);
724 /// \brief Generate the compact unwind encoding for the CFI instructions.
726 generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const {
727 return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
731 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
734 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
735 StringRef CPU, bool SupportsCU)
736 : DarwinX86AsmBackend(T, MRI, CPU, true), SupportsCU(SupportsCU) {
737 HasReliableSymbolDifference = true;
740 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
741 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
742 MachO::CPU_TYPE_X86_64,
743 MachO::CPU_SUBTYPE_X86_64_ALL);
746 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
747 // Temporary labels in the string literals sections require symbols. The
748 // issue is that the x86_64 relocation format does not allow symbol +
749 // offset, and so the linker does not have enough information to resolve the
750 // access to the appropriate atom unless an external relocation is used. For
751 // non-cstring sections, we expect the compiler to use a non-temporary label
752 // for anything that could have an addend pointing outside the symbol.
754 // See <rdar://problem/4765733>.
755 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
756 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
759 virtual bool isSectionAtomizable(const MCSection &Section) const {
760 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
761 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
762 switch (SMO.getType()) {
766 case MCSectionMachO::S_4BYTE_LITERALS:
767 case MCSectionMachO::S_8BYTE_LITERALS:
768 case MCSectionMachO::S_16BYTE_LITERALS:
769 case MCSectionMachO::S_LITERAL_POINTERS:
770 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
771 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
772 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
773 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
774 case MCSectionMachO::S_INTERPOSING:
779 /// \brief Generate the compact unwind encoding for the CFI instructions.
781 generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const {
782 return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
786 } // end anonymous namespace
788 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
789 const MCRegisterInfo &MRI,
792 Triple TheTriple(TT);
794 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
795 return new DarwinX86_32AsmBackend(T, MRI, CPU,
796 TheTriple.isMacOSX() &&
797 !TheTriple.isMacOSXVersionLT(10, 7));
799 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
800 return new WindowsX86AsmBackend(T, false, CPU);
802 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
803 return new ELFX86_32AsmBackend(T, OSABI, CPU);
806 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
807 const MCRegisterInfo &MRI,
810 Triple TheTriple(TT);
812 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
813 return new DarwinX86_64AsmBackend(T, MRI, CPU,
814 TheTriple.isMacOSX() &&
815 !TheTriple.isMacOSXVersionLT(10, 7));
817 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
818 return new WindowsX86AsmBackend(T, true, CPU);
820 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
821 return new ELFX86_64AsmBackend(T, OSABI, CPU);