1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/IntrinsicLowering.h"
23 #include "llvm/Pass.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SSARegMap.h"
29 #include "llvm/Target/MRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/InstVisitor.h"
34 /// BMI - A special BuildMI variant that takes an iterator to insert the
35 /// instruction at as well as a basic block. This is the version for when you
36 /// have a destination register in mind.
37 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
38 MachineBasicBlock::iterator &I,
39 int Opcode, unsigned NumOperands,
41 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
42 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
43 I = MBB->insert(I, MI)+1;
44 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
47 /// BMI - A special BuildMI variant that takes an iterator to insert the
48 /// instruction at as well as a basic block.
49 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
50 MachineBasicBlock::iterator &I,
51 int Opcode, unsigned NumOperands) {
52 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
53 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
54 I = MBB->insert(I, MI)+1;
55 return MachineInstrBuilder(MI);
60 struct ISel : public FunctionPass, InstVisitor<ISel> {
62 IntrinsicLowering &IL;
63 MachineFunction *F; // The function we are compiling into
64 MachineBasicBlock *BB; // The current MBB we are compiling
65 int VarArgsFrameIndex; // FrameIndex for start of varargs area
67 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
69 // MBBMap - Mapping between LLVM BB -> Machine BB
70 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
72 ISel(TargetMachine &tm, IntrinsicLowering &il)
73 : TM(tm), IL(il), F(0), BB(0) {}
75 /// runOnFunction - Top level implementation of instruction selection for
76 /// the entire function.
78 bool runOnFunction(Function &Fn) {
79 // First pass over the function, lower any unknown intrinsic functions
80 // with the IntrinsicLowering class.
81 LowerUnknownIntrinsicFunctionCalls(Fn);
83 F = &MachineFunction::construct(&Fn, TM);
85 // Create all of the machine basic blocks for the function...
86 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
87 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
91 // Copy incoming arguments off of the stack...
92 LoadArgumentsToVirtualRegs(Fn);
94 // Instruction select everything except PHI nodes
97 // Select the PHI nodes
103 // We always build a machine code representation for the function
107 virtual const char *getPassName() const {
108 return "X86 Simple Instruction Selection";
111 /// visitBasicBlock - This method is called when we are visiting a new basic
112 /// block. This simply creates a new MachineBasicBlock to emit code into
113 /// and adds it to the current MachineFunction. Subsequent visit* for
114 /// instructions will be invoked for all instructions in the basic block.
116 void visitBasicBlock(BasicBlock &LLVM_BB) {
117 BB = MBBMap[&LLVM_BB];
120 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
121 /// function, lowering any calls to unknown intrinsic functions into the
122 /// equivalent LLVM code.
123 void LowerUnknownIntrinsicFunctionCalls(Function &F);
125 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
126 /// from the stack into virtual registers.
128 void LoadArgumentsToVirtualRegs(Function &F);
130 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
131 /// because we have to generate our sources into the source basic blocks,
132 /// not the current one.
134 void SelectPHINodes();
136 // Visitation methods for various instructions. These methods simply emit
137 // fixed X86 code for each instruction.
140 // Control flow operators
141 void visitReturnInst(ReturnInst &RI);
142 void visitBranchInst(BranchInst &BI);
148 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
149 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
151 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
152 const std::vector<ValueRecord> &Args);
153 void visitCallInst(CallInst &I);
154 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
156 // Arithmetic operators
157 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
158 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
159 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
160 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
161 unsigned DestReg, const Type *DestTy,
162 unsigned Op0Reg, unsigned Op1Reg);
163 void doMultiplyConst(MachineBasicBlock *MBB,
164 MachineBasicBlock::iterator &MBBI,
165 unsigned DestReg, const Type *DestTy,
166 unsigned Op0Reg, unsigned Op1Val);
167 void visitMul(BinaryOperator &B);
169 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
170 void visitRem(BinaryOperator &B) { visitDivRem(B); }
171 void visitDivRem(BinaryOperator &B);
174 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
175 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
176 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
178 // Comparison operators...
179 void visitSetCondInst(SetCondInst &I);
180 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
181 MachineBasicBlock *MBB,
182 MachineBasicBlock::iterator &MBBI);
184 // Memory Instructions
185 void visitLoadInst(LoadInst &I);
186 void visitStoreInst(StoreInst &I);
187 void visitGetElementPtrInst(GetElementPtrInst &I);
188 void visitAllocaInst(AllocaInst &I);
189 void visitMallocInst(MallocInst &I);
190 void visitFreeInst(FreeInst &I);
193 void visitShiftInst(ShiftInst &I);
194 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
195 void visitCastInst(CastInst &I);
196 void visitVANextInst(VANextInst &I);
197 void visitVAArgInst(VAArgInst &I);
199 void visitInstruction(Instruction &I) {
200 std::cerr << "Cannot instruction select: " << I;
204 /// promote32 - Make a value 32-bits wide, and put it somewhere.
206 void promote32(unsigned targetReg, const ValueRecord &VR);
208 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
209 /// constant expression GEP support.
211 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
212 Value *Src, User::op_iterator IdxBegin,
213 User::op_iterator IdxEnd, unsigned TargetReg);
215 /// emitCastOperation - Common code shared between visitCastInst and
216 /// constant expression cast support.
217 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
218 Value *Src, const Type *DestTy, unsigned TargetReg);
220 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
221 /// and constant expression support.
222 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
223 MachineBasicBlock::iterator &IP,
224 Value *Op0, Value *Op1,
225 unsigned OperatorClass, unsigned TargetReg);
227 void emitDivRemOperation(MachineBasicBlock *BB,
228 MachineBasicBlock::iterator &IP,
229 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
230 const Type *Ty, unsigned TargetReg);
232 /// emitSetCCOperation - Common code shared between visitSetCondInst and
233 /// constant expression support.
234 void emitSetCCOperation(MachineBasicBlock *BB,
235 MachineBasicBlock::iterator &IP,
236 Value *Op0, Value *Op1, unsigned Opcode,
239 /// emitShiftOperation - Common code shared between visitShiftInst and
240 /// constant expression support.
241 void emitShiftOperation(MachineBasicBlock *MBB,
242 MachineBasicBlock::iterator &IP,
243 Value *Op, Value *ShiftAmount, bool isLeftShift,
244 const Type *ResultTy, unsigned DestReg);
247 /// copyConstantToRegister - Output the instructions required to put the
248 /// specified constant into the specified register.
250 void copyConstantToRegister(MachineBasicBlock *MBB,
251 MachineBasicBlock::iterator &MBBI,
252 Constant *C, unsigned Reg);
254 /// makeAnotherReg - This method returns the next register number we haven't
257 /// Long values are handled somewhat specially. They are always allocated
258 /// as pairs of 32 bit integer values. The register number returned is the
259 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
260 /// of the long value.
262 unsigned makeAnotherReg(const Type *Ty) {
263 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
264 "Current target doesn't have X86 reg info??");
265 const X86RegisterInfo *MRI =
266 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
267 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
268 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
269 // Create the lower part
270 F->getSSARegMap()->createVirtualRegister(RC);
271 // Create the upper part.
272 return F->getSSARegMap()->createVirtualRegister(RC)-1;
275 // Add the mapping of regnumber => reg class to MachineFunction
276 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
277 return F->getSSARegMap()->createVirtualRegister(RC);
280 /// getReg - This method turns an LLVM value into a register number. This
281 /// is guaranteed to produce the same register number for a particular value
282 /// every time it is queried.
284 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
285 unsigned getReg(Value *V) {
286 // Just append to the end of the current bb.
287 MachineBasicBlock::iterator It = BB->end();
288 return getReg(V, BB, It);
290 unsigned getReg(Value *V, MachineBasicBlock *MBB,
291 MachineBasicBlock::iterator &IPt) {
292 unsigned &Reg = RegMap[V];
294 Reg = makeAnotherReg(V->getType());
298 // If this operand is a constant, emit the code to copy the constant into
299 // the register here...
301 if (Constant *C = dyn_cast<Constant>(V)) {
302 copyConstantToRegister(MBB, IPt, C, Reg);
303 RegMap.erase(V); // Assign a new name to this constant if ref'd again
304 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
305 // Move the address of the global into the register
306 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
307 RegMap.erase(V); // Assign a new name to this address if ref'd again
315 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
319 cByte, cShort, cInt, cFP, cLong
322 /// getClass - Turn a primitive type into a "class" number which is based on the
323 /// size of the type, and whether or not it is floating point.
325 static inline TypeClass getClass(const Type *Ty) {
326 switch (Ty->getPrimitiveID()) {
327 case Type::SByteTyID:
328 case Type::UByteTyID: return cByte; // Byte operands are class #0
329 case Type::ShortTyID:
330 case Type::UShortTyID: return cShort; // Short operands are class #1
333 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
335 case Type::FloatTyID:
336 case Type::DoubleTyID: return cFP; // Floating Point is #3
339 case Type::ULongTyID: return cLong; // Longs are class #4
341 assert(0 && "Invalid type to getClass!");
342 return cByte; // not reached
346 // getClassB - Just like getClass, but treat boolean values as bytes.
347 static inline TypeClass getClassB(const Type *Ty) {
348 if (Ty == Type::BoolTy) return cByte;
353 /// copyConstantToRegister - Output the instructions required to put the
354 /// specified constant into the specified register.
356 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
357 MachineBasicBlock::iterator &IP,
358 Constant *C, unsigned R) {
359 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
361 switch (CE->getOpcode()) {
362 case Instruction::GetElementPtr:
363 emitGEPOperation(MBB, IP, CE->getOperand(0),
364 CE->op_begin()+1, CE->op_end(), R);
366 case Instruction::Cast:
367 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
370 case Instruction::Xor: ++Class; // FALL THROUGH
371 case Instruction::Or: ++Class; // FALL THROUGH
372 case Instruction::And: ++Class; // FALL THROUGH
373 case Instruction::Sub: ++Class; // FALL THROUGH
374 case Instruction::Add:
375 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
379 case Instruction::Mul: {
380 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
381 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
382 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
385 case Instruction::Div:
386 case Instruction::Rem: {
387 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
388 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
389 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
390 CE->getOpcode() == Instruction::Div,
395 case Instruction::SetNE:
396 case Instruction::SetEQ:
397 case Instruction::SetLT:
398 case Instruction::SetGT:
399 case Instruction::SetLE:
400 case Instruction::SetGE:
401 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
405 case Instruction::Shl:
406 case Instruction::Shr:
407 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
408 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
412 std::cerr << "Offending expr: " << C << "\n";
413 assert(0 && "Constant expression not yet handled!\n");
417 if (C->getType()->isIntegral()) {
418 unsigned Class = getClassB(C->getType());
420 if (Class == cLong) {
421 // Copy the value into the register pair.
422 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
423 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
424 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
428 assert(Class <= cInt && "Type not handled yet!");
430 static const unsigned IntegralOpcodeTab[] = {
431 X86::MOVir8, X86::MOVir16, X86::MOVir32
434 if (C->getType() == Type::BoolTy) {
435 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
437 ConstantInt *CI = cast<ConstantInt>(C);
438 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
440 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
441 double Value = CFP->getValue();
443 BMI(MBB, IP, X86::FLD0, 0, R);
444 else if (Value == +1.0)
445 BMI(MBB, IP, X86::FLD1, 0, R);
447 // Otherwise we need to spill the constant to memory...
448 MachineConstantPool *CP = F->getConstantPool();
449 unsigned CPI = CP->getConstantPoolIndex(CFP);
450 const Type *Ty = CFP->getType();
452 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
453 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
454 addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
457 } else if (isa<ConstantPointerNull>(C)) {
458 // Copy zero (null pointer) to the register.
459 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
460 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
461 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
462 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
464 std::cerr << "Offending constant: " << C << "\n";
465 assert(0 && "Type not handled yet!");
469 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
470 /// the stack into virtual registers.
472 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
473 // Emit instructions to load the arguments... On entry to a function on the
474 // X86, the stack frame looks like this:
476 // [ESP] -- return address
477 // [ESP + 4] -- first argument (leftmost lexically)
478 // [ESP + 8] -- second argument, if first argument is four bytes in size
481 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
482 MachineFrameInfo *MFI = F->getFrameInfo();
484 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
485 unsigned Reg = getReg(*I);
487 int FI; // Frame object index
488 switch (getClassB(I->getType())) {
490 FI = MFI->CreateFixedObject(1, ArgOffset);
491 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
494 FI = MFI->CreateFixedObject(2, ArgOffset);
495 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
498 FI = MFI->CreateFixedObject(4, ArgOffset);
499 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
502 FI = MFI->CreateFixedObject(8, ArgOffset);
503 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
504 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
505 ArgOffset += 4; // longs require 4 additional bytes
509 if (I->getType() == Type::FloatTy) {
510 Opcode = X86::FLDr32;
511 FI = MFI->CreateFixedObject(4, ArgOffset);
513 Opcode = X86::FLDr64;
514 FI = MFI->CreateFixedObject(8, ArgOffset);
515 ArgOffset += 4; // doubles require 4 additional bytes
517 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
520 assert(0 && "Unhandled argument type!");
522 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
525 // If the function takes variable number of arguments, add a frame offset for
526 // the start of the first vararg value... this is used to expand
528 if (Fn.getFunctionType()->isVarArg())
529 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
533 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
534 /// because we have to generate our sources into the source basic blocks, not
537 void ISel::SelectPHINodes() {
538 const TargetInstrInfo &TII = TM.getInstrInfo();
539 const Function &LF = *F->getFunction(); // The LLVM function...
540 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
541 const BasicBlock *BB = I;
542 MachineBasicBlock *MBB = MBBMap[I];
544 // Loop over all of the PHI nodes in the LLVM basic block...
545 unsigned NumPHIs = 0;
546 for (BasicBlock::const_iterator I = BB->begin();
547 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
549 // Create a new machine instr PHI node, and insert it.
550 unsigned PHIReg = getReg(*PN);
551 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
552 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
554 MachineInstr *LongPhiMI = 0;
555 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
556 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
557 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
560 // PHIValues - Map of blocks to incoming virtual registers. We use this
561 // so that we only initialize one incoming value for a particular block,
562 // even if the block has multiple entries in the PHI node.
564 std::map<MachineBasicBlock*, unsigned> PHIValues;
566 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
567 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
569 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
570 PHIValues.lower_bound(PredMBB);
572 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
573 // We already inserted an initialization of the register for this
574 // predecessor. Recycle it.
575 ValReg = EntryIt->second;
578 // Get the incoming value into a virtual register.
580 Value *Val = PN->getIncomingValue(i);
582 // If this is a constant or GlobalValue, we may have to insert code
583 // into the basic block to compute it into a virtual register.
584 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
585 // Because we don't want to clobber any values which might be in
586 // physical registers with the computation of this constant (which
587 // might be arbitrarily complex if it is a constant expression),
588 // just insert the computation at the top of the basic block.
589 MachineBasicBlock::iterator PI = PredMBB->begin();
591 // Skip over any PHI nodes though!
592 while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
595 ValReg = getReg(Val, PredMBB, PI);
597 ValReg = getReg(Val);
600 // Remember that we inserted a value for this PHI for this predecessor
601 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
604 PhiMI->addRegOperand(ValReg);
605 PhiMI->addMachineBasicBlockOperand(PredMBB);
607 LongPhiMI->addRegOperand(ValReg+1);
608 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
615 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
616 // the conditional branch instruction which is the only user of the cc
617 // instruction. This is the case if the conditional branch is the only user of
618 // the setcc, and if the setcc is in the same basic block as the conditional
619 // branch. We also don't handle long arguments below, so we reject them here as
622 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
623 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
624 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
625 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
626 const Type *Ty = SCI->getOperand(0)->getType();
627 if (Ty != Type::LongTy && Ty != Type::ULongTy)
633 // Return a fixed numbering for setcc instructions which does not depend on the
634 // order of the opcodes.
636 static unsigned getSetCCNumber(unsigned Opcode) {
638 default: assert(0 && "Unknown setcc instruction!");
639 case Instruction::SetEQ: return 0;
640 case Instruction::SetNE: return 1;
641 case Instruction::SetLT: return 2;
642 case Instruction::SetGE: return 3;
643 case Instruction::SetGT: return 4;
644 case Instruction::SetLE: return 5;
648 // LLVM -> X86 signed X86 unsigned
649 // ----- ---------- ------------
650 // seteq -> sete sete
651 // setne -> setne setne
652 // setlt -> setl setb
653 // setge -> setge setae
654 // setgt -> setg seta
655 // setle -> setle setbe
657 // sets // Used by comparison with 0 optimization
659 static const unsigned SetCCOpcodeTab[2][8] = {
660 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
662 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
663 X86::SETSr, X86::SETNSr },
666 // EmitComparison - This function emits a comparison of the two operands,
667 // returning the extended setcc code to use.
668 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
669 MachineBasicBlock *MBB,
670 MachineBasicBlock::iterator &IP) {
671 // The arguments are already supposed to be of the same type.
672 const Type *CompTy = Op0->getType();
673 unsigned Class = getClassB(CompTy);
674 unsigned Op0r = getReg(Op0, MBB, IP);
676 // Special case handling of: cmp R, i
677 if (Class == cByte || Class == cShort || Class == cInt)
678 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
679 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
681 // Mask off any upper bits of the constant, if there are any...
682 Op1v &= (1ULL << (8 << Class)) - 1;
684 // If this is a comparison against zero, emit more efficient code. We
685 // can't handle unsigned comparisons against zero unless they are == or
686 // !=. These should have been strength reduced already anyway.
687 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
688 static const unsigned TESTTab[] = {
689 X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
691 BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
693 if (OpNum == 2) return 6; // Map jl -> js
694 if (OpNum == 3) return 7; // Map jg -> jns
698 static const unsigned CMPTab[] = {
699 X86::CMPri8, X86::CMPri16, X86::CMPri32
702 BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
706 unsigned Op1r = getReg(Op1, MBB, IP);
708 default: assert(0 && "Unknown type class!");
709 // Emit: cmp <var1>, <var2> (do the comparison). We can
710 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
713 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
716 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
719 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
722 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
723 BMI(MBB, IP, X86::FNSTSWr8, 0);
724 BMI(MBB, IP, X86::SAHF, 1);
728 if (OpNum < 2) { // seteq, setne
729 unsigned LoTmp = makeAnotherReg(Type::IntTy);
730 unsigned HiTmp = makeAnotherReg(Type::IntTy);
731 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
732 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
733 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
734 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
735 break; // Allow the sete or setne to be generated from flags set by OR
737 // Emit a sequence of code which compares the high and low parts once
738 // each, then uses a conditional move to handle the overflow case. For
739 // example, a setlt for long would generate code like this:
741 // AL = lo(op1) < lo(op2) // Signedness depends on operands
742 // BL = hi(op1) < hi(op2) // Always unsigned comparison
743 // dest = hi(op1) == hi(op2) ? AL : BL;
746 // FIXME: This would be much better if we had hierarchical register
747 // classes! Until then, hardcode registers so that we can deal with their
748 // aliases (because we don't have conditional byte moves).
750 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
751 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
752 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
753 BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
754 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
755 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
756 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
757 // NOTE: visitSetCondInst knows that the value is dumped into the BL
758 // register at this point for long values...
766 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
767 /// register, then move it to wherever the result should be.
769 void ISel::visitSetCondInst(SetCondInst &I) {
770 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
772 unsigned DestReg = getReg(I);
773 MachineBasicBlock::iterator MII = BB->end();
774 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
778 /// emitSetCCOperation - Common code shared between visitSetCondInst and
779 /// constant expression support.
780 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
781 MachineBasicBlock::iterator &IP,
782 Value *Op0, Value *Op1, unsigned Opcode,
783 unsigned TargetReg) {
784 unsigned OpNum = getSetCCNumber(Opcode);
785 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
787 const Type *CompTy = Op0->getType();
788 unsigned CompClass = getClassB(CompTy);
789 bool isSigned = CompTy->isSigned() && CompClass != cFP;
791 if (CompClass != cLong || OpNum < 2) {
792 // Handle normal comparisons with a setcc instruction...
793 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
795 // Handle long comparisons by copying the value which is already in BL into
796 // the register we want...
797 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
804 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
805 /// operand, in the specified target register.
806 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
807 bool isUnsigned = VR.Ty->isUnsigned();
809 // Make sure we have the register number for this value...
810 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
812 switch (getClassB(VR.Ty)) {
814 // Extend value into target register (8->32)
816 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
818 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
821 // Extend value into target register (16->32)
823 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
825 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
828 // Move value into target register (32->32)
829 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
832 assert(0 && "Unpromotable operand class in promote32");
836 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
837 /// we have the following possibilities:
839 /// ret void: No return value, simply emit a 'ret' instruction
840 /// ret sbyte, ubyte : Extend value into EAX and return
841 /// ret short, ushort: Extend value into EAX and return
842 /// ret int, uint : Move value into EAX and return
843 /// ret pointer : Move value into EAX and return
844 /// ret long, ulong : Move value into EAX/EDX and return
845 /// ret float/double : Top of FP stack
847 void ISel::visitReturnInst(ReturnInst &I) {
848 if (I.getNumOperands() == 0) {
849 BuildMI(BB, X86::FP_REG_KILL, 0);
850 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
854 Value *RetVal = I.getOperand(0);
855 unsigned RetReg = getReg(RetVal);
856 switch (getClassB(RetVal->getType())) {
857 case cByte: // integral return values: extend or move into EAX and return
860 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
861 // Declare that EAX is live on exit
862 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
864 case cFP: // Floats & Doubles: Return in ST(0)
865 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
866 // Declare that top-of-stack is live on exit
867 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
870 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
871 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
872 // Declare that EAX & EDX are live on exit
873 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
879 // Emit a 'ret' instruction
880 BuildMI(BB, X86::FP_REG_KILL, 0);
881 BuildMI(BB, X86::RET, 0);
884 // getBlockAfter - Return the basic block which occurs lexically after the
886 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
887 Function::iterator I = BB; ++I; // Get iterator to next block
888 return I != BB->getParent()->end() ? &*I : 0;
891 /// visitBranchInst - Handle conditional and unconditional branches here. Note
892 /// that since code layout is frozen at this point, that if we are trying to
893 /// jump to a block that is the immediate successor of the current block, we can
894 /// just make a fall-through (but we don't currently).
896 void ISel::visitBranchInst(BranchInst &BI) {
897 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
899 if (!BI.isConditional()) { // Unconditional branch?
900 if (BI.getSuccessor(0) != NextBB) {
901 BuildMI(BB, X86::FP_REG_KILL, 0);
902 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
907 // See if we can fold the setcc into the branch itself...
908 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
910 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
911 // computed some other way...
912 unsigned condReg = getReg(BI.getCondition());
913 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
914 BuildMI(BB, X86::FP_REG_KILL, 0);
915 if (BI.getSuccessor(1) == NextBB) {
916 if (BI.getSuccessor(0) != NextBB)
917 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
919 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
921 if (BI.getSuccessor(0) != NextBB)
922 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
927 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
928 MachineBasicBlock::iterator MII = BB->end();
929 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
931 const Type *CompTy = SCI->getOperand(0)->getType();
932 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
935 // LLVM -> X86 signed X86 unsigned
936 // ----- ---------- ------------
944 // js // Used by comparison with 0 optimization
947 static const unsigned OpcodeTab[2][8] = {
948 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
949 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
953 BuildMI(BB, X86::FP_REG_KILL, 0);
954 if (BI.getSuccessor(0) != NextBB) {
955 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
956 if (BI.getSuccessor(1) != NextBB)
957 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
959 // Change to the inverse condition...
960 if (BI.getSuccessor(1) != NextBB) {
962 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
968 /// doCall - This emits an abstract call instruction, setting up the arguments
969 /// and the return value as appropriate. For the actual function call itself,
970 /// it inserts the specified CallMI instruction into the stream.
972 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
973 const std::vector<ValueRecord> &Args) {
975 // Count how many bytes are to be pushed on the stack...
976 unsigned NumBytes = 0;
979 for (unsigned i = 0, e = Args.size(); i != e; ++i)
980 switch (getClassB(Args[i].Ty)) {
981 case cByte: case cShort: case cInt:
982 NumBytes += 4; break;
984 NumBytes += 8; break;
986 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
988 default: assert(0 && "Unknown class!");
991 // Adjust the stack pointer for the new arguments...
992 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
994 // Arguments go on the stack in reverse order, as specified by the ABI.
995 unsigned ArgOffset = 0;
996 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
997 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
998 switch (getClassB(Args[i].Ty)) {
1001 // Promote arg to 32 bits wide into a temporary register...
1002 unsigned R = makeAnotherReg(Type::UIntTy);
1003 promote32(R, Args[i]);
1004 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1005 X86::ESP, ArgOffset).addReg(R);
1009 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1010 X86::ESP, ArgOffset).addReg(ArgReg);
1013 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1014 X86::ESP, ArgOffset).addReg(ArgReg);
1015 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1016 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1017 ArgOffset += 4; // 8 byte entry, not 4.
1021 if (Args[i].Ty == Type::FloatTy) {
1022 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
1023 X86::ESP, ArgOffset).addReg(ArgReg);
1025 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1026 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
1027 X86::ESP, ArgOffset).addReg(ArgReg);
1028 ArgOffset += 4; // 8 byte entry, not 4.
1032 default: assert(0 && "Unknown class!");
1037 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
1040 BB->push_back(CallMI);
1042 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
1044 // If there is a return value, scavenge the result from the location the call
1047 if (Ret.Ty != Type::VoidTy) {
1048 unsigned DestClass = getClassB(Ret.Ty);
1049 switch (DestClass) {
1053 // Integral results are in %eax, or the appropriate portion
1055 static const unsigned regRegMove[] = {
1056 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1058 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1059 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1062 case cFP: // Floating-point return values live in %ST(0)
1063 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1065 case cLong: // Long values are left in EDX:EAX
1066 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
1067 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
1069 default: assert(0 && "Unknown class!");
1075 /// visitCallInst - Push args on stack and do a procedure call instruction.
1076 void ISel::visitCallInst(CallInst &CI) {
1077 MachineInstr *TheCall;
1078 if (Function *F = CI.getCalledFunction()) {
1079 // Is it an intrinsic function call?
1080 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1081 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1085 // Emit a CALL instruction with PC-relative displacement.
1086 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1087 } else { // Emit an indirect call...
1088 unsigned Reg = getReg(CI.getCalledValue());
1089 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1092 std::vector<ValueRecord> Args;
1093 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1094 Args.push_back(ValueRecord(CI.getOperand(i)));
1096 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1097 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1101 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1102 /// function, lowering any calls to unknown intrinsic functions into the
1103 /// equivalent LLVM code.
1104 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1105 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1106 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1107 if (CallInst *CI = dyn_cast<CallInst>(I++))
1108 if (Function *F = CI->getCalledFunction())
1109 switch (F->getIntrinsicID()) {
1110 case Intrinsic::not_intrinsic:
1111 case Intrinsic::va_start:
1112 case Intrinsic::va_copy:
1113 case Intrinsic::va_end:
1114 // We directly implement these intrinsics
1117 // All other intrinsic calls we must lower.
1118 Instruction *Before = CI->getPrev();
1119 IL.LowerIntrinsicCall(CI);
1120 if (Before) { // Move iterator to instruction after call
1129 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1130 unsigned TmpReg1, TmpReg2;
1132 case Intrinsic::va_start:
1133 // Get the address of the first vararg value...
1134 TmpReg1 = getReg(CI);
1135 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1138 case Intrinsic::va_copy:
1139 TmpReg1 = getReg(CI);
1140 TmpReg2 = getReg(CI.getOperand(1));
1141 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1143 case Intrinsic::va_end: return; // Noop on X86
1145 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1150 /// visitSimpleBinary - Implement simple binary operators for integral types...
1151 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1153 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1154 unsigned DestReg = getReg(B);
1155 MachineBasicBlock::iterator MI = BB->end();
1156 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1157 OperatorClass, DestReg);
1160 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1161 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1164 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1165 /// and constant expression support.
1167 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1168 MachineBasicBlock::iterator &IP,
1169 Value *Op0, Value *Op1,
1170 unsigned OperatorClass, unsigned DestReg) {
1171 unsigned Class = getClassB(Op0->getType());
1173 // sub 0, X -> neg X
1174 if (OperatorClass == 1 && Class != cLong)
1175 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
1176 if (CI->isNullValue()) {
1177 unsigned op1Reg = getReg(Op1, MBB, IP);
1179 default: assert(0 && "Unknown class for this function!");
1181 BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
1184 BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
1187 BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
1192 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1193 static const unsigned OpcodeTab[][4] = {
1194 // Arithmetic operators
1195 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1196 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1198 // Bitwise operators
1199 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1200 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1201 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1204 bool isLong = false;
1205 if (Class == cLong) {
1207 Class = cInt; // Bottom 32 bits are handled just like ints
1210 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1211 assert(Opcode && "Floating point arguments to logical inst?");
1212 unsigned Op0r = getReg(Op0, MBB, IP);
1213 unsigned Op1r = getReg(Op1, MBB, IP);
1214 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1216 if (isLong) { // Handle the upper 32 bits of long values...
1217 static const unsigned TopTab[] = {
1218 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1220 BMI(MBB, IP, TopTab[OperatorClass], 2,
1221 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1226 // Special case: op Reg, <const>
1227 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1228 unsigned Op0r = getReg(Op0, MBB, IP);
1230 // xor X, -1 -> not X
1231 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1232 static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
1233 BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1237 // add X, -1 -> dec X
1238 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1239 static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
1240 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1244 // add X, 1 -> inc X
1245 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1246 static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
1247 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1251 static const unsigned OpcodeTab[][3] = {
1252 // Arithmetic operators
1253 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1254 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1256 // Bitwise operators
1257 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1258 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1259 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1262 assert(Class < 3 && "General code handles 64-bit integer types!");
1263 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1264 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1266 // Mask off any upper bits of the constant, if there are any...
1267 Op1v &= (1ULL << (8 << Class)) - 1;
1268 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
1271 /// doMultiply - Emit appropriate instructions to multiply together the
1272 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1273 /// result should be given as DestTy.
1275 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1276 unsigned DestReg, const Type *DestTy,
1277 unsigned op0Reg, unsigned op1Reg) {
1278 unsigned Class = getClass(DestTy);
1280 case cFP: // Floating point multiply
1281 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1285 BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
1286 .addReg(op0Reg).addReg(op1Reg);
1289 // Must use the MUL instruction, which forces use of AL...
1290 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1291 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1292 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1295 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1299 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1300 // returns zero when the input is not exactly a power of two.
1301 static unsigned ExactLog2(unsigned Val) {
1302 if (Val == 0) return 0;
1305 if (Val & 1) return 0;
1312 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1313 MachineBasicBlock::iterator &IP,
1314 unsigned DestReg, const Type *DestTy,
1315 unsigned op0Reg, unsigned ConstRHS) {
1316 unsigned Class = getClass(DestTy);
1318 // If the element size is exactly a power of 2, use a shift to get it.
1319 if (unsigned Shift = ExactLog2(ConstRHS)) {
1321 default: assert(0 && "Unknown class for this function!");
1323 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1326 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1329 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1334 if (Class == cShort) {
1335 BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1337 } else if (Class == cInt) {
1338 BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1342 // Most general case, emit a normal multiply...
1343 static const unsigned MOVirTab[] = {
1344 X86::MOVir8, X86::MOVir16, X86::MOVir32
1347 unsigned TmpReg = makeAnotherReg(DestTy);
1348 BMI(MBB, IP, MOVirTab[Class], 1, TmpReg).addZImm(ConstRHS);
1350 // Emit a MUL to multiply the register holding the index by
1351 // elementSize, putting the result in OffsetReg.
1352 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1355 /// visitMul - Multiplies are not simple binary operators because they must deal
1356 /// with the EAX register explicitly.
1358 void ISel::visitMul(BinaryOperator &I) {
1359 unsigned Op0Reg = getReg(I.getOperand(0));
1360 unsigned DestReg = getReg(I);
1362 // Simple scalar multiply?
1363 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1364 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1365 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1366 MachineBasicBlock::iterator MBBI = BB->end();
1367 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1369 unsigned Op1Reg = getReg(I.getOperand(1));
1370 MachineBasicBlock::iterator MBBI = BB->end();
1371 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1374 unsigned Op1Reg = getReg(I.getOperand(1));
1376 // Long value. We have to do things the hard way...
1377 // Multiply the two low parts... capturing carry into EDX
1378 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1379 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1381 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1382 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1383 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1385 MachineBasicBlock::iterator MBBI = BB->end();
1386 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1387 BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1389 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1390 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1391 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1394 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1395 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1397 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1398 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1403 /// visitDivRem - Handle division and remainder instructions... these
1404 /// instruction both require the same instructions to be generated, they just
1405 /// select the result from a different register. Note that both of these
1406 /// instructions work differently for signed and unsigned operands.
1408 void ISel::visitDivRem(BinaryOperator &I) {
1409 unsigned Op0Reg = getReg(I.getOperand(0));
1410 unsigned Op1Reg = getReg(I.getOperand(1));
1411 unsigned ResultReg = getReg(I);
1413 MachineBasicBlock::iterator IP = BB->end();
1414 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1415 I.getType(), ResultReg);
1418 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1419 MachineBasicBlock::iterator &IP,
1420 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1421 const Type *Ty, unsigned ResultReg) {
1422 unsigned Class = getClass(Ty);
1424 case cFP: // Floating point divide
1426 BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1427 } else { // Floating point remainder...
1428 MachineInstr *TheCall =
1429 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1430 std::vector<ValueRecord> Args;
1431 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1432 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1433 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1437 static const char *FnName[] =
1438 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1440 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1441 MachineInstr *TheCall =
1442 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1444 std::vector<ValueRecord> Args;
1445 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1446 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1447 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1450 case cByte: case cShort: case cInt:
1451 break; // Small integrals, handled below...
1452 default: assert(0 && "Unknown class!");
1455 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1456 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1457 static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
1458 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
1459 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1461 static const unsigned DivOpcode[][4] = {
1462 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1463 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1466 bool isSigned = Ty->isSigned();
1467 unsigned Reg = Regs[Class];
1468 unsigned ExtReg = ExtRegs[Class];
1470 // Put the first operand into one of the A registers...
1471 BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1474 // Emit a sign extension instruction...
1475 unsigned ShiftResult = makeAnotherReg(Ty);
1476 BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1477 BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1479 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
1480 BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
1483 // Emit the appropriate divide or remainder instruction...
1484 BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1486 // Figure out which register we want to pick the result out of...
1487 unsigned DestReg = isDiv ? Reg : ExtReg;
1489 // Put the result into the destination register...
1490 BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1494 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1495 /// for constant immediate shift values, and for constant immediate
1496 /// shift values equal to 1. Even the general case is sort of special,
1497 /// because the shift amount has to be in CL, not just any old register.
1499 void ISel::visitShiftInst(ShiftInst &I) {
1500 MachineBasicBlock::iterator IP = BB->end ();
1501 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
1502 I.getOpcode () == Instruction::Shl, I.getType (),
1506 /// emitShiftOperation - Common code shared between visitShiftInst and
1507 /// constant expression support.
1508 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
1509 MachineBasicBlock::iterator &IP,
1510 Value *Op, Value *ShiftAmount, bool isLeftShift,
1511 const Type *ResultTy, unsigned DestReg) {
1512 unsigned SrcReg = getReg (Op, MBB, IP);
1513 bool isSigned = ResultTy->isSigned ();
1514 unsigned Class = getClass (ResultTy);
1516 static const unsigned ConstantOperand[][4] = {
1517 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1518 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1519 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1520 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1523 static const unsigned NonConstantOperand[][4] = {
1524 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1525 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1526 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1527 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1530 // Longs, as usual, are handled specially...
1531 if (Class == cLong) {
1532 // If we have a constant shift, we can generate much more efficient code
1533 // than otherwise...
1535 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1536 unsigned Amount = CUI->getValue();
1538 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1540 BMI(MBB, IP, Opc[3], 3,
1541 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1542 BMI(MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1544 BMI(MBB, IP, Opc[3], 3,
1545 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1546 BMI(MBB, IP, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1548 } else { // Shifting more than 32 bits
1551 BMI(MBB, IP, X86::SHLir32, 2,
1552 DestReg + 1).addReg(SrcReg).addZImm(Amount);
1553 BMI(MBB, IP, X86::MOVir32, 1,
1554 DestReg).addZImm(0);
1556 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1557 BMI(MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1558 BMI(MBB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1562 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1564 if (!isLeftShift && isSigned) {
1565 // If this is a SHR of a Long, then we need to do funny sign extension
1566 // stuff. TmpReg gets the value to use as the high-part if we are
1567 // shifting more than 32 bits.
1568 BMI(MBB, IP, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1570 // Other shifts use a fixed zero value if the shift is more than 32
1572 BMI(MBB, IP, X86::MOVir32, 1, TmpReg).addZImm(0);
1575 // Initialize CL with the shift amount...
1576 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
1577 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1579 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1580 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1582 // TmpReg2 = shld inHi, inLo
1583 BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1584 // TmpReg3 = shl inLo, CL
1585 BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1587 // Set the flags to indicate whether the shift was by more than 32 bits.
1588 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1590 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1591 BMI(MBB, IP, X86::CMOVNErr32, 2,
1592 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1593 // DestLo = (>32) ? TmpReg : TmpReg3;
1594 BMI(MBB, IP, X86::CMOVNErr32, 2,
1595 DestReg).addReg(TmpReg3).addReg(TmpReg);
1597 // TmpReg2 = shrd inLo, inHi
1598 BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1599 // TmpReg3 = s[ah]r inHi, CL
1600 BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1603 // Set the flags to indicate whether the shift was by more than 32 bits.
1604 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1606 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1607 BMI(MBB, IP, X86::CMOVNErr32, 2,
1608 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1610 // DestHi = (>32) ? TmpReg : TmpReg3;
1611 BMI(MBB, IP, X86::CMOVNErr32, 2,
1612 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1618 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1619 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1620 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1622 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1623 BMI(MBB, IP, Opc[Class], 2,
1624 DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1625 } else { // The shift amount is non-constant.
1626 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
1627 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1629 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1630 BMI(MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
1635 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1636 /// instruction. The load and store instructions are the only place where we
1637 /// need to worry about the memory layout of the target machine.
1639 void ISel::visitLoadInst(LoadInst &I) {
1640 unsigned SrcAddrReg = getReg(I.getOperand(0));
1641 unsigned DestReg = getReg(I);
1643 unsigned Class = getClassB(I.getType());
1645 if (Class == cLong) {
1646 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), SrcAddrReg);
1647 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1651 static const unsigned Opcodes[] = {
1652 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr32
1654 unsigned Opcode = Opcodes[Class];
1655 if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
1656 addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg);
1659 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1662 void ISel::visitStoreInst(StoreInst &I) {
1663 unsigned ValReg = getReg(I.getOperand(0));
1664 unsigned AddressReg = getReg(I.getOperand(1));
1666 const Type *ValTy = I.getOperand(0)->getType();
1667 unsigned Class = getClassB(ValTy);
1669 if (Class == cLong) {
1670 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1671 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
1675 static const unsigned Opcodes[] = {
1676 X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTr32
1678 unsigned Opcode = Opcodes[Class];
1679 if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
1680 addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
1684 /// visitCastInst - Here we have various kinds of copying with or without
1685 /// sign extension going on.
1686 void ISel::visitCastInst(CastInst &CI) {
1687 Value *Op = CI.getOperand(0);
1688 // If this is a cast from a 32-bit integer to a Long type, and the only uses
1689 // of the case are GEP instructions, then the cast does not need to be
1690 // generated explicitly, it will be folded into the GEP.
1691 if (CI.getType() == Type::LongTy &&
1692 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
1693 bool AllUsesAreGEPs = true;
1694 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
1695 if (!isa<GetElementPtrInst>(*I)) {
1696 AllUsesAreGEPs = false;
1700 // No need to codegen this cast if all users are getelementptr instrs...
1701 if (AllUsesAreGEPs) return;
1704 unsigned DestReg = getReg(CI);
1705 MachineBasicBlock::iterator MI = BB->end();
1706 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
1709 /// emitCastOperation - Common code shared between visitCastInst and
1710 /// constant expression cast support.
1711 void ISel::emitCastOperation(MachineBasicBlock *BB,
1712 MachineBasicBlock::iterator &IP,
1713 Value *Src, const Type *DestTy,
1715 unsigned SrcReg = getReg(Src, BB, IP);
1716 const Type *SrcTy = Src->getType();
1717 unsigned SrcClass = getClassB(SrcTy);
1718 unsigned DestClass = getClassB(DestTy);
1720 // Implement casts to bool by using compare on the operand followed by set if
1721 // not zero on the result.
1722 if (DestTy == Type::BoolTy) {
1725 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1728 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1731 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1734 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1735 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1739 assert(0 && "FIXME: implement cast FP to bool");
1743 // If the zero flag is not set, then the value is true, set the byte to
1745 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1749 static const unsigned RegRegMove[] = {
1750 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1753 // Implement casts between values of the same type class (as determined by
1754 // getClass) by using a register-to-register move.
1755 if (SrcClass == DestClass) {
1756 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1757 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1758 } else if (SrcClass == cFP) {
1759 if (SrcTy == Type::FloatTy) { // double -> float
1760 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1761 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1762 } else { // float -> double
1763 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1764 "Unknown cFP member!");
1765 // Truncate from double to float by storing to memory as short, then
1767 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1768 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1769 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1770 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1772 } else if (SrcClass == cLong) {
1773 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1774 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1776 assert(0 && "Cannot handle this type of cast instruction!");
1782 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1783 // or zero extension, depending on whether the source type was signed.
1784 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1785 SrcClass < DestClass) {
1786 bool isLong = DestClass == cLong;
1787 if (isLong) DestClass = cInt;
1789 static const unsigned Opc[][4] = {
1790 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1791 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1794 bool isUnsigned = SrcTy->isUnsigned();
1795 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1796 DestReg).addReg(SrcReg);
1798 if (isLong) { // Handle upper 32 bits as appropriate...
1799 if (isUnsigned) // Zero out top bits...
1800 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1801 else // Sign extend bottom half...
1802 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1807 // Special case long -> int ...
1808 if (SrcClass == cLong && DestClass == cInt) {
1809 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1813 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1814 // move out of AX or AL.
1815 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1816 && SrcClass > DestClass) {
1817 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1818 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1819 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1823 // Handle casts from integer to floating point now...
1824 if (DestClass == cFP) {
1825 // Promote the integer to a type supported by FLD. We do this because there
1826 // are no unsigned FLD instructions, so we must promote an unsigned value to
1827 // a larger signed value, then use FLD on the larger value.
1829 const Type *PromoteType = 0;
1830 unsigned PromoteOpcode;
1831 switch (SrcTy->getPrimitiveID()) {
1832 case Type::BoolTyID:
1833 case Type::SByteTyID:
1834 // We don't have the facilities for directly loading byte sized data from
1835 // memory (even signed). Promote it to 16 bits.
1836 PromoteType = Type::ShortTy;
1837 PromoteOpcode = X86::MOVSXr16r8;
1839 case Type::UByteTyID:
1840 PromoteType = Type::ShortTy;
1841 PromoteOpcode = X86::MOVZXr16r8;
1843 case Type::UShortTyID:
1844 PromoteType = Type::IntTy;
1845 PromoteOpcode = X86::MOVZXr32r16;
1847 case Type::UIntTyID: {
1848 // Make a 64 bit temporary... and zero out the top of it...
1849 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1850 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1851 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1852 SrcTy = Type::LongTy;
1857 case Type::ULongTyID:
1858 assert("FIXME: not implemented: cast ulong X to fp type!");
1859 default: // No promotion needed...
1864 unsigned TmpReg = makeAnotherReg(PromoteType);
1865 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1866 1, TmpReg).addReg(SrcReg);
1867 SrcTy = PromoteType;
1868 SrcClass = getClass(PromoteType);
1872 // Spill the integer to memory and reload it from there...
1874 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1876 if (SrcClass == cLong) {
1877 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1878 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1879 FrameIdx, 4).addReg(SrcReg+1);
1881 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1882 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1885 static const unsigned Op2[] =
1886 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1887 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1891 // Handle casts from floating point to integer now...
1892 if (SrcClass == cFP) {
1893 // Change the floating point control register to use "round towards zero"
1894 // mode when truncating to an integer value.
1896 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1897 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1899 // Load the old value of the high byte of the control word...
1900 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1901 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1903 // Set the high part to be round to zero...
1904 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1906 // Reload the modified control word now...
1907 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1909 // Restore the memory image of control word to original value
1910 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1911 CWFrameIdx, 1).addReg(HighPartOfCW);
1913 // We don't have the facilities for directly storing byte sized data to
1914 // memory. Promote it to 16 bits. We also must promote unsigned values to
1915 // larger classes because we only have signed FP stores.
1916 unsigned StoreClass = DestClass;
1917 const Type *StoreTy = DestTy;
1918 if (StoreClass == cByte || DestTy->isUnsigned())
1919 switch (StoreClass) {
1920 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1921 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1922 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1923 // The following treatment of cLong may not be perfectly right,
1924 // but it survives chains of casts of the form
1925 // double->ulong->double.
1926 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
1927 default: assert(0 && "Unknown store class!");
1930 // Spill the integer to memory and reload it from there...
1932 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1934 static const unsigned Op1[] =
1935 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1936 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1938 if (DestClass == cLong) {
1939 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1940 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1942 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1943 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1946 // Reload the original control word now...
1947 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1951 // Anything we haven't handled already, we can't (yet) handle at all.
1952 assert(0 && "Unhandled cast instruction!");
1956 /// visitVANextInst - Implement the va_next instruction...
1958 void ISel::visitVANextInst(VANextInst &I) {
1959 unsigned VAList = getReg(I.getOperand(0));
1960 unsigned DestReg = getReg(I);
1963 switch (I.getArgType()->getPrimitiveID()) {
1966 assert(0 && "Error: bad type for va_next instruction!");
1968 case Type::PointerTyID:
1969 case Type::UIntTyID:
1973 case Type::ULongTyID:
1974 case Type::LongTyID:
1975 case Type::DoubleTyID:
1980 // Increment the VAList pointer...
1981 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
1984 void ISel::visitVAArgInst(VAArgInst &I) {
1985 unsigned VAList = getReg(I.getOperand(0));
1986 unsigned DestReg = getReg(I);
1988 switch (I.getType()->getPrimitiveID()) {
1991 assert(0 && "Error: bad type for va_next instruction!");
1993 case Type::PointerTyID:
1994 case Type::UIntTyID:
1996 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1998 case Type::ULongTyID:
1999 case Type::LongTyID:
2000 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
2001 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
2003 case Type::DoubleTyID:
2004 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
2010 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2011 unsigned outputReg = getReg(I);
2012 MachineBasicBlock::iterator MI = BB->end();
2013 emitGEPOperation(BB, MI, I.getOperand(0),
2014 I.op_begin()+1, I.op_end(), outputReg);
2017 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2018 MachineBasicBlock::iterator &IP,
2019 Value *Src, User::op_iterator IdxBegin,
2020 User::op_iterator IdxEnd, unsigned TargetReg) {
2021 const TargetData &TD = TM.getTargetData();
2022 const Type *Ty = Src->getType();
2023 unsigned BaseReg = getReg(Src, MBB, IP);
2025 // GEPs have zero or more indices; we must perform a struct access
2026 // or array access for each one.
2027 for (GetElementPtrInst::op_iterator oi = IdxBegin,
2028 oe = IdxEnd; oi != oe; ++oi) {
2030 unsigned NextReg = BaseReg;
2031 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2032 // It's a struct access. idx is the index into the structure,
2033 // which names the field. This index must have ubyte type.
2034 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
2035 assert(CUI->getType() == Type::UByteTy
2036 && "Funny-looking structure index in GEP");
2037 // Use the TargetData structure to pick out what the layout of
2038 // the structure is in memory. Since the structure index must
2039 // be constant, we can get its value and use it to find the
2040 // right byte offset from the StructLayout class's list of
2041 // structure member offsets.
2042 unsigned idxValue = CUI->getValue();
2043 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
2045 NextReg = makeAnotherReg(Type::UIntTy);
2046 // Emit an ADD to add FieldOff to the basePtr.
2047 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
2049 // The next type is the member of the structure selected by the
2051 Ty = StTy->getElementTypes()[idxValue];
2052 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
2053 // It's an array or pointer access: [ArraySize x ElementType].
2055 // idx is the index into the array. Unlike with structure
2056 // indices, we may not know its actual value at code-generation
2058 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2060 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2061 // operand on X86. Handle this case directly now...
2062 if (CastInst *CI = dyn_cast<CastInst>(idx))
2063 if (CI->getOperand(0)->getType() == Type::IntTy ||
2064 CI->getOperand(0)->getType() == Type::UIntTy)
2065 idx = CI->getOperand(0);
2067 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2068 // must find the size of the pointed-to type (Not coincidentally, the next
2069 // type is the type of the elements in the array).
2070 Ty = SqTy->getElementType();
2071 unsigned elementSize = TD.getTypeSize(Ty);
2073 // If idxReg is a constant, we don't need to perform the multiply!
2074 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2075 if (!CSI->isNullValue()) {
2076 unsigned Offset = elementSize*CSI->getValue();
2077 NextReg = makeAnotherReg(Type::UIntTy);
2078 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
2080 } else if (elementSize == 1) {
2081 // If the element size is 1, we don't have to multiply, just add
2082 unsigned idxReg = getReg(idx, MBB, IP);
2083 NextReg = makeAnotherReg(Type::UIntTy);
2084 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
2086 unsigned idxReg = getReg(idx, MBB, IP);
2087 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2089 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2091 // Emit an ADD to add OffsetReg to the basePtr.
2092 NextReg = makeAnotherReg(Type::UIntTy);
2093 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
2096 // Now that we are here, further indices refer to subtypes of this
2097 // one, so we don't need to worry about BaseReg itself, anymore.
2100 // After we have processed all the indices, the result is left in
2101 // BaseReg. Move it to the register where we were expected to
2102 // put the answer. A 32-bit move should do it, because we are in
2104 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2108 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2109 /// frame manager, otherwise do it the hard way.
2111 void ISel::visitAllocaInst(AllocaInst &I) {
2112 // Find the data size of the alloca inst's getAllocatedType.
2113 const Type *Ty = I.getAllocatedType();
2114 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2116 // If this is a fixed size alloca in the entry block for the function,
2117 // statically stack allocate the space.
2119 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2120 if (I.getParent() == I.getParent()->getParent()->begin()) {
2121 TySize *= CUI->getValue(); // Get total allocated size...
2122 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2124 // Create a new stack object using the frame manager...
2125 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2126 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2131 // Create a register to hold the temporary result of multiplying the type size
2132 // constant by the variable amount.
2133 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2134 unsigned SrcReg1 = getReg(I.getArraySize());
2136 // TotalSizeReg = mul <numelements>, <TypeSize>
2137 MachineBasicBlock::iterator MBBI = BB->end();
2138 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2140 // AddedSize = add <TotalSizeReg>, 15
2141 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2142 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2144 // AlignedSize = and <AddedSize>, ~15
2145 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2146 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2148 // Subtract size from stack pointer, thereby allocating some space.
2149 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2151 // Put a pointer to the space into the result register, by copying
2152 // the stack pointer.
2153 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2155 // Inform the Frame Information that we have just allocated a variable-sized
2157 F->getFrameInfo()->CreateVariableSizedObject();
2160 /// visitMallocInst - Malloc instructions are code generated into direct calls
2161 /// to the library malloc.
2163 void ISel::visitMallocInst(MallocInst &I) {
2164 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2167 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2168 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2170 Arg = makeAnotherReg(Type::UIntTy);
2171 unsigned Op0Reg = getReg(I.getOperand(0));
2172 MachineBasicBlock::iterator MBBI = BB->end();
2173 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2176 std::vector<ValueRecord> Args;
2177 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2178 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2179 1).addExternalSymbol("malloc", true);
2180 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2184 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2187 void ISel::visitFreeInst(FreeInst &I) {
2188 std::vector<ValueRecord> Args;
2189 Args.push_back(ValueRecord(I.getOperand(0)));
2190 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2191 1).addExternalSymbol("free", true);
2192 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2195 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2196 /// into a machine code representation is a very simple peep-hole fashion. The
2197 /// generated code sucks but the implementation is nice and simple.
2199 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM,
2200 IntrinsicLowering &IL) {
2201 return new ISel(TM, IL);