1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/GetElementPtrTypeIterator.h"
30 #include "llvm/Support/InstVisitor.h"
31 #include "llvm/Support/CFG.h"
32 #include "Support/Statistic.h"
37 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
41 struct ISel : public FunctionPass, InstVisitor<ISel> {
43 MachineFunction *F; // The function we are compiling into
44 MachineBasicBlock *BB; // The current MBB we are compiling
45 int VarArgsFrameIndex; // FrameIndex for start of varargs area
46 int ReturnAddressIndex; // FrameIndex for the return address
48 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
50 // MBBMap - Mapping between LLVM BB -> Machine BB
51 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
53 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
55 /// runOnFunction - Top level implementation of instruction selection for
56 /// the entire function.
58 bool runOnFunction(Function &Fn) {
59 // First pass over the function, lower any unknown intrinsic functions
60 // with the IntrinsicLowering class.
61 LowerUnknownIntrinsicFunctionCalls(Fn);
63 F = &MachineFunction::construct(&Fn, TM);
65 // Create all of the machine basic blocks for the function...
66 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
67 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
71 // Set up a frame object for the return address. This is used by the
72 // llvm.returnaddress & llvm.frameaddress intrinisics.
73 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
75 // Copy incoming arguments off of the stack...
76 LoadArgumentsToVirtualRegs(Fn);
78 // Instruction select everything except PHI nodes
81 // Select the PHI nodes
84 // Insert the FP_REG_KILL instructions into blocks that need them.
90 // We always build a machine code representation for the function
94 virtual const char *getPassName() const {
95 return "X86 Simple Instruction Selection";
98 /// visitBasicBlock - This method is called when we are visiting a new basic
99 /// block. This simply creates a new MachineBasicBlock to emit code into
100 /// and adds it to the current MachineFunction. Subsequent visit* for
101 /// instructions will be invoked for all instructions in the basic block.
103 void visitBasicBlock(BasicBlock &LLVM_BB) {
104 BB = MBBMap[&LLVM_BB];
107 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
108 /// function, lowering any calls to unknown intrinsic functions into the
109 /// equivalent LLVM code.
111 void LowerUnknownIntrinsicFunctionCalls(Function &F);
113 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
114 /// from the stack into virtual registers.
116 void LoadArgumentsToVirtualRegs(Function &F);
118 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
119 /// because we have to generate our sources into the source basic blocks,
120 /// not the current one.
122 void SelectPHINodes();
124 /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks
125 /// that need them. This only occurs due to the floating point stackifier
126 /// not being aggressive enough to handle arbitrary global stackification.
128 void InsertFPRegKills();
130 // Visitation methods for various instructions. These methods simply emit
131 // fixed X86 code for each instruction.
134 // Control flow operators
135 void visitReturnInst(ReturnInst &RI);
136 void visitBranchInst(BranchInst &BI);
142 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
143 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
145 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
146 const std::vector<ValueRecord> &Args);
147 void visitCallInst(CallInst &I);
148 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
150 // Arithmetic operators
151 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
152 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
153 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
154 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
155 unsigned DestReg, const Type *DestTy,
156 unsigned Op0Reg, unsigned Op1Reg);
157 void doMultiplyConst(MachineBasicBlock *MBB,
158 MachineBasicBlock::iterator MBBI,
159 unsigned DestReg, const Type *DestTy,
160 unsigned Op0Reg, unsigned Op1Val);
161 void visitMul(BinaryOperator &B);
163 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
164 void visitRem(BinaryOperator &B) { visitDivRem(B); }
165 void visitDivRem(BinaryOperator &B);
168 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
169 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
170 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
172 // Comparison operators...
173 void visitSetCondInst(SetCondInst &I);
174 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
175 MachineBasicBlock *MBB,
176 MachineBasicBlock::iterator MBBI);
177 void visitSelectInst(SelectInst &SI);
180 // Memory Instructions
181 void visitLoadInst(LoadInst &I);
182 void visitStoreInst(StoreInst &I);
183 void visitGetElementPtrInst(GetElementPtrInst &I);
184 void visitAllocaInst(AllocaInst &I);
185 void visitMallocInst(MallocInst &I);
186 void visitFreeInst(FreeInst &I);
189 void visitShiftInst(ShiftInst &I);
190 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
191 void visitCastInst(CastInst &I);
192 void visitVANextInst(VANextInst &I);
193 void visitVAArgInst(VAArgInst &I);
195 void visitInstruction(Instruction &I) {
196 std::cerr << "Cannot instruction select: " << I;
200 /// promote32 - Make a value 32-bits wide, and put it somewhere.
202 void promote32(unsigned targetReg, const ValueRecord &VR);
204 /// getAddressingMode - Get the addressing mode to use to address the
205 /// specified value. The returned value should be used with addFullAddress.
206 void getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
207 unsigned &IndexReg, unsigned &Disp);
210 /// getGEPIndex - This is used to fold GEP instructions into X86 addressing
212 void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
213 std::vector<Value*> &GEPOps,
214 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
215 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
217 /// isGEPFoldable - Return true if the specified GEP can be completely
218 /// folded into the addressing mode of a load/store or lea instruction.
219 bool isGEPFoldable(MachineBasicBlock *MBB,
220 Value *Src, User::op_iterator IdxBegin,
221 User::op_iterator IdxEnd, unsigned &BaseReg,
222 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
224 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
225 /// constant expression GEP support.
227 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
228 Value *Src, User::op_iterator IdxBegin,
229 User::op_iterator IdxEnd, unsigned TargetReg);
231 /// emitCastOperation - Common code shared between visitCastInst and
232 /// constant expression cast support.
234 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
235 Value *Src, const Type *DestTy, unsigned TargetReg);
237 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
238 /// and constant expression support.
240 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
241 MachineBasicBlock::iterator IP,
242 Value *Op0, Value *Op1,
243 unsigned OperatorClass, unsigned TargetReg);
245 void emitDivRemOperation(MachineBasicBlock *BB,
246 MachineBasicBlock::iterator IP,
247 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
248 const Type *Ty, unsigned TargetReg);
250 /// emitSetCCOperation - Common code shared between visitSetCondInst and
251 /// constant expression support.
253 void emitSetCCOperation(MachineBasicBlock *BB,
254 MachineBasicBlock::iterator IP,
255 Value *Op0, Value *Op1, unsigned Opcode,
258 /// emitShiftOperation - Common code shared between visitShiftInst and
259 /// constant expression support.
261 void emitShiftOperation(MachineBasicBlock *MBB,
262 MachineBasicBlock::iterator IP,
263 Value *Op, Value *ShiftAmount, bool isLeftShift,
264 const Type *ResultTy, unsigned DestReg);
266 /// emitSelectOperation - Common code shared between visitSelectInst and the
267 /// constant expression support.
268 void emitSelectOperation(MachineBasicBlock *MBB,
269 MachineBasicBlock::iterator IP,
270 Value *Cond, Value *TrueVal, Value *FalseVal,
273 /// copyConstantToRegister - Output the instructions required to put the
274 /// specified constant into the specified register.
276 void copyConstantToRegister(MachineBasicBlock *MBB,
277 MachineBasicBlock::iterator MBBI,
278 Constant *C, unsigned Reg);
280 /// makeAnotherReg - This method returns the next register number we haven't
283 /// Long values are handled somewhat specially. They are always allocated
284 /// as pairs of 32 bit integer values. The register number returned is the
285 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
286 /// of the long value.
288 unsigned makeAnotherReg(const Type *Ty) {
289 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
290 "Current target doesn't have X86 reg info??");
291 const X86RegisterInfo *MRI =
292 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
293 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
294 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
295 // Create the lower part
296 F->getSSARegMap()->createVirtualRegister(RC);
297 // Create the upper part.
298 return F->getSSARegMap()->createVirtualRegister(RC)-1;
301 // Add the mapping of regnumber => reg class to MachineFunction
302 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
303 return F->getSSARegMap()->createVirtualRegister(RC);
306 /// getReg - This method turns an LLVM value into a register number. This
307 /// is guaranteed to produce the same register number for a particular value
308 /// every time it is queried.
310 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
311 unsigned getReg(Value *V) {
312 // Just append to the end of the current bb.
313 MachineBasicBlock::iterator It = BB->end();
314 return getReg(V, BB, It);
316 unsigned getReg(Value *V, MachineBasicBlock *MBB,
317 MachineBasicBlock::iterator IPt) {
318 unsigned &Reg = RegMap[V];
320 Reg = makeAnotherReg(V->getType());
324 // If this operand is a constant, emit the code to copy the constant into
325 // the register here...
327 if (Constant *C = dyn_cast<Constant>(V)) {
328 copyConstantToRegister(MBB, IPt, C, Reg);
329 RegMap.erase(V); // Assign a new name to this constant if ref'd again
330 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
331 // Move the address of the global into the register
332 BuildMI(*MBB, IPt, X86::MOV32ri, 1, Reg).addGlobalAddress(GV);
333 RegMap.erase(V); // Assign a new name to this address if ref'd again
341 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
345 cByte, cShort, cInt, cFP, cLong
348 /// getClass - Turn a primitive type into a "class" number which is based on the
349 /// size of the type, and whether or not it is floating point.
351 static inline TypeClass getClass(const Type *Ty) {
352 switch (Ty->getPrimitiveID()) {
353 case Type::SByteTyID:
354 case Type::UByteTyID: return cByte; // Byte operands are class #0
355 case Type::ShortTyID:
356 case Type::UShortTyID: return cShort; // Short operands are class #1
359 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
361 case Type::FloatTyID:
362 case Type::DoubleTyID: return cFP; // Floating Point is #3
365 case Type::ULongTyID: return cLong; // Longs are class #4
367 assert(0 && "Invalid type to getClass!");
368 return cByte; // not reached
372 // getClassB - Just like getClass, but treat boolean values as bytes.
373 static inline TypeClass getClassB(const Type *Ty) {
374 if (Ty == Type::BoolTy) return cByte;
379 /// copyConstantToRegister - Output the instructions required to put the
380 /// specified constant into the specified register.
382 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
383 MachineBasicBlock::iterator IP,
384 Constant *C, unsigned R) {
385 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
387 switch (CE->getOpcode()) {
388 case Instruction::GetElementPtr:
389 emitGEPOperation(MBB, IP, CE->getOperand(0),
390 CE->op_begin()+1, CE->op_end(), R);
392 case Instruction::Cast:
393 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
396 case Instruction::Xor: ++Class; // FALL THROUGH
397 case Instruction::Or: ++Class; // FALL THROUGH
398 case Instruction::And: ++Class; // FALL THROUGH
399 case Instruction::Sub: ++Class; // FALL THROUGH
400 case Instruction::Add:
401 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
405 case Instruction::Mul: {
406 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
407 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
408 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
411 case Instruction::Div:
412 case Instruction::Rem: {
413 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
414 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
415 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
416 CE->getOpcode() == Instruction::Div,
421 case Instruction::SetNE:
422 case Instruction::SetEQ:
423 case Instruction::SetLT:
424 case Instruction::SetGT:
425 case Instruction::SetLE:
426 case Instruction::SetGE:
427 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
431 case Instruction::Shl:
432 case Instruction::Shr:
433 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
434 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
437 case Instruction::Select:
438 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
439 CE->getOperand(2), R);
443 std::cerr << "Offending expr: " << C << "\n";
444 assert(0 && "Constant expression not yet handled!\n");
448 if (C->getType()->isIntegral()) {
449 unsigned Class = getClassB(C->getType());
451 if (Class == cLong) {
452 // Copy the value into the register pair.
453 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
454 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(Val & 0xFFFFFFFF);
455 BuildMI(*MBB, IP, X86::MOV32ri, 1, R+1).addImm(Val >> 32);
459 assert(Class <= cInt && "Type not handled yet!");
461 static const unsigned IntegralOpcodeTab[] = {
462 X86::MOV8ri, X86::MOV16ri, X86::MOV32ri
465 if (C->getType() == Type::BoolTy) {
466 BuildMI(*MBB, IP, X86::MOV8ri, 1, R).addImm(C == ConstantBool::True);
468 ConstantInt *CI = cast<ConstantInt>(C);
469 BuildMI(*MBB, IP, IntegralOpcodeTab[Class],1,R).addImm(CI->getRawValue());
471 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
472 if (CFP->isExactlyValue(+0.0))
473 BuildMI(*MBB, IP, X86::FLD0, 0, R);
474 else if (CFP->isExactlyValue(+1.0))
475 BuildMI(*MBB, IP, X86::FLD1, 0, R);
477 // Otherwise we need to spill the constant to memory...
478 MachineConstantPool *CP = F->getConstantPool();
479 unsigned CPI = CP->getConstantPoolIndex(CFP);
480 const Type *Ty = CFP->getType();
482 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
483 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLD32m : X86::FLD64m;
484 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 4, R), CPI);
487 } else if (isa<ConstantPointerNull>(C)) {
488 // Copy zero (null pointer) to the register.
489 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(0);
490 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
491 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addGlobalAddress(CPR->getValue());
493 std::cerr << "Offending constant: " << C << "\n";
494 assert(0 && "Type not handled yet!");
498 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
499 /// the stack into virtual registers.
501 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
502 // Emit instructions to load the arguments... On entry to a function on the
503 // X86, the stack frame looks like this:
505 // [ESP] -- return address
506 // [ESP + 4] -- first argument (leftmost lexically)
507 // [ESP + 8] -- second argument, if first argument is four bytes in size
510 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
511 MachineFrameInfo *MFI = F->getFrameInfo();
513 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
514 unsigned Reg = getReg(*I);
516 int FI; // Frame object index
517 switch (getClassB(I->getType())) {
519 FI = MFI->CreateFixedObject(1, ArgOffset);
520 addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Reg), FI);
523 FI = MFI->CreateFixedObject(2, ArgOffset);
524 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Reg), FI);
527 FI = MFI->CreateFixedObject(4, ArgOffset);
528 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
531 FI = MFI->CreateFixedObject(8, ArgOffset);
532 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
533 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg+1), FI, 4);
534 ArgOffset += 4; // longs require 4 additional bytes
538 if (I->getType() == Type::FloatTy) {
539 Opcode = X86::FLD32m;
540 FI = MFI->CreateFixedObject(4, ArgOffset);
542 Opcode = X86::FLD64m;
543 FI = MFI->CreateFixedObject(8, ArgOffset);
544 ArgOffset += 4; // doubles require 4 additional bytes
546 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
549 assert(0 && "Unhandled argument type!");
551 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
554 // If the function takes variable number of arguments, add a frame offset for
555 // the start of the first vararg value... this is used to expand
557 if (Fn.getFunctionType()->isVarArg())
558 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
562 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
563 /// because we have to generate our sources into the source basic blocks, not
566 void ISel::SelectPHINodes() {
567 const TargetInstrInfo &TII = TM.getInstrInfo();
568 const Function &LF = *F->getFunction(); // The LLVM function...
569 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
570 const BasicBlock *BB = I;
571 MachineBasicBlock &MBB = *MBBMap[I];
573 // Loop over all of the PHI nodes in the LLVM basic block...
574 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
575 for (BasicBlock::const_iterator I = BB->begin();
576 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
578 // Create a new machine instr PHI node, and insert it.
579 unsigned PHIReg = getReg(*PN);
580 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
581 X86::PHI, PN->getNumOperands(), PHIReg);
583 MachineInstr *LongPhiMI = 0;
584 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
585 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
586 X86::PHI, PN->getNumOperands(), PHIReg+1);
588 // PHIValues - Map of blocks to incoming virtual registers. We use this
589 // so that we only initialize one incoming value for a particular block,
590 // even if the block has multiple entries in the PHI node.
592 std::map<MachineBasicBlock*, unsigned> PHIValues;
594 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
595 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
597 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
598 PHIValues.lower_bound(PredMBB);
600 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
601 // We already inserted an initialization of the register for this
602 // predecessor. Recycle it.
603 ValReg = EntryIt->second;
606 // Get the incoming value into a virtual register.
608 Value *Val = PN->getIncomingValue(i);
610 // If this is a constant or GlobalValue, we may have to insert code
611 // into the basic block to compute it into a virtual register.
612 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
613 if (isa<ConstantExpr>(Val)) {
614 // Because we don't want to clobber any values which might be in
615 // physical registers with the computation of this constant (which
616 // might be arbitrarily complex if it is a constant expression),
617 // just insert the computation at the top of the basic block.
618 MachineBasicBlock::iterator PI = PredMBB->begin();
620 // Skip over any PHI nodes though!
621 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
624 ValReg = getReg(Val, PredMBB, PI);
626 // Simple constants get emitted at the end of the basic block,
627 // before any terminator instructions. We "know" that the code to
628 // move a constant into a register will never clobber any flags.
629 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
632 ValReg = getReg(Val);
635 // Remember that we inserted a value for this PHI for this predecessor
636 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
639 PhiMI->addRegOperand(ValReg);
640 PhiMI->addMachineBasicBlockOperand(PredMBB);
642 LongPhiMI->addRegOperand(ValReg+1);
643 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
647 // Now that we emitted all of the incoming values for the PHI node, make
648 // sure to reposition the InsertPoint after the PHI that we just added.
649 // This is needed because we might have inserted a constant into this
650 // block, right after the PHI's which is before the old insert point!
651 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
657 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
658 /// compensation code on critical edges. As such, it requires that we kill all
659 /// FP registers on the exit from any blocks that either ARE critical edges, or
660 /// branch to a block that has incoming critical edges.
662 /// Note that this kill instruction will eventually be eliminated when
663 /// restrictions in the stackifier are relaxed.
665 static bool RequiresFPRegKill(const BasicBlock *BB) {
667 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
668 const BasicBlock *Succ = *SI;
669 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
670 ++PI; // Block have at least one predecessory
671 if (PI != PE) { // If it has exactly one, this isn't crit edge
672 // If this block has more than one predecessor, check all of the
673 // predecessors to see if they have multiple successors. If so, then the
674 // block we are analyzing needs an FPRegKill.
675 for (PI = pred_begin(Succ); PI != PE; ++PI) {
676 const BasicBlock *Pred = *PI;
677 succ_const_iterator SI2 = succ_begin(Pred);
678 ++SI2; // There must be at least one successor of this block.
679 if (SI2 != succ_end(Pred))
680 return true; // Yes, we must insert the kill on this edge.
684 // If we got this far, there is no need to insert the kill instruction.
691 // InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that
692 // need them. This only occurs due to the floating point stackifier not being
693 // aggressive enough to handle arbitrary global stackification.
695 // Currently we insert an FP_REG_KILL instruction into each block that uses or
696 // defines a floating point virtual register.
698 // When the global register allocators (like linear scan) finally update live
699 // variable analysis, we can keep floating point values in registers across
700 // portions of the CFG that do not involve critical edges. This will be a big
701 // win, but we are waiting on the global allocators before we can do this.
703 // With a bit of work, the floating point stackifier pass can be enhanced to
704 // break critical edges as needed (to make a place to put compensation code),
705 // but this will require some infrastructure improvements as well.
707 void ISel::InsertFPRegKills() {
708 SSARegMap &RegMap = *F->getSSARegMap();
710 for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
711 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
712 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
713 MachineOperand& MO = I->getOperand(i);
714 if (MO.isRegister() && MO.getReg()) {
715 unsigned Reg = MO.getReg();
716 if (MRegisterInfo::isVirtualRegister(Reg))
717 if (RegMap.getRegClass(Reg)->getSize() == 10)
721 // If we haven't found an FP register use or def in this basic block, check
722 // to see if any of our successors has an FP PHI node, which will cause a
723 // copy to be inserted into this block.
724 for (succ_const_iterator SI = succ_begin(BB->getBasicBlock()),
725 E = succ_end(BB->getBasicBlock()); SI != E; ++SI) {
726 MachineBasicBlock *SBB = MBBMap[*SI];
727 for (MachineBasicBlock::iterator I = SBB->begin();
728 I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
729 if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
735 // Okay, this block uses an FP register. If the block has successors (ie,
736 // it's not an unwind/return), insert the FP_REG_KILL instruction.
737 if (BB->getBasicBlock()->getTerminator()->getNumSuccessors() &&
738 RequiresFPRegKill(BB->getBasicBlock())) {
739 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
746 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
747 // it into the conditional branch or select instruction which is the only user
748 // of the cc instruction. This is the case if the conditional branch is the
749 // only user of the setcc, and if the setcc is in the same basic block as the
750 // conditional branch. We also don't handle long arguments below, so we reject
751 // them here as well.
753 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
754 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
755 if (SCI->hasOneUse()) {
756 Instruction *User = cast<Instruction>(SCI->use_back());
757 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
758 SCI->getParent() == User->getParent() &&
759 getClassB(SCI->getOperand(0)->getType()) != cLong)
765 // Return a fixed numbering for setcc instructions which does not depend on the
766 // order of the opcodes.
768 static unsigned getSetCCNumber(unsigned Opcode) {
770 default: assert(0 && "Unknown setcc instruction!");
771 case Instruction::SetEQ: return 0;
772 case Instruction::SetNE: return 1;
773 case Instruction::SetLT: return 2;
774 case Instruction::SetGE: return 3;
775 case Instruction::SetGT: return 4;
776 case Instruction::SetLE: return 5;
780 // LLVM -> X86 signed X86 unsigned
781 // ----- ---------- ------------
782 // seteq -> sete sete
783 // setne -> setne setne
784 // setlt -> setl setb
785 // setge -> setge setae
786 // setgt -> setg seta
787 // setle -> setle setbe
789 // sets // Used by comparison with 0 optimization
791 static const unsigned SetCCOpcodeTab[2][8] = {
792 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
794 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
795 X86::SETSr, X86::SETNSr },
798 // EmitComparison - This function emits a comparison of the two operands,
799 // returning the extended setcc code to use.
800 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
801 MachineBasicBlock *MBB,
802 MachineBasicBlock::iterator IP) {
803 // The arguments are already supposed to be of the same type.
804 const Type *CompTy = Op0->getType();
805 unsigned Class = getClassB(CompTy);
806 unsigned Op0r = getReg(Op0, MBB, IP);
808 // Special case handling of: cmp R, i
809 if (Class == cByte || Class == cShort || Class == cInt)
810 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
811 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
813 // Mask off any upper bits of the constant, if there are any...
814 Op1v &= (1ULL << (8 << Class)) - 1;
816 // If this is a comparison against zero, emit more efficient code. We
817 // can't handle unsigned comparisons against zero unless they are == or
818 // !=. These should have been strength reduced already anyway.
819 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
820 static const unsigned TESTTab[] = {
821 X86::TEST8rr, X86::TEST16rr, X86::TEST32rr
823 BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
825 if (OpNum == 2) return 6; // Map jl -> js
826 if (OpNum == 3) return 7; // Map jg -> jns
830 static const unsigned CMPTab[] = {
831 X86::CMP8ri, X86::CMP16ri, X86::CMP32ri
834 BuildMI(*MBB, IP, CMPTab[Class], 2).addReg(Op0r).addImm(Op1v);
838 // Special case handling of comparison against +/- 0.0
839 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
840 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
841 BuildMI(*MBB, IP, X86::FTST, 1).addReg(Op0r);
842 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
843 BuildMI(*MBB, IP, X86::SAHF, 1);
847 unsigned Op1r = getReg(Op1, MBB, IP);
849 default: assert(0 && "Unknown type class!");
850 // Emit: cmp <var1>, <var2> (do the comparison). We can
851 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
854 BuildMI(*MBB, IP, X86::CMP8rr, 2).addReg(Op0r).addReg(Op1r);
857 BuildMI(*MBB, IP, X86::CMP16rr, 2).addReg(Op0r).addReg(Op1r);
860 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
863 BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
864 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
865 BuildMI(*MBB, IP, X86::SAHF, 1);
869 if (OpNum < 2) { // seteq, setne
870 unsigned LoTmp = makeAnotherReg(Type::IntTy);
871 unsigned HiTmp = makeAnotherReg(Type::IntTy);
872 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
873 BuildMI(*MBB, IP, X86::XOR32rr, 2, LoTmp).addReg(Op0r).addReg(Op1r);
874 BuildMI(*MBB, IP, X86::XOR32rr, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
875 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
876 break; // Allow the sete or setne to be generated from flags set by OR
878 // Emit a sequence of code which compares the high and low parts once
879 // each, then uses a conditional move to handle the overflow case. For
880 // example, a setlt for long would generate code like this:
882 // AL = lo(op1) < lo(op2) // Signedness depends on operands
883 // BL = hi(op1) < hi(op2) // Always unsigned comparison
884 // dest = hi(op1) == hi(op2) ? AL : BL;
887 // FIXME: This would be much better if we had hierarchical register
888 // classes! Until then, hardcode registers so that we can deal with their
889 // aliases (because we don't have conditional byte moves).
891 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
892 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
893 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r+1).addReg(Op1r+1);
894 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
895 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
896 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
897 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
899 // NOTE: visitSetCondInst knows that the value is dumped into the BL
900 // register at this point for long values...
907 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
908 /// register, then move it to wherever the result should be.
910 void ISel::visitSetCondInst(SetCondInst &I) {
911 if (canFoldSetCCIntoBranchOrSelect(&I))
912 return; // Fold this into a branch or select.
914 unsigned DestReg = getReg(I);
915 MachineBasicBlock::iterator MII = BB->end();
916 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
920 /// emitSetCCOperation - Common code shared between visitSetCondInst and
921 /// constant expression support.
923 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
924 MachineBasicBlock::iterator IP,
925 Value *Op0, Value *Op1, unsigned Opcode,
926 unsigned TargetReg) {
927 unsigned OpNum = getSetCCNumber(Opcode);
928 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
930 const Type *CompTy = Op0->getType();
931 unsigned CompClass = getClassB(CompTy);
932 bool isSigned = CompTy->isSigned() && CompClass != cFP;
934 if (CompClass != cLong || OpNum < 2) {
935 // Handle normal comparisons with a setcc instruction...
936 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
938 // Handle long comparisons by copying the value which is already in BL into
939 // the register we want...
940 BuildMI(*MBB, IP, X86::MOV8rr, 1, TargetReg).addReg(X86::BL);
944 void ISel::visitSelectInst(SelectInst &SI) {
945 unsigned DestReg = getReg(SI);
946 MachineBasicBlock::iterator MII = BB->end();
947 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
948 SI.getFalseValue(), DestReg);
951 /// emitSelect - Common code shared between visitSelectInst and the constant
952 /// expression support.
953 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
954 MachineBasicBlock::iterator IP,
955 Value *Cond, Value *TrueVal, Value *FalseVal,
957 unsigned SelectClass = getClassB(TrueVal->getType());
959 // We don't support 8-bit conditional moves. If we have incoming constants,
960 // transform them into 16-bit constants to avoid having a run-time conversion.
961 if (SelectClass == cByte) {
962 if (Constant *T = dyn_cast<Constant>(TrueVal))
963 TrueVal = ConstantExpr::getCast(T, Type::ShortTy);
964 if (Constant *F = dyn_cast<Constant>(FalseVal))
965 FalseVal = ConstantExpr::getCast(F, Type::ShortTy);
970 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
971 // We successfully folded the setcc into the select instruction.
973 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
974 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
977 const Type *CompTy = SCI->getOperand(0)->getType();
978 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
980 // LLVM -> X86 signed X86 unsigned
981 // ----- ---------- ------------
982 // seteq -> cmovNE cmovNE
983 // setne -> cmovE cmovE
984 // setlt -> cmovGE cmovAE
985 // setge -> cmovL cmovB
986 // setgt -> cmovLE cmovBE
987 // setle -> cmovG cmovA
989 // cmovNS // Used by comparison with 0 optimization
992 switch (SelectClass) {
993 default: assert(0 && "Unknown value class!");
995 // Annoyingly, we don't have a full set of floating point conditional
997 static const unsigned OpcodeTab[2][8] = {
998 { X86::FCMOVNE, X86::FCMOVE, X86::FCMOVAE, X86::FCMOVB,
999 X86::FCMOVBE, X86::FCMOVA, 0, 0 },
1000 { X86::FCMOVNE, X86::FCMOVE, 0, 0, 0, 0, 0, 0 },
1002 Opcode = OpcodeTab[isSigned][OpNum];
1004 // If opcode == 0, we hit a case that we don't support. Output a setcc
1005 // and compare the result against zero.
1007 unsigned CompClass = getClassB(CompTy);
1009 if (CompClass != cLong || OpNum < 2) {
1010 CondReg = makeAnotherReg(Type::BoolTy);
1011 // Handle normal comparisons with a setcc instruction...
1012 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, CondReg);
1014 // Long comparisons end up in the BL register.
1018 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1019 Opcode = X86::FCMOVE;
1025 static const unsigned OpcodeTab[2][8] = {
1026 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVAE16rr, X86::CMOVB16rr,
1027 X86::CMOVBE16rr, X86::CMOVA16rr, 0, 0 },
1028 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVGE16rr, X86::CMOVL16rr,
1029 X86::CMOVLE16rr, X86::CMOVG16rr, X86::CMOVNS16rr, X86::CMOVS16rr },
1031 Opcode = OpcodeTab[isSigned][OpNum];
1036 static const unsigned OpcodeTab[2][8] = {
1037 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVAE32rr, X86::CMOVB32rr,
1038 X86::CMOVBE32rr, X86::CMOVA32rr, 0, 0 },
1039 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVGE32rr, X86::CMOVL32rr,
1040 X86::CMOVLE32rr, X86::CMOVG32rr, X86::CMOVNS32rr, X86::CMOVS32rr },
1042 Opcode = OpcodeTab[isSigned][OpNum];
1047 // Get the value being branched on, and use it to set the condition codes.
1048 unsigned CondReg = getReg(Cond, MBB, IP);
1049 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1050 switch (SelectClass) {
1051 default: assert(0 && "Unknown value class!");
1052 case cFP: Opcode = X86::FCMOVE; break;
1054 case cShort: Opcode = X86::CMOVE16rr; break;
1056 case cLong: Opcode = X86::CMOVE32rr; break;
1060 unsigned TrueReg = getReg(TrueVal, MBB, IP);
1061 unsigned FalseReg = getReg(FalseVal, MBB, IP);
1062 unsigned RealDestReg = DestReg;
1065 // Annoyingly enough, X86 doesn't HAVE 8-bit conditional moves. Because of
1066 // this, we have to promote the incoming values to 16 bits, perform a 16-bit
1067 // cmove, then truncate the result.
1068 if (SelectClass == cByte) {
1069 DestReg = makeAnotherReg(Type::ShortTy);
1070 if (getClassB(TrueVal->getType()) == cByte) {
1071 // Promote the true value, by storing it into AL, and reading from AX.
1072 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::AL).addReg(TrueReg);
1073 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::AH).addImm(0);
1074 TrueReg = makeAnotherReg(Type::ShortTy);
1075 BuildMI(*MBB, IP, X86::MOV16rr, 1, TrueReg).addReg(X86::AX);
1077 if (getClassB(FalseVal->getType()) == cByte) {
1078 // Promote the true value, by storing it into CL, and reading from CX.
1079 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(FalseReg);
1080 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::CH).addImm(0);
1081 FalseReg = makeAnotherReg(Type::ShortTy);
1082 BuildMI(*MBB, IP, X86::MOV16rr, 1, FalseReg).addReg(X86::CX);
1086 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(TrueReg).addReg(FalseReg);
1088 switch (SelectClass) {
1090 // We did the computation with 16-bit registers. Truncate back to our
1091 // result by copying into AX then copying out AL.
1092 BuildMI(*MBB, IP, X86::MOV16rr, 1, X86::AX).addReg(DestReg);
1093 BuildMI(*MBB, IP, X86::MOV8rr, 1, RealDestReg).addReg(X86::AL);
1096 // Move the upper half of the value as well.
1097 BuildMI(*MBB, IP, Opcode, 2,DestReg+1).addReg(TrueReg+1).addReg(FalseReg+1);
1104 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1105 /// operand, in the specified target register.
1107 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1108 bool isUnsigned = VR.Ty->isUnsigned();
1110 Value *Val = VR.Val;
1111 const Type *Ty = VR.Ty;
1113 if (Constant *C = dyn_cast<Constant>(Val)) {
1114 Val = ConstantExpr::getCast(C, Type::IntTy);
1118 // If this is a simple constant, just emit a MOVri directly to avoid the
1120 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1121 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1122 BuildMI(BB, X86::MOV32ri, 1, targetReg).addImm(TheVal);
1127 // Make sure we have the register number for this value...
1128 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1130 switch (getClassB(Ty)) {
1132 // Extend value into target register (8->32)
1134 BuildMI(BB, X86::MOVZX32rr8, 1, targetReg).addReg(Reg);
1136 BuildMI(BB, X86::MOVSX32rr8, 1, targetReg).addReg(Reg);
1139 // Extend value into target register (16->32)
1141 BuildMI(BB, X86::MOVZX32rr16, 1, targetReg).addReg(Reg);
1143 BuildMI(BB, X86::MOVSX32rr16, 1, targetReg).addReg(Reg);
1146 // Move value into target register (32->32)
1147 BuildMI(BB, X86::MOV32rr, 1, targetReg).addReg(Reg);
1150 assert(0 && "Unpromotable operand class in promote32");
1154 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
1155 /// we have the following possibilities:
1157 /// ret void: No return value, simply emit a 'ret' instruction
1158 /// ret sbyte, ubyte : Extend value into EAX and return
1159 /// ret short, ushort: Extend value into EAX and return
1160 /// ret int, uint : Move value into EAX and return
1161 /// ret pointer : Move value into EAX and return
1162 /// ret long, ulong : Move value into EAX/EDX and return
1163 /// ret float/double : Top of FP stack
1165 void ISel::visitReturnInst(ReturnInst &I) {
1166 if (I.getNumOperands() == 0) {
1167 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
1171 Value *RetVal = I.getOperand(0);
1172 switch (getClassB(RetVal->getType())) {
1173 case cByte: // integral return values: extend or move into EAX and return
1176 promote32(X86::EAX, ValueRecord(RetVal));
1177 // Declare that EAX is live on exit
1178 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
1180 case cFP: { // Floats & Doubles: Return in ST(0)
1181 unsigned RetReg = getReg(RetVal);
1182 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
1183 // Declare that top-of-stack is live on exit
1184 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
1188 unsigned RetReg = getReg(RetVal);
1189 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
1190 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
1191 // Declare that EAX & EDX are live on exit
1192 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
1197 visitInstruction(I);
1199 // Emit a 'ret' instruction
1200 BuildMI(BB, X86::RET, 0);
1203 // getBlockAfter - Return the basic block which occurs lexically after the
1205 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1206 Function::iterator I = BB; ++I; // Get iterator to next block
1207 return I != BB->getParent()->end() ? &*I : 0;
1210 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1211 /// that since code layout is frozen at this point, that if we are trying to
1212 /// jump to a block that is the immediate successor of the current block, we can
1213 /// just make a fall-through (but we don't currently).
1215 void ISel::visitBranchInst(BranchInst &BI) {
1216 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1218 if (!BI.isConditional()) { // Unconditional branch?
1219 if (BI.getSuccessor(0) != NextBB)
1220 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1224 // See if we can fold the setcc into the branch itself...
1225 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1227 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1228 // computed some other way...
1229 unsigned condReg = getReg(BI.getCondition());
1230 BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
1231 if (BI.getSuccessor(1) == NextBB) {
1232 if (BI.getSuccessor(0) != NextBB)
1233 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
1235 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
1237 if (BI.getSuccessor(0) != NextBB)
1238 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1243 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1244 MachineBasicBlock::iterator MII = BB->end();
1245 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1247 const Type *CompTy = SCI->getOperand(0)->getType();
1248 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1251 // LLVM -> X86 signed X86 unsigned
1252 // ----- ---------- ------------
1260 // js // Used by comparison with 0 optimization
1263 static const unsigned OpcodeTab[2][8] = {
1264 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1265 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1266 X86::JS, X86::JNS },
1269 if (BI.getSuccessor(0) != NextBB) {
1270 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
1271 if (BI.getSuccessor(1) != NextBB)
1272 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
1274 // Change to the inverse condition...
1275 if (BI.getSuccessor(1) != NextBB) {
1277 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
1283 /// doCall - This emits an abstract call instruction, setting up the arguments
1284 /// and the return value as appropriate. For the actual function call itself,
1285 /// it inserts the specified CallMI instruction into the stream.
1287 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1288 const std::vector<ValueRecord> &Args) {
1290 // Count how many bytes are to be pushed on the stack...
1291 unsigned NumBytes = 0;
1293 if (!Args.empty()) {
1294 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1295 switch (getClassB(Args[i].Ty)) {
1296 case cByte: case cShort: case cInt:
1297 NumBytes += 4; break;
1299 NumBytes += 8; break;
1301 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1303 default: assert(0 && "Unknown class!");
1306 // Adjust the stack pointer for the new arguments...
1307 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1309 // Arguments go on the stack in reverse order, as specified by the ABI.
1310 unsigned ArgOffset = 0;
1311 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1313 switch (getClassB(Args[i].Ty)) {
1316 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1317 // Zero/Sign extend constant, then stuff into memory.
1318 ConstantInt *Val = cast<ConstantInt>(Args[i].Val);
1319 Val = cast<ConstantInt>(ConstantExpr::getCast(Val, Type::IntTy));
1320 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1321 .addImm(Val->getRawValue() & 0xFFFFFFFF);
1323 // Promote arg to 32 bits wide into a temporary register...
1324 ArgReg = makeAnotherReg(Type::UIntTy);
1325 promote32(ArgReg, Args[i]);
1326 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1327 X86::ESP, ArgOffset).addReg(ArgReg);
1331 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1332 unsigned Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1333 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1334 X86::ESP, ArgOffset).addImm(Val);
1336 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1337 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1338 X86::ESP, ArgOffset).addReg(ArgReg);
1342 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1343 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1344 X86::ESP, ArgOffset).addReg(ArgReg);
1345 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1346 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1347 ArgOffset += 4; // 8 byte entry, not 4.
1351 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1352 if (Args[i].Ty == Type::FloatTy) {
1353 addRegOffset(BuildMI(BB, X86::FST32m, 5),
1354 X86::ESP, ArgOffset).addReg(ArgReg);
1356 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1357 addRegOffset(BuildMI(BB, X86::FST64m, 5),
1358 X86::ESP, ArgOffset).addReg(ArgReg);
1359 ArgOffset += 4; // 8 byte entry, not 4.
1363 default: assert(0 && "Unknown class!");
1368 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(0);
1371 BB->push_back(CallMI);
1373 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addImm(NumBytes);
1375 // If there is a return value, scavenge the result from the location the call
1378 if (Ret.Ty != Type::VoidTy) {
1379 unsigned DestClass = getClassB(Ret.Ty);
1380 switch (DestClass) {
1384 // Integral results are in %eax, or the appropriate portion
1386 static const unsigned regRegMove[] = {
1387 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr
1389 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1390 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1393 case cFP: // Floating-point return values live in %ST(0)
1394 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1396 case cLong: // Long values are left in EDX:EAX
1397 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg).addReg(X86::EAX);
1398 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg+1).addReg(X86::EDX);
1400 default: assert(0 && "Unknown class!");
1406 /// visitCallInst - Push args on stack and do a procedure call instruction.
1407 void ISel::visitCallInst(CallInst &CI) {
1408 MachineInstr *TheCall;
1409 if (Function *F = CI.getCalledFunction()) {
1410 // Is it an intrinsic function call?
1411 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1412 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1416 // Emit a CALL instruction with PC-relative displacement.
1417 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1418 } else { // Emit an indirect call...
1419 unsigned Reg = getReg(CI.getCalledValue());
1420 TheCall = BuildMI(X86::CALL32r, 1).addReg(Reg);
1423 std::vector<ValueRecord> Args;
1424 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1425 Args.push_back(ValueRecord(CI.getOperand(i)));
1427 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1428 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1432 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1433 /// function, lowering any calls to unknown intrinsic functions into the
1434 /// equivalent LLVM code.
1436 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1437 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1438 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1439 if (CallInst *CI = dyn_cast<CallInst>(I++))
1440 if (Function *F = CI->getCalledFunction())
1441 switch (F->getIntrinsicID()) {
1442 case Intrinsic::not_intrinsic:
1443 case Intrinsic::vastart:
1444 case Intrinsic::vacopy:
1445 case Intrinsic::vaend:
1446 case Intrinsic::returnaddress:
1447 case Intrinsic::frameaddress:
1448 case Intrinsic::memcpy:
1449 case Intrinsic::memset:
1450 // We directly implement these intrinsics
1453 // All other intrinsic calls we must lower.
1454 Instruction *Before = CI->getPrev();
1455 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1456 if (Before) { // Move iterator to instruction after call
1465 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1466 unsigned TmpReg1, TmpReg2;
1468 case Intrinsic::vastart:
1469 // Get the address of the first vararg value...
1470 TmpReg1 = getReg(CI);
1471 addFrameReference(BuildMI(BB, X86::LEA32r, 5, TmpReg1), VarArgsFrameIndex);
1474 case Intrinsic::vacopy:
1475 TmpReg1 = getReg(CI);
1476 TmpReg2 = getReg(CI.getOperand(1));
1477 BuildMI(BB, X86::MOV32rr, 1, TmpReg1).addReg(TmpReg2);
1479 case Intrinsic::vaend: return; // Noop on X86
1481 case Intrinsic::returnaddress:
1482 case Intrinsic::frameaddress:
1483 TmpReg1 = getReg(CI);
1484 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1485 if (ID == Intrinsic::returnaddress) {
1486 // Just load the return address
1487 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, TmpReg1),
1488 ReturnAddressIndex);
1490 addFrameReference(BuildMI(BB, X86::LEA32r, 4, TmpReg1),
1491 ReturnAddressIndex, -4);
1494 // Values other than zero are not implemented yet.
1495 BuildMI(BB, X86::MOV32ri, 1, TmpReg1).addImm(0);
1499 case Intrinsic::memcpy: {
1500 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1502 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1503 Align = AlignC->getRawValue();
1504 if (Align == 0) Align = 1;
1507 // Turn the byte code into # iterations
1510 switch (Align & 3) {
1511 case 2: // WORD aligned
1512 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1513 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1515 CountReg = makeAnotherReg(Type::IntTy);
1516 unsigned ByteReg = getReg(CI.getOperand(3));
1517 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1519 Opcode = X86::REP_MOVSW;
1521 case 0: // DWORD aligned
1522 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1523 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1525 CountReg = makeAnotherReg(Type::IntTy);
1526 unsigned ByteReg = getReg(CI.getOperand(3));
1527 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1529 Opcode = X86::REP_MOVSD;
1531 default: // BYTE aligned
1532 CountReg = getReg(CI.getOperand(3));
1533 Opcode = X86::REP_MOVSB;
1537 // No matter what the alignment is, we put the source in ESI, the
1538 // destination in EDI, and the count in ECX.
1539 TmpReg1 = getReg(CI.getOperand(1));
1540 TmpReg2 = getReg(CI.getOperand(2));
1541 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1542 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1543 BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2);
1544 BuildMI(BB, Opcode, 0);
1547 case Intrinsic::memset: {
1548 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1550 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1551 Align = AlignC->getRawValue();
1552 if (Align == 0) Align = 1;
1555 // Turn the byte code into # iterations
1558 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1559 unsigned Val = ValC->getRawValue() & 255;
1561 // If the value is a constant, then we can potentially use larger copies.
1562 switch (Align & 3) {
1563 case 2: // WORD aligned
1564 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1565 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1567 CountReg = makeAnotherReg(Type::IntTy);
1568 unsigned ByteReg = getReg(CI.getOperand(3));
1569 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1571 BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val);
1572 Opcode = X86::REP_STOSW;
1574 case 0: // DWORD aligned
1575 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1576 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1578 CountReg = makeAnotherReg(Type::IntTy);
1579 unsigned ByteReg = getReg(CI.getOperand(3));
1580 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1582 Val = (Val << 8) | Val;
1583 BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val);
1584 Opcode = X86::REP_STOSD;
1586 default: // BYTE aligned
1587 CountReg = getReg(CI.getOperand(3));
1588 BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val);
1589 Opcode = X86::REP_STOSB;
1593 // If it's not a constant value we are storing, just fall back. We could
1594 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1595 unsigned ValReg = getReg(CI.getOperand(2));
1596 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1597 CountReg = getReg(CI.getOperand(3));
1598 Opcode = X86::REP_STOSB;
1601 // No matter what the alignment is, we put the source in ESI, the
1602 // destination in EDI, and the count in ECX.
1603 TmpReg1 = getReg(CI.getOperand(1));
1604 //TmpReg2 = getReg(CI.getOperand(2));
1605 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1606 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1607 BuildMI(BB, Opcode, 0);
1611 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1615 static bool isSafeToFoldLoadIntoInstruction(LoadInst &LI, Instruction &User) {
1616 if (LI.getParent() != User.getParent())
1618 BasicBlock::iterator It = &LI;
1619 // Check all of the instructions between the load and the user. We should
1620 // really use alias analysis here, but for now we just do something simple.
1621 for (++It; It != BasicBlock::iterator(&User); ++It) {
1622 switch (It->getOpcode()) {
1623 case Instruction::Free:
1624 case Instruction::Store:
1625 case Instruction::Call:
1626 case Instruction::Invoke:
1634 /// visitSimpleBinary - Implement simple binary operators for integral types...
1635 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1638 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1639 unsigned DestReg = getReg(B);
1640 MachineBasicBlock::iterator MI = BB->end();
1641 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1643 // Special case: op Reg, load [mem]
1644 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1))
1645 if (!B.swapOperands())
1646 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
1648 unsigned Class = getClassB(B.getType());
1649 if (isa<LoadInst>(Op1) && Class < cFP &&
1650 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op1), B)) {
1652 static const unsigned OpcodeTab[][3] = {
1653 // Arithmetic operators
1654 { X86::ADD8rm, X86::ADD16rm, X86::ADD32rm }, // ADD
1655 { X86::SUB8rm, X86::SUB16rm, X86::SUB32rm }, // SUB
1657 // Bitwise operators
1658 { X86::AND8rm, X86::AND16rm, X86::AND32rm }, // AND
1659 { X86:: OR8rm, X86:: OR16rm, X86:: OR32rm }, // OR
1660 { X86::XOR8rm, X86::XOR16rm, X86::XOR32rm }, // XOR
1663 assert(Class < cFP && "General code handles 64-bit integer types!");
1664 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1666 unsigned BaseReg, Scale, IndexReg, Disp;
1667 getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), BaseReg,
1668 Scale, IndexReg, Disp);
1670 unsigned Op0r = getReg(Op0);
1671 addFullAddress(BuildMI(BB, Opcode, 2, DestReg).addReg(Op0r),
1672 BaseReg, Scale, IndexReg, Disp);
1676 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1679 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1680 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1683 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1684 /// and constant expression support.
1686 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1687 MachineBasicBlock::iterator IP,
1688 Value *Op0, Value *Op1,
1689 unsigned OperatorClass, unsigned DestReg) {
1690 unsigned Class = getClassB(Op0->getType());
1692 // sub 0, X -> neg X
1693 if (OperatorClass == 1)
1694 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1695 if (CI->isNullValue()) {
1696 unsigned op1Reg = getReg(Op1, MBB, IP);
1697 static unsigned const NEGTab[] = {
1698 X86::NEG8r, X86::NEG16r, X86::NEG32r, 0, X86::NEG32r
1700 BuildMI(*MBB, IP, NEGTab[Class], 1, DestReg).addReg(op1Reg);
1702 if (Class == cLong) {
1703 // We just emitted: Dl = neg Sl
1704 // Now emit : T = addc Sh, 0
1706 unsigned T = makeAnotherReg(Type::IntTy);
1707 BuildMI(*MBB, IP, X86::ADC32ri, 2, T).addReg(op1Reg+1).addImm(0);
1708 BuildMI(*MBB, IP, X86::NEG32r, 1, DestReg+1).addReg(T);
1712 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1713 if (CFP->isExactlyValue(-0.0)) {
1715 unsigned op1Reg = getReg(Op1, MBB, IP);
1716 BuildMI(*MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
1720 // Special case: op Reg, <const>
1721 if (isa<ConstantInt>(Op1)) {
1722 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1723 unsigned Op0r = getReg(Op0, MBB, IP);
1725 // xor X, -1 -> not X
1726 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1727 static unsigned const NOTTab[] = {
1728 X86::NOT8r, X86::NOT16r, X86::NOT32r, 0, X86::NOT32r
1730 BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1731 if (Class == cLong) // Invert the top part too
1732 BuildMI(*MBB, IP, X86::NOT32r, 1, DestReg+1).addReg(Op0r+1);
1736 // add X, -1 -> dec X
1737 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1738 static unsigned const DECTab[] = {
1739 X86::DEC8r, X86::DEC16r, X86::DEC32r, 0, X86::DEC32r
1741 BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1742 if (Class == cLong) // Dh = sbb Sh, 0
1743 BuildMI(*MBB, IP, X86::SBB32ri, 2, DestReg+1).addReg(Op0r+1).addImm(0);
1747 // add X, 1 -> inc X
1748 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1749 static unsigned const INCTab[] = {
1750 X86::INC8r, X86::INC16r, X86::INC32r, 0, X86::INC32r
1752 BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
1753 if (Class == cLong) // Dh = adc Sh, 0
1754 BuildMI(*MBB, IP, X86::ADC32ri, 2, DestReg+1).addReg(Op0r+1).addImm(0);
1758 static const unsigned OpcodeTab[][5] = {
1759 // Arithmetic operators
1760 { X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
1761 { X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
1763 // Bitwise operators
1764 { X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
1765 { X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
1766 { X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
1769 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1771 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1772 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1v &0xFFFFFFFF);
1774 if (Class == cLong) {
1775 static const unsigned TopTab[] = {
1776 X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
1778 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
1779 .addReg(Op0r+1).addImm(uint64_t(Op1v) >> 32);
1784 // Finally, handle the general case now.
1785 static const unsigned OpcodeTab[][5] = {
1786 // Arithmetic operators
1787 { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, X86::FpADD, X86::ADD32rr },// ADD
1788 { X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB, X86::SUB32rr },// SUB
1790 // Bitwise operators
1791 { X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
1792 { X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
1793 { X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
1796 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1797 assert(Opcode && "Floating point arguments to logical inst?");
1798 unsigned Op0r = getReg(Op0, MBB, IP);
1799 unsigned Op1r = getReg(Op1, MBB, IP);
1800 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1802 if (Class == cLong) { // Handle the upper 32 bits of long values...
1803 static const unsigned TopTab[] = {
1804 X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
1806 BuildMI(*MBB, IP, TopTab[OperatorClass], 2,
1807 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1811 /// doMultiply - Emit appropriate instructions to multiply together the
1812 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1813 /// result should be given as DestTy.
1815 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
1816 unsigned DestReg, const Type *DestTy,
1817 unsigned op0Reg, unsigned op1Reg) {
1818 unsigned Class = getClass(DestTy);
1820 case cFP: // Floating point multiply
1821 BuildMI(*MBB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1825 BuildMI(*MBB, MBBI, Class == cInt ? X86::IMUL32rr:X86::IMUL16rr, 2, DestReg)
1826 .addReg(op0Reg).addReg(op1Reg);
1829 // Must use the MUL instruction, which forces use of AL...
1830 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, X86::AL).addReg(op0Reg);
1831 BuildMI(*MBB, MBBI, X86::MUL8r, 1).addReg(op1Reg);
1832 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1835 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1839 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1840 // returns zero when the input is not exactly a power of two.
1841 static unsigned ExactLog2(unsigned Val) {
1842 if (Val == 0) return 0;
1845 if (Val & 1) return 0;
1852 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1853 MachineBasicBlock::iterator IP,
1854 unsigned DestReg, const Type *DestTy,
1855 unsigned op0Reg, unsigned ConstRHS) {
1856 unsigned Class = getClass(DestTy);
1858 // If the element size is exactly a power of 2, use a shift to get it.
1859 if (unsigned Shift = ExactLog2(ConstRHS)) {
1861 default: assert(0 && "Unknown class for this function!");
1863 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
1866 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
1869 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
1874 if (Class == cShort) {
1875 BuildMI(*MBB, IP, X86::IMUL16rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
1877 } else if (Class == cInt) {
1878 BuildMI(*MBB, IP, X86::IMUL32rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
1882 // Most general case, emit a normal multiply...
1883 static const unsigned MOVriTab[] = {
1884 X86::MOV8ri, X86::MOV16ri, X86::MOV32ri
1887 unsigned TmpReg = makeAnotherReg(DestTy);
1888 BuildMI(*MBB, IP, MOVriTab[Class], 1, TmpReg).addImm(ConstRHS);
1890 // Emit a MUL to multiply the register holding the index by
1891 // elementSize, putting the result in OffsetReg.
1892 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1895 /// visitMul - Multiplies are not simple binary operators because they must deal
1896 /// with the EAX register explicitly.
1898 void ISel::visitMul(BinaryOperator &I) {
1899 unsigned Op0Reg = getReg(I.getOperand(0));
1900 unsigned DestReg = getReg(I);
1902 // Simple scalar multiply?
1903 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1904 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1905 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1906 MachineBasicBlock::iterator MBBI = BB->end();
1907 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1909 unsigned Op1Reg = getReg(I.getOperand(1));
1910 MachineBasicBlock::iterator MBBI = BB->end();
1911 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1914 unsigned Op1Reg = getReg(I.getOperand(1));
1916 // Long value. We have to do things the hard way...
1917 // Multiply the two low parts... capturing carry into EDX
1918 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
1919 BuildMI(BB, X86::MUL32r, 1).addReg(Op1Reg); // AL*BL
1921 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1922 BuildMI(BB, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
1923 BuildMI(BB, X86::MOV32rr, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1925 MachineBasicBlock::iterator MBBI = BB->end();
1926 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1927 BuildMI(*BB, MBBI, X86::IMUL32rr,2,AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1929 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1930 BuildMI(*BB, MBBI, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
1931 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1934 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1935 BuildMI(*BB, MBBI, X86::IMUL32rr,2,ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1937 BuildMI(*BB, MBBI, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1938 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1943 /// visitDivRem - Handle division and remainder instructions... these
1944 /// instruction both require the same instructions to be generated, they just
1945 /// select the result from a different register. Note that both of these
1946 /// instructions work differently for signed and unsigned operands.
1948 void ISel::visitDivRem(BinaryOperator &I) {
1949 unsigned Op0Reg = getReg(I.getOperand(0));
1950 unsigned Op1Reg = getReg(I.getOperand(1));
1951 unsigned ResultReg = getReg(I);
1953 MachineBasicBlock::iterator IP = BB->end();
1954 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1955 I.getType(), ResultReg);
1958 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1959 MachineBasicBlock::iterator IP,
1960 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1961 const Type *Ty, unsigned ResultReg) {
1962 unsigned Class = getClass(Ty);
1964 case cFP: // Floating point divide
1966 BuildMI(*BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1967 } else { // Floating point remainder...
1968 MachineInstr *TheCall =
1969 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1970 std::vector<ValueRecord> Args;
1971 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1972 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1973 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1977 static const char *FnName[] =
1978 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1980 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1981 MachineInstr *TheCall =
1982 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1984 std::vector<ValueRecord> Args;
1985 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1986 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1987 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1990 case cByte: case cShort: case cInt:
1991 break; // Small integrals, handled below...
1992 default: assert(0 && "Unknown class!");
1995 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1996 static const unsigned MovOpcode[]={ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr };
1997 static const unsigned SarOpcode[]={ X86::SAR8ri, X86::SAR16ri, X86::SAR32ri };
1998 static const unsigned ClrOpcode[]={ X86::MOV8ri, X86::MOV16ri, X86::MOV32ri };
1999 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
2001 static const unsigned DivOpcode[][4] = {
2002 { X86::DIV8r , X86::DIV16r , X86::DIV32r , 0 }, // Unsigned division
2003 { X86::IDIV8r, X86::IDIV16r, X86::IDIV32r, 0 }, // Signed division
2006 bool isSigned = Ty->isSigned();
2007 unsigned Reg = Regs[Class];
2008 unsigned ExtReg = ExtRegs[Class];
2010 // Put the first operand into one of the A registers...
2011 BuildMI(*BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
2014 // Emit a sign extension instruction...
2015 unsigned ShiftResult = makeAnotherReg(Ty);
2016 BuildMI(*BB, IP, SarOpcode[Class], 2,ShiftResult).addReg(Op0Reg).addImm(31);
2017 BuildMI(*BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
2019 // If unsigned, emit a zeroing instruction... (reg = 0)
2020 BuildMI(*BB, IP, ClrOpcode[Class], 2, ExtReg).addImm(0);
2023 // Emit the appropriate divide or remainder instruction...
2024 BuildMI(*BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
2026 // Figure out which register we want to pick the result out of...
2027 unsigned DestReg = isDiv ? Reg : ExtReg;
2029 // Put the result into the destination register...
2030 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
2034 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2035 /// for constant immediate shift values, and for constant immediate
2036 /// shift values equal to 1. Even the general case is sort of special,
2037 /// because the shift amount has to be in CL, not just any old register.
2039 void ISel::visitShiftInst(ShiftInst &I) {
2040 MachineBasicBlock::iterator IP = BB->end ();
2041 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
2042 I.getOpcode () == Instruction::Shl, I.getType (),
2046 /// emitShiftOperation - Common code shared between visitShiftInst and
2047 /// constant expression support.
2048 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2049 MachineBasicBlock::iterator IP,
2050 Value *Op, Value *ShiftAmount, bool isLeftShift,
2051 const Type *ResultTy, unsigned DestReg) {
2052 unsigned SrcReg = getReg (Op, MBB, IP);
2053 bool isSigned = ResultTy->isSigned ();
2054 unsigned Class = getClass (ResultTy);
2056 static const unsigned ConstantOperand[][4] = {
2057 { X86::SHR8ri, X86::SHR16ri, X86::SHR32ri, X86::SHRD32rri8 }, // SHR
2058 { X86::SAR8ri, X86::SAR16ri, X86::SAR32ri, X86::SHRD32rri8 }, // SAR
2059 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SHL
2060 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SAL = SHL
2063 static const unsigned NonConstantOperand[][4] = {
2064 { X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL }, // SHR
2065 { X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL }, // SAR
2066 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SHL
2067 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SAL = SHL
2070 // Longs, as usual, are handled specially...
2071 if (Class == cLong) {
2072 // If we have a constant shift, we can generate much more efficient code
2073 // than otherwise...
2075 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2076 unsigned Amount = CUI->getValue();
2078 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2080 BuildMI(*MBB, IP, Opc[3], 3,
2081 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addImm(Amount);
2082 BuildMI(*MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addImm(Amount);
2084 BuildMI(*MBB, IP, Opc[3], 3,
2085 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addImm(Amount);
2086 BuildMI(*MBB, IP, Opc[2],2,DestReg+1).addReg(SrcReg+1).addImm(Amount);
2088 } else { // Shifting more than 32 bits
2091 BuildMI(*MBB, IP, X86::SHL32ri, 2,
2092 DestReg + 1).addReg(SrcReg).addImm(Amount);
2093 BuildMI(*MBB, IP, X86::MOV32ri, 1,
2096 unsigned Opcode = isSigned ? X86::SAR32ri : X86::SHR32ri;
2097 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addImm(Amount);
2098 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2102 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2104 if (!isLeftShift && isSigned) {
2105 // If this is a SHR of a Long, then we need to do funny sign extension
2106 // stuff. TmpReg gets the value to use as the high-part if we are
2107 // shifting more than 32 bits.
2108 BuildMI(*MBB, IP, X86::SAR32ri, 2, TmpReg).addReg(SrcReg).addImm(31);
2110 // Other shifts use a fixed zero value if the shift is more than 32
2112 BuildMI(*MBB, IP, X86::MOV32ri, 1, TmpReg).addImm(0);
2115 // Initialize CL with the shift amount...
2116 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
2117 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2119 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2120 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2122 // TmpReg2 = shld inHi, inLo
2123 BuildMI(*MBB, IP, X86::SHLD32rrCL,2,TmpReg2).addReg(SrcReg+1)
2125 // TmpReg3 = shl inLo, CL
2126 BuildMI(*MBB, IP, X86::SHL32rCL, 1, TmpReg3).addReg(SrcReg);
2128 // Set the flags to indicate whether the shift was by more than 32 bits.
2129 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2131 // DestHi = (>32) ? TmpReg3 : TmpReg2;
2132 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2133 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
2134 // DestLo = (>32) ? TmpReg : TmpReg3;
2135 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2136 DestReg).addReg(TmpReg3).addReg(TmpReg);
2138 // TmpReg2 = shrd inLo, inHi
2139 BuildMI(*MBB, IP, X86::SHRD32rrCL,2,TmpReg2).addReg(SrcReg)
2141 // TmpReg3 = s[ah]r inHi, CL
2142 BuildMI(*MBB, IP, isSigned ? X86::SAR32rCL : X86::SHR32rCL, 1, TmpReg3)
2145 // Set the flags to indicate whether the shift was by more than 32 bits.
2146 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2148 // DestLo = (>32) ? TmpReg3 : TmpReg2;
2149 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2150 DestReg).addReg(TmpReg2).addReg(TmpReg3);
2152 // DestHi = (>32) ? TmpReg : TmpReg3;
2153 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2154 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
2160 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2161 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2162 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2164 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2165 BuildMI(*MBB, IP, Opc[Class], 2,
2166 DestReg).addReg(SrcReg).addImm(CUI->getValue());
2167 } else { // The shift amount is non-constant.
2168 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2169 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2171 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
2172 BuildMI(*MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
2177 void ISel::getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
2178 unsigned &IndexReg, unsigned &Disp) {
2179 BaseReg = 0; Scale = 1; IndexReg = 0; Disp = 0;
2180 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
2181 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
2182 BaseReg, Scale, IndexReg, Disp))
2184 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
2185 if (CE->getOpcode() == Instruction::GetElementPtr)
2186 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
2187 BaseReg, Scale, IndexReg, Disp))
2191 // If it's not foldable, reset addr mode.
2192 BaseReg = getReg(Addr);
2193 Scale = 1; IndexReg = 0; Disp = 0;
2197 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
2198 /// instruction. The load and store instructions are the only place where we
2199 /// need to worry about the memory layout of the target machine.
2201 void ISel::visitLoadInst(LoadInst &I) {
2202 // Check to see if this load instruction is going to be folded into a binary
2203 // instruction, like add. If so, we don't want to emit it. Wouldn't a real
2204 // pattern matching instruction selector be nice?
2205 if (I.hasOneUse() && getClassB(I.getType()) < cFP) {
2206 Instruction *User = cast<Instruction>(I.use_back());
2207 switch (User->getOpcode()) {
2208 default: User = 0; break;
2209 case Instruction::Add:
2210 case Instruction::Sub:
2211 case Instruction::And:
2212 case Instruction::Or:
2213 case Instruction::Xor:
2218 // Okay, we found a user. If the load is the first operand and there is
2219 // no second operand load, reverse the operand ordering. Note that this
2220 // can fail for a subtract (ie, no change will be made).
2221 if (!isa<LoadInst>(User->getOperand(1)))
2222 cast<BinaryOperator>(User)->swapOperands();
2224 // Okay, now that everything is set up, if this load is used by the second
2225 // operand, and if there are no instructions that invalidate the load
2226 // before the binary operator, eliminate the load.
2227 if (User->getOperand(1) == &I &&
2228 isSafeToFoldLoadIntoInstruction(I, *User))
2229 return; // Eliminate the load!
2233 unsigned DestReg = getReg(I);
2234 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
2235 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
2237 unsigned Class = getClassB(I.getType());
2238 if (Class == cLong) {
2239 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg),
2240 BaseReg, Scale, IndexReg, Disp);
2241 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1),
2242 BaseReg, Scale, IndexReg, Disp+4);
2246 static const unsigned Opcodes[] = {
2247 X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m
2249 unsigned Opcode = Opcodes[Class];
2250 if (I.getType() == Type::DoubleTy) Opcode = X86::FLD64m;
2251 addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
2252 BaseReg, Scale, IndexReg, Disp);
2255 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
2258 void ISel::visitStoreInst(StoreInst &I) {
2259 unsigned BaseReg, Scale, IndexReg, Disp;
2260 getAddressingMode(I.getOperand(1), BaseReg, Scale, IndexReg, Disp);
2262 const Type *ValTy = I.getOperand(0)->getType();
2263 unsigned Class = getClassB(ValTy);
2265 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
2266 uint64_t Val = CI->getRawValue();
2267 if (Class == cLong) {
2268 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
2269 BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U);
2270 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
2271 BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32);
2273 static const unsigned Opcodes[] = {
2274 X86::MOV8mi, X86::MOV16mi, X86::MOV32mi
2276 unsigned Opcode = Opcodes[Class];
2277 addFullAddress(BuildMI(BB, Opcode, 5),
2278 BaseReg, Scale, IndexReg, Disp).addImm(Val);
2280 } else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
2281 addFullAddress(BuildMI(BB, X86::MOV8mi, 5),
2282 BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue());
2284 if (Class == cLong) {
2285 unsigned ValReg = getReg(I.getOperand(0));
2286 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
2287 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
2288 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
2289 BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
2291 unsigned ValReg = getReg(I.getOperand(0));
2292 static const unsigned Opcodes[] = {
2293 X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST32m
2295 unsigned Opcode = Opcodes[Class];
2296 if (ValTy == Type::DoubleTy) Opcode = X86::FST64m;
2297 addFullAddress(BuildMI(BB, Opcode, 1+4),
2298 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
2304 /// visitCastInst - Here we have various kinds of copying with or without sign
2305 /// extension going on.
2307 void ISel::visitCastInst(CastInst &CI) {
2308 Value *Op = CI.getOperand(0);
2309 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2310 // of the case are GEP instructions, then the cast does not need to be
2311 // generated explicitly, it will be folded into the GEP.
2312 if (CI.getType() == Type::LongTy &&
2313 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
2314 bool AllUsesAreGEPs = true;
2315 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2316 if (!isa<GetElementPtrInst>(*I)) {
2317 AllUsesAreGEPs = false;
2321 // No need to codegen this cast if all users are getelementptr instrs...
2322 if (AllUsesAreGEPs) return;
2325 unsigned DestReg = getReg(CI);
2326 MachineBasicBlock::iterator MI = BB->end();
2327 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2330 /// emitCastOperation - Common code shared between visitCastInst and constant
2331 /// expression cast support.
2333 void ISel::emitCastOperation(MachineBasicBlock *BB,
2334 MachineBasicBlock::iterator IP,
2335 Value *Src, const Type *DestTy,
2337 unsigned SrcReg = getReg(Src, BB, IP);
2338 const Type *SrcTy = Src->getType();
2339 unsigned SrcClass = getClassB(SrcTy);
2340 unsigned DestClass = getClassB(DestTy);
2342 // Implement casts to bool by using compare on the operand followed by set if
2343 // not zero on the result.
2344 if (DestTy == Type::BoolTy) {
2347 BuildMI(*BB, IP, X86::TEST8rr, 2).addReg(SrcReg).addReg(SrcReg);
2350 BuildMI(*BB, IP, X86::TEST16rr, 2).addReg(SrcReg).addReg(SrcReg);
2353 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg).addReg(SrcReg);
2356 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2357 BuildMI(*BB, IP, X86::OR32rr, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
2361 BuildMI(*BB, IP, X86::FTST, 1).addReg(SrcReg);
2362 BuildMI(*BB, IP, X86::FNSTSW8r, 0);
2363 BuildMI(*BB, IP, X86::SAHF, 1);
2367 // If the zero flag is not set, then the value is true, set the byte to
2369 BuildMI(*BB, IP, X86::SETNEr, 1, DestReg);
2373 static const unsigned RegRegMove[] = {
2374 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
2377 // Implement casts between values of the same type class (as determined by
2378 // getClass) by using a register-to-register move.
2379 if (SrcClass == DestClass) {
2380 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
2381 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
2382 } else if (SrcClass == cFP) {
2383 if (SrcTy == Type::FloatTy) { // double -> float
2384 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2385 BuildMI(*BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
2386 } else { // float -> double
2387 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2388 "Unknown cFP member!");
2389 // Truncate from double to float by storing to memory as short, then
2391 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
2392 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
2393 addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5), FrameIdx).addReg(SrcReg);
2394 addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx);
2396 } else if (SrcClass == cLong) {
2397 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
2398 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg+1);
2400 assert(0 && "Cannot handle this type of cast instruction!");
2406 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2407 // or zero extension, depending on whether the source type was signed.
2408 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2409 SrcClass < DestClass) {
2410 bool isLong = DestClass == cLong;
2411 if (isLong) DestClass = cInt;
2413 static const unsigned Opc[][4] = {
2414 { X86::MOVSX16rr8, X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOV32rr }, // s
2415 { X86::MOVZX16rr8, X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOV32rr } // u
2418 bool isUnsigned = SrcTy->isUnsigned();
2419 BuildMI(*BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
2420 DestReg).addReg(SrcReg);
2422 if (isLong) { // Handle upper 32 bits as appropriate...
2423 if (isUnsigned) // Zero out top bits...
2424 BuildMI(*BB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2425 else // Sign extend bottom half...
2426 BuildMI(*BB, IP, X86::SAR32ri, 2, DestReg+1).addReg(DestReg).addImm(31);
2431 // Special case long -> int ...
2432 if (SrcClass == cLong && DestClass == cInt) {
2433 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
2437 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
2438 // move out of AX or AL.
2439 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2440 && SrcClass > DestClass) {
2441 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
2442 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
2443 BuildMI(*BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
2447 // Handle casts from integer to floating point now...
2448 if (DestClass == cFP) {
2449 // Promote the integer to a type supported by FLD. We do this because there
2450 // are no unsigned FLD instructions, so we must promote an unsigned value to
2451 // a larger signed value, then use FLD on the larger value.
2453 const Type *PromoteType = 0;
2454 unsigned PromoteOpcode;
2455 unsigned RealDestReg = DestReg;
2456 switch (SrcTy->getPrimitiveID()) {
2457 case Type::BoolTyID:
2458 case Type::SByteTyID:
2459 // We don't have the facilities for directly loading byte sized data from
2460 // memory (even signed). Promote it to 16 bits.
2461 PromoteType = Type::ShortTy;
2462 PromoteOpcode = X86::MOVSX16rr8;
2464 case Type::UByteTyID:
2465 PromoteType = Type::ShortTy;
2466 PromoteOpcode = X86::MOVZX16rr8;
2468 case Type::UShortTyID:
2469 PromoteType = Type::IntTy;
2470 PromoteOpcode = X86::MOVZX32rr16;
2472 case Type::UIntTyID: {
2473 // Make a 64 bit temporary... and zero out the top of it...
2474 unsigned TmpReg = makeAnotherReg(Type::LongTy);
2475 BuildMI(*BB, IP, X86::MOV32rr, 1, TmpReg).addReg(SrcReg);
2476 BuildMI(*BB, IP, X86::MOV32ri, 1, TmpReg+1).addImm(0);
2477 SrcTy = Type::LongTy;
2482 case Type::ULongTyID:
2483 // Don't fild into the read destination.
2484 DestReg = makeAnotherReg(Type::DoubleTy);
2486 default: // No promotion needed...
2491 unsigned TmpReg = makeAnotherReg(PromoteType);
2492 unsigned Opc = SrcTy->isSigned() ? X86::MOVSX16rr8 : X86::MOVZX16rr8;
2493 BuildMI(*BB, IP, Opc, 1, TmpReg).addReg(SrcReg);
2494 SrcTy = PromoteType;
2495 SrcClass = getClass(PromoteType);
2499 // Spill the integer to memory and reload it from there...
2501 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2503 if (SrcClass == cLong) {
2504 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
2505 FrameIdx).addReg(SrcReg);
2506 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
2507 FrameIdx, 4).addReg(SrcReg+1);
2509 static const unsigned Op1[] = { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr };
2510 addFrameReference(BuildMI(*BB, IP, Op1[SrcClass], 5),
2511 FrameIdx).addReg(SrcReg);
2514 static const unsigned Op2[] =
2515 { 0/*byte*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m };
2516 addFrameReference(BuildMI(*BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
2518 // We need special handling for unsigned 64-bit integer sources. If the
2519 // input number has the "sign bit" set, then we loaded it incorrectly as a
2520 // negative 64-bit number. In this case, add an offset value.
2521 if (SrcTy == Type::ULongTy) {
2522 // Emit a test instruction to see if the dynamic input value was signed.
2523 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg+1).addReg(SrcReg+1);
2525 // If the sign bit is set, get a pointer to an offset, otherwise get a
2526 // pointer to a zero.
2527 MachineConstantPool *CP = F->getConstantPool();
2528 unsigned Zero = makeAnotherReg(Type::IntTy);
2529 Constant *Null = Constant::getNullValue(Type::UIntTy);
2530 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero),
2531 CP->getConstantPoolIndex(Null));
2532 unsigned Offset = makeAnotherReg(Type::IntTy);
2533 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
2535 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Offset),
2536 CP->getConstantPoolIndex(OffsetCst));
2537 unsigned Addr = makeAnotherReg(Type::IntTy);
2538 BuildMI(*BB, IP, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset);
2540 // Load the constant for an add. FIXME: this could make an 'fadd' that
2541 // reads directly from memory, but we don't support these yet.
2542 unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
2543 addDirectMem(BuildMI(*BB, IP, X86::FLD32m, 4, ConstReg), Addr);
2545 BuildMI(*BB, IP, X86::FpADD, 2, RealDestReg)
2546 .addReg(ConstReg).addReg(DestReg);
2552 // Handle casts from floating point to integer now...
2553 if (SrcClass == cFP) {
2554 // Change the floating point control register to use "round towards zero"
2555 // mode when truncating to an integer value.
2557 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
2558 addFrameReference(BuildMI(*BB, IP, X86::FNSTCW16m, 4), CWFrameIdx);
2560 // Load the old value of the high byte of the control word...
2561 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
2562 addFrameReference(BuildMI(*BB, IP, X86::MOV8rm, 4, HighPartOfCW),
2565 // Set the high part to be round to zero...
2566 addFrameReference(BuildMI(*BB, IP, X86::MOV8mi, 5),
2567 CWFrameIdx, 1).addImm(12);
2569 // Reload the modified control word now...
2570 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
2572 // Restore the memory image of control word to original value
2573 addFrameReference(BuildMI(*BB, IP, X86::MOV8mr, 5),
2574 CWFrameIdx, 1).addReg(HighPartOfCW);
2576 // We don't have the facilities for directly storing byte sized data to
2577 // memory. Promote it to 16 bits. We also must promote unsigned values to
2578 // larger classes because we only have signed FP stores.
2579 unsigned StoreClass = DestClass;
2580 const Type *StoreTy = DestTy;
2581 if (StoreClass == cByte || DestTy->isUnsigned())
2582 switch (StoreClass) {
2583 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
2584 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
2585 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
2586 // The following treatment of cLong may not be perfectly right,
2587 // but it survives chains of casts of the form
2588 // double->ulong->double.
2589 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
2590 default: assert(0 && "Unknown store class!");
2593 // Spill the integer to memory and reload it from there...
2595 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
2597 static const unsigned Op1[] =
2598 { 0, X86::FIST16m, X86::FIST32m, 0, X86::FISTP64m };
2599 addFrameReference(BuildMI(*BB, IP, Op1[StoreClass], 5),
2600 FrameIdx).addReg(SrcReg);
2602 if (DestClass == cLong) {
2603 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg), FrameIdx);
2604 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg+1),
2607 static const unsigned Op2[] = { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm };
2608 addFrameReference(BuildMI(*BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
2611 // Reload the original control word now...
2612 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
2616 // Anything we haven't handled already, we can't (yet) handle at all.
2617 assert(0 && "Unhandled cast instruction!");
2621 /// visitVANextInst - Implement the va_next instruction...
2623 void ISel::visitVANextInst(VANextInst &I) {
2624 unsigned VAList = getReg(I.getOperand(0));
2625 unsigned DestReg = getReg(I);
2628 switch (I.getArgType()->getPrimitiveID()) {
2631 assert(0 && "Error: bad type for va_next instruction!");
2633 case Type::PointerTyID:
2634 case Type::UIntTyID:
2638 case Type::ULongTyID:
2639 case Type::LongTyID:
2640 case Type::DoubleTyID:
2645 // Increment the VAList pointer...
2646 BuildMI(BB, X86::ADD32ri, 2, DestReg).addReg(VAList).addImm(Size);
2649 void ISel::visitVAArgInst(VAArgInst &I) {
2650 unsigned VAList = getReg(I.getOperand(0));
2651 unsigned DestReg = getReg(I);
2653 switch (I.getType()->getPrimitiveID()) {
2656 assert(0 && "Error: bad type for va_next instruction!");
2658 case Type::PointerTyID:
2659 case Type::UIntTyID:
2661 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
2663 case Type::ULongTyID:
2664 case Type::LongTyID:
2665 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
2666 addRegOffset(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), VAList, 4);
2668 case Type::DoubleTyID:
2669 addDirectMem(BuildMI(BB, X86::FLD64m, 4, DestReg), VAList);
2674 /// visitGetElementPtrInst - instruction-select GEP instructions
2676 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2677 // If this GEP instruction will be folded into all of its users, we don't need
2678 // to explicitly calculate it!
2679 unsigned A, B, C, D;
2680 if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) {
2681 // Check all of the users of the instruction to see if they are loads and
2683 bool AllWillFold = true;
2684 for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI)
2685 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Load)
2686 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Store ||
2687 cast<Instruction>(*UI)->getOperand(0) == &I) {
2688 AllWillFold = false;
2692 // If the instruction is foldable, and will be folded into all users, don't
2694 if (AllWillFold) return;
2697 unsigned outputReg = getReg(I);
2698 emitGEPOperation(BB, BB->end(), I.getOperand(0),
2699 I.op_begin()+1, I.op_end(), outputReg);
2702 /// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and
2703 /// GEPTypes (the derived types being stepped through at each level). On return
2704 /// from this function, if some indexes of the instruction are representable as
2705 /// an X86 lea instruction, the machine operands are put into the Ops
2706 /// instruction and the consumed indexes are poped from the GEPOps/GEPTypes
2707 /// lists. Otherwise, GEPOps.size() is returned. If this returns a an
2708 /// addressing mode that only partially consumes the input, the BaseReg input of
2709 /// the addressing mode must be left free.
2711 /// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
2713 void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
2714 std::vector<Value*> &GEPOps,
2715 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
2716 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
2717 const TargetData &TD = TM.getTargetData();
2719 // Clear out the state we are working with...
2720 BaseReg = 0; // No base register
2721 Scale = 1; // Unit scale
2722 IndexReg = 0; // No index register
2723 Disp = 0; // No displacement
2725 // While there are GEP indexes that can be folded into the current address,
2726 // keep processing them.
2727 while (!GEPTypes.empty()) {
2728 if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
2729 // It's a struct access. CUI is the index into the structure,
2730 // which names the field. This index must have unsigned type.
2731 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
2733 // Use the TargetData structure to pick out what the layout of the
2734 // structure is in memory. Since the structure index must be constant, we
2735 // can get its value and use it to find the right byte offset from the
2736 // StructLayout class's list of structure member offsets.
2737 Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
2738 GEPOps.pop_back(); // Consume a GEP operand
2739 GEPTypes.pop_back();
2741 // It's an array or pointer access: [ArraySize x ElementType].
2742 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2743 Value *idx = GEPOps.back();
2745 // idx is the index into the array. Unlike with structure
2746 // indices, we may not know its actual value at code-generation
2749 // If idx is a constant, fold it into the offset.
2750 unsigned TypeSize = TD.getTypeSize(SqTy->getElementType());
2751 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2752 Disp += TypeSize*CSI->getValue();
2753 } else if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(idx)) {
2754 Disp += TypeSize*CUI->getValue();
2756 // If the index reg is already taken, we can't handle this index.
2757 if (IndexReg) return;
2759 // If this is a size that we can handle, then add the index as
2761 case 1: case 2: case 4: case 8:
2762 // These are all acceptable scales on X86.
2766 // Otherwise, we can't handle this scale
2770 if (CastInst *CI = dyn_cast<CastInst>(idx))
2771 if (CI->getOperand(0)->getType() == Type::IntTy ||
2772 CI->getOperand(0)->getType() == Type::UIntTy)
2773 idx = CI->getOperand(0);
2775 IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
2778 GEPOps.pop_back(); // Consume a GEP operand
2779 GEPTypes.pop_back();
2783 // GEPTypes is empty, which means we have a single operand left. See if we
2784 // can set it as the base register.
2786 // FIXME: When addressing modes are more powerful/correct, we could load
2787 // global addresses directly as 32-bit immediates.
2788 assert(BaseReg == 0);
2789 BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
2790 GEPOps.pop_back(); // Consume the last GEP operand
2794 /// isGEPFoldable - Return true if the specified GEP can be completely
2795 /// folded into the addressing mode of a load/store or lea instruction.
2796 bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
2797 Value *Src, User::op_iterator IdxBegin,
2798 User::op_iterator IdxEnd, unsigned &BaseReg,
2799 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
2800 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2801 Src = CPR->getValue();
2803 std::vector<Value*> GEPOps;
2804 GEPOps.resize(IdxEnd-IdxBegin+1);
2806 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2808 std::vector<const Type*> GEPTypes;
2809 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2810 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2812 MachineBasicBlock::iterator IP;
2813 if (MBB) IP = MBB->end();
2814 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
2816 // We can fold it away iff the getGEPIndex call eliminated all operands.
2817 return GEPOps.empty();
2820 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2821 MachineBasicBlock::iterator IP,
2822 Value *Src, User::op_iterator IdxBegin,
2823 User::op_iterator IdxEnd, unsigned TargetReg) {
2824 const TargetData &TD = TM.getTargetData();
2825 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2826 Src = CPR->getValue();
2828 std::vector<Value*> GEPOps;
2829 GEPOps.resize(IdxEnd-IdxBegin+1);
2831 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2833 std::vector<const Type*> GEPTypes;
2834 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2835 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2837 // Keep emitting instructions until we consume the entire GEP instruction.
2838 while (!GEPOps.empty()) {
2839 unsigned OldSize = GEPOps.size();
2840 unsigned BaseReg, Scale, IndexReg, Disp;
2841 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
2843 if (GEPOps.size() != OldSize) {
2844 // getGEPIndex consumed some of the input. Build an LEA instruction here.
2845 unsigned NextTarget = 0;
2846 if (!GEPOps.empty()) {
2847 assert(BaseReg == 0 &&
2848 "getGEPIndex should have left the base register open for chaining!");
2849 NextTarget = BaseReg = makeAnotherReg(Type::UIntTy);
2852 if (IndexReg == 0 && Disp == 0)
2853 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
2855 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg),
2856 BaseReg, Scale, IndexReg, Disp);
2858 TargetReg = NextTarget;
2859 } else if (GEPTypes.empty()) {
2860 // The getGEPIndex operation didn't want to build an LEA. Check to see if
2861 // all operands are consumed but the base pointer. If so, just load it
2862 // into the register.
2863 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps[0])) {
2864 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addGlobalAddress(GV);
2866 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
2867 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
2869 break; // we are now done
2872 // It's an array or pointer access: [ArraySize x ElementType].
2873 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2874 Value *idx = GEPOps.back();
2875 GEPOps.pop_back(); // Consume a GEP operand
2876 GEPTypes.pop_back();
2878 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
2879 // operand on X86. Handle this case directly now...
2880 if (CastInst *CI = dyn_cast<CastInst>(idx))
2881 if (CI->getOperand(0)->getType() == Type::IntTy ||
2882 CI->getOperand(0)->getType() == Type::UIntTy)
2883 idx = CI->getOperand(0);
2885 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2886 // must find the size of the pointed-to type (Not coincidentally, the next
2887 // type is the type of the elements in the array).
2888 const Type *ElTy = SqTy->getElementType();
2889 unsigned elementSize = TD.getTypeSize(ElTy);
2891 // If idxReg is a constant, we don't need to perform the multiply!
2892 if (ConstantInt *CSI = dyn_cast<ConstantInt>(idx)) {
2893 if (!CSI->isNullValue()) {
2894 unsigned Offset = elementSize*CSI->getRawValue();
2895 unsigned Reg = makeAnotherReg(Type::UIntTy);
2896 BuildMI(*MBB, IP, X86::ADD32ri, 2, TargetReg)
2897 .addReg(Reg).addImm(Offset);
2898 --IP; // Insert the next instruction before this one.
2899 TargetReg = Reg; // Codegen the rest of the GEP into this
2901 } else if (elementSize == 1) {
2902 // If the element size is 1, we don't have to multiply, just add
2903 unsigned idxReg = getReg(idx, MBB, IP);
2904 unsigned Reg = makeAnotherReg(Type::UIntTy);
2905 BuildMI(*MBB, IP, X86::ADD32rr, 2,TargetReg).addReg(Reg).addReg(idxReg);
2906 --IP; // Insert the next instruction before this one.
2907 TargetReg = Reg; // Codegen the rest of the GEP into this
2909 unsigned idxReg = getReg(idx, MBB, IP);
2910 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2912 // Make sure we can back the iterator up to point to the first
2913 // instruction emitted.
2914 MachineBasicBlock::iterator BeforeIt = IP;
2915 if (IP == MBB->begin())
2916 BeforeIt = MBB->end();
2919 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2921 // Emit an ADD to add OffsetReg to the basePtr.
2922 unsigned Reg = makeAnotherReg(Type::UIntTy);
2923 BuildMI(*MBB, IP, X86::ADD32rr, 2, TargetReg)
2924 .addReg(Reg).addReg(OffsetReg);
2926 // Step to the first instruction of the multiply.
2927 if (BeforeIt == MBB->end())
2932 TargetReg = Reg; // Codegen the rest of the GEP into this
2939 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2940 /// frame manager, otherwise do it the hard way.
2942 void ISel::visitAllocaInst(AllocaInst &I) {
2943 // Find the data size of the alloca inst's getAllocatedType.
2944 const Type *Ty = I.getAllocatedType();
2945 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2947 // If this is a fixed size alloca in the entry block for the function,
2948 // statically stack allocate the space.
2950 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2951 if (I.getParent() == I.getParent()->getParent()->begin()) {
2952 TySize *= CUI->getValue(); // Get total allocated size...
2953 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2955 // Create a new stack object using the frame manager...
2956 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2957 addFrameReference(BuildMI(BB, X86::LEA32r, 5, getReg(I)), FrameIdx);
2962 // Create a register to hold the temporary result of multiplying the type size
2963 // constant by the variable amount.
2964 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2965 unsigned SrcReg1 = getReg(I.getArraySize());
2967 // TotalSizeReg = mul <numelements>, <TypeSize>
2968 MachineBasicBlock::iterator MBBI = BB->end();
2969 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2971 // AddedSize = add <TotalSizeReg>, 15
2972 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2973 BuildMI(BB, X86::ADD32ri, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
2975 // AlignedSize = and <AddedSize>, ~15
2976 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2977 BuildMI(BB, X86::AND32ri, 2, AlignedSize).addReg(AddedSizeReg).addImm(~15);
2979 // Subtract size from stack pointer, thereby allocating some space.
2980 BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2982 // Put a pointer to the space into the result register, by copying
2983 // the stack pointer.
2984 BuildMI(BB, X86::MOV32rr, 1, getReg(I)).addReg(X86::ESP);
2986 // Inform the Frame Information that we have just allocated a variable-sized
2988 F->getFrameInfo()->CreateVariableSizedObject();
2991 /// visitMallocInst - Malloc instructions are code generated into direct calls
2992 /// to the library malloc.
2994 void ISel::visitMallocInst(MallocInst &I) {
2995 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2998 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2999 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
3001 Arg = makeAnotherReg(Type::UIntTy);
3002 unsigned Op0Reg = getReg(I.getOperand(0));
3003 MachineBasicBlock::iterator MBBI = BB->end();
3004 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
3007 std::vector<ValueRecord> Args;
3008 Args.push_back(ValueRecord(Arg, Type::UIntTy));
3009 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
3010 1).addExternalSymbol("malloc", true);
3011 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
3015 /// visitFreeInst - Free instructions are code gen'd to call the free libc
3018 void ISel::visitFreeInst(FreeInst &I) {
3019 std::vector<ValueRecord> Args;
3020 Args.push_back(ValueRecord(I.getOperand(0)));
3021 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
3022 1).addExternalSymbol("free", true);
3023 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
3026 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
3027 /// into a machine code representation is a very simple peep-hole fashion. The
3028 /// generated code sucks but the implementation is nice and simple.
3030 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
3031 return new ISel(TM);