1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Support/InstVisitor.h"
23 #include "llvm/Target/MRegisterInfo.h"
26 using namespace MOTy; // Get Use, Def, UseAndDef
29 struct ISel : public FunctionPass, InstVisitor<ISel> {
31 MachineFunction *F; // The function we are compiling into
32 MachineBasicBlock *BB; // The current MBB we are compiling
35 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
37 ISel(TargetMachine &tm)
38 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
40 /// runOnFunction - Top level implementation of instruction selection for
41 /// the entire function.
43 bool runOnFunction(Function &Fn) {
44 F = &MachineFunction::construct(&Fn, TM);
47 CurReg = MRegisterInfo::FirstVirtualRegister;
49 return false; // We never modify the LLVM itself.
52 /// visitBasicBlock - This method is called when we are visiting a new basic
53 /// block. This simply creates a new MachineBasicBlock to emit code into
54 /// and adds it to the current MachineFunction. Subsequent visit* for
55 /// instructions will be invoked for all instructions in the basic block.
57 void visitBasicBlock(BasicBlock &LLVM_BB) {
58 BB = new MachineBasicBlock(&LLVM_BB);
59 // FIXME: Use the auto-insert form when it's available
60 F->getBasicBlockList().push_back(BB);
63 // Visitation methods for various instructions. These methods simply emit
64 // fixed X86 code for each instruction.
67 // Control flow operators
68 void visitReturnInst(ReturnInst &RI);
69 void visitBranchInst(BranchInst &BI);
70 void visitCallInst(CallInst &I);
72 // Arithmetic operators
73 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
74 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
75 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
76 void visitMul(BinaryOperator &B);
78 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
79 void visitRem(BinaryOperator &B) { visitDivRem(B); }
80 void visitDivRem(BinaryOperator &B);
83 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
84 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
85 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
87 // Binary comparison operators
88 void visitSetCCInst(SetCondInst &I, unsigned OpNum);
89 void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
90 void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
91 void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
92 void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
93 void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
94 void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
96 // Memory Instructions
97 void visitLoadInst(LoadInst &I);
98 void visitStoreInst(StoreInst &I);
101 void visitShiftInst(ShiftInst &I);
102 void visitPHINode(PHINode &I);
103 void visitCastInst(CastInst &I);
105 void visitInstruction(Instruction &I) {
106 std::cerr << "Cannot instruction select: " << I;
111 /// copyConstantToRegister - Output the instructions required to put the
112 /// specified constant into the specified register.
114 void copyConstantToRegister(Constant *C, unsigned Reg);
116 /// getReg - This method turns an LLVM value into a register number. This
117 /// is guaranteed to produce the same register number for a particular value
118 /// every time it is queried.
120 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
121 unsigned getReg(Value *V) {
122 unsigned &Reg = RegMap[V];
127 // Add the mapping of regnumber => reg class to MachineFunction
129 TM.getRegisterInfo()->getRegClassForType(V->getType()));
132 // If this operand is a constant, emit the code to copy the constant into
133 // the register here...
135 if (Constant *C = dyn_cast<Constant>(V))
136 copyConstantToRegister(C, Reg);
143 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
147 cByte, cShort, cInt, cLong, cFloat, cDouble
150 /// getClass - Turn a primitive type into a "class" number which is based on the
151 /// size of the type, and whether or not it is floating point.
153 static inline TypeClass getClass(const Type *Ty) {
154 switch (Ty->getPrimitiveID()) {
155 case Type::SByteTyID:
156 case Type::UByteTyID: return cByte; // Byte operands are class #0
157 case Type::ShortTyID:
158 case Type::UShortTyID: return cShort; // Short operands are class #1
161 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
164 case Type::ULongTyID: return cLong; // Longs are class #3
165 case Type::FloatTyID: return cFloat; // Float is class #4
166 case Type::DoubleTyID: return cDouble; // Doubles are class #5
168 assert(0 && "Invalid type to getClass!");
169 return cByte; // not reached
174 /// copyConstantToRegister - Output the instructions required to put the
175 /// specified constant into the specified register.
177 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
178 assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
180 if (C->getType()->isIntegral()) {
181 unsigned Class = getClass(C->getType());
182 assert(Class != 3 && "Type not handled yet!");
184 static const unsigned IntegralOpcodeTab[] = {
185 X86::MOVir8, X86::MOVir16, X86::MOVir32
188 if (C->getType()->isSigned()) {
189 ConstantSInt *CSI = cast<ConstantSInt>(C);
190 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
192 ConstantUInt *CUI = cast<ConstantUInt>(C);
193 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
196 assert(0 && "Type not handled yet!");
201 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
202 /// register, then move it to wherever the result should be.
203 /// We handle FP setcc instructions by pushing them, doing a
204 /// compare-and-pop-twice, and then copying the concodes to the main
205 /// processor's concodes (I didn't make this up, it's in the Intel manual)
207 void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
208 // The arguments are already supposed to be of the same type.
209 const Type *CompTy = I.getOperand(0)->getType();
210 unsigned reg1 = getReg(I.getOperand(0));
211 unsigned reg2 = getReg(I.getOperand(1));
213 unsigned Class = getClass(CompTy);
215 // Emit: cmp <var1>, <var2> (do the comparison). We can
216 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
219 BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
222 BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
225 BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
228 // Push the variables on the stack with fldl opcodes.
229 // FIXME: assuming var1, var2 are in memory, if not, spill to
231 case cFloat: // Floats
232 BuildMI (BB, X86::FLDr4, 1).addReg (reg1);
233 BuildMI (BB, X86::FLDr4, 1).addReg (reg2);
235 case cDouble: // Doubles
236 BuildMI (BB, X86::FLDr8, 1).addReg (reg1);
237 BuildMI (BB, X86::FLDr8, 1).addReg (reg2);
244 if (CompTy->isFloatingPoint()) {
245 // (Non-trapping) compare and pop twice.
246 BuildMI (BB, X86::FUCOMPP, 0);
247 // Move fp status word (concodes) to ax.
248 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
249 // Load real concodes from ax.
250 BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
253 // Emit setOp instruction (extract concode; clobbers ax),
254 // using the following mapping:
255 // LLVM -> X86 signed X86 unsigned
257 // seteq -> sete sete
258 // setne -> setne setne
259 // setlt -> setl setb
260 // setgt -> setg seta
261 // setle -> setle setbe
262 // setge -> setge setae
264 static const unsigned OpcodeTab[2][6] = {
265 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
266 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
269 BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
271 // Put it in the result using a move.
272 BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
276 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
277 /// we have the following possibilities:
279 /// ret void: No return value, simply emit a 'ret' instruction
280 /// ret sbyte, ubyte : Extend value into EAX and return
281 /// ret short, ushort: Extend value into EAX and return
282 /// ret int, uint : Move value into EAX and return
283 /// ret pointer : Move value into EAX and return
284 /// ret long, ulong : Move value into EAX/EDX and return
285 /// ret float/double : Top of FP stack
287 void ISel::visitReturnInst (ReturnInst &I) {
288 if (I.getNumOperands() == 0) {
289 // Emit a 'ret' instruction
290 BuildMI(BB, X86::RET, 0);
294 unsigned val = getReg(I.getOperand(0));
295 unsigned Class = getClass(I.getOperand(0)->getType());
296 bool isUnsigned = I.getOperand(0)->getType()->isUnsigned();
299 // ret sbyte, ubyte: Extend value into EAX and return
301 BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
303 BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
306 // ret short, ushort: Extend value into EAX and return
308 BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
310 BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
313 // ret int, uint, ptr: Move value into EAX and return
315 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val);
318 // ret float/double: top of FP stack
320 case cFloat: // Floats
321 BuildMI(BB, X86::FLDr4, 1).addReg(val);
323 case cDouble: // Doubles
324 BuildMI(BB, X86::FLDr8, 1).addReg(val);
327 // ret long: use EAX(least significant 32 bits)/EDX (most
328 // significant 32)...uh, I think so Brain, but how do i call
329 // up the two parts of the value from inside this mouse
335 // Emit a 'ret' instruction
336 BuildMI(BB, X86::RET, 0);
339 /// visitBranchInst - Handle conditional and unconditional branches here. Note
340 /// that since code layout is frozen at this point, that if we are trying to
341 /// jump to a block that is the immediate successor of the current block, we can
342 /// just make a fall-through. (but we don't currently).
345 ISel::visitBranchInst (BranchInst & BI)
347 if (BI.isConditional ())
349 BasicBlock *ifTrue = BI.getSuccessor (0);
350 BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
352 // simplest thing I can think of: compare condition with zero,
353 // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
355 unsigned int condReg = getReg (BI.getCondition ());
356 BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
357 BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
358 BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
360 else // unconditional branch
362 BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
367 ISel::visitCallInst (CallInst &CI)
369 visitInstruction (CI);
372 /// visitSimpleBinary - Implement simple binary operators for integral types...
373 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
376 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
377 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
380 unsigned Class = getClass(B.getType());
381 if (Class > 2) // FIXME: Handle longs
384 static const unsigned OpcodeTab[][4] = {
385 // Arithmetic operators
386 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
387 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
390 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
391 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
392 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
395 unsigned Opcode = OpcodeTab[OperatorClass][Class];
396 unsigned Op0r = getReg(B.getOperand(0));
397 unsigned Op1r = getReg(B.getOperand(1));
398 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
401 /// visitMul - Multiplies are not simple binary operators because they must deal
402 /// with the EAX register explicitly.
404 void ISel::visitMul(BinaryOperator &I) {
405 unsigned Class = getClass(I.getType());
406 if (Class > 2) // FIXME: Handle longs
409 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
410 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
411 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
413 unsigned Reg = Regs[Class];
414 unsigned Op0Reg = getReg(I.getOperand(0));
415 unsigned Op1Reg = getReg(I.getOperand(1));
417 // Put the first operand into one of the A registers...
418 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
420 // Emit the appropriate multiply instruction...
421 BuildMI(BB, MulOpcode[Class], 1).addReg(Op1Reg);
423 // Put the result into the destination register...
424 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
428 /// visitDivRem - Handle division and remainder instructions... these
429 /// instruction both require the same instructions to be generated, they just
430 /// select the result from a different register. Note that both of these
431 /// instructions work differently for signed and unsigned operands.
433 void ISel::visitDivRem(BinaryOperator &I) {
434 unsigned Class = getClass(I.getType());
435 if (Class > 2) // FIXME: Handle longs
438 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
439 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
440 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
441 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
442 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
444 static const unsigned DivOpcode[][4] = {
445 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
446 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
449 bool isSigned = I.getType()->isSigned();
450 unsigned Reg = Regs[Class];
451 unsigned ExtReg = ExtRegs[Class];
452 unsigned Op0Reg = getReg(I.getOperand(0));
453 unsigned Op1Reg = getReg(I.getOperand(1));
455 // Put the first operand into one of the A registers...
456 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
459 // Emit a sign extension instruction...
460 BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
462 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
463 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
466 // Emit the appropriate divide or remainder instruction...
467 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
469 // Figure out which register we want to pick the result out of...
470 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
472 // Put the result into the destination register...
473 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
477 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
478 /// for constant immediate shift values, and for constant immediate
479 /// shift values equal to 1. Even the general case is sort of special,
480 /// because the shift amount has to be in CL, not just any old register.
482 void ISel::visitShiftInst (ShiftInst &I) {
483 unsigned Op0r = getReg (I.getOperand(0));
484 unsigned DestReg = getReg(I);
485 bool isLeftShift = I.getOpcode() == Instruction::Shl;
486 bool isOperandSigned = I.getType()->isUnsigned();
487 unsigned OperandClass = getClass(I.getType());
489 if (OperandClass > 2)
490 visitInstruction(I); // Can't handle longs yet!
492 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
494 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
495 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
496 unsigned char shAmt = CUI->getValue();
498 static const unsigned ConstantOperand[][4] = {
499 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
500 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
501 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
502 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
505 const unsigned *OpTab = // Figure out the operand table to use
506 ConstantOperand[isLeftShift*2+isOperandSigned];
508 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
509 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
513 // The shift amount is non-constant.
515 // In fact, you can only shift with a variable shift amount if
516 // that amount is already in the CL register, so we have to put it
520 // Emit: move cl, shiftAmount (put the shift amount in CL.)
521 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
523 // This is a shift right (SHR).
524 static const unsigned NonConstantOperand[][4] = {
525 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
526 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
527 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
528 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
531 const unsigned *OpTab = // Figure out the operand table to use
532 NonConstantOperand[isLeftShift*2+isOperandSigned];
534 BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
539 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
542 void ISel::visitLoadInst(LoadInst &I) {
543 unsigned Class = getClass(I.getType());
544 if (Class > 2) // FIXME: Handle longs and others...
547 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
549 unsigned AddressReg = getReg(I.getOperand(0));
550 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
554 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
557 void ISel::visitStoreInst(StoreInst &I) {
558 unsigned Class = getClass(I.getOperand(0)->getType());
559 if (Class > 2) // FIXME: Handle longs and others...
562 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
564 unsigned ValReg = getReg(I.getOperand(0));
565 unsigned AddressReg = getReg(I.getOperand(1));
566 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
570 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
572 void ISel::visitPHINode(PHINode &PN) {
573 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
575 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
576 // FIXME: This will put constants after the PHI nodes in the block, which
577 // is invalid. They should be put inline into the PHI node eventually.
579 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
580 MI->addPCDispOperand(PN.getIncomingBlock(i));
585 ISel::visitCastInst (CastInst &CI)
587 visitInstruction (CI);
590 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
591 /// into a machine code representation is a very simple peep-hole fashion. The
592 /// generated code sucks but the implementation is nice and simple.
594 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {