1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/Pass.h"
22 #include "llvm/CodeGen/IntrinsicLowering.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/GetElementPtrTypeIterator.h"
30 #include "llvm/Support/InstVisitor.h"
31 #include "Support/Statistic.h"
36 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
38 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
42 cByte, cShort, cInt, cFP, cLong
46 /// getClass - Turn a primitive type into a "class" number which is based on the
47 /// size of the type, and whether or not it is floating point.
49 static inline TypeClass getClass(const Type *Ty) {
50 switch (Ty->getTypeID()) {
52 case Type::UByteTyID: return cByte; // Byte operands are class #0
54 case Type::UShortTyID: return cShort; // Short operands are class #1
57 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
60 case Type::DoubleTyID: return cFP; // Floating Point is #3
63 case Type::ULongTyID: return cLong; // Longs are class #4
65 assert(0 && "Invalid type to getClass!");
66 return cByte; // not reached
70 // getClassB - Just like getClass, but treat boolean values as bytes.
71 static inline TypeClass getClassB(const Type *Ty) {
72 if (Ty == Type::BoolTy) return cByte;
77 struct ISel : public FunctionPass, InstVisitor<ISel> {
79 MachineFunction *F; // The function we are compiling into
80 MachineBasicBlock *BB; // The current MBB we are compiling
81 int VarArgsFrameIndex; // FrameIndex for start of varargs area
82 int ReturnAddressIndex; // FrameIndex for the return address
84 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
86 // MBBMap - Mapping between LLVM BB -> Machine BB
87 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
89 // AllocaMap - Mapping from fixed sized alloca instructions to the
90 // FrameIndex for the alloca.
91 std::map<AllocaInst*, unsigned> AllocaMap;
93 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
95 /// runOnFunction - Top level implementation of instruction selection for
96 /// the entire function.
98 bool runOnFunction(Function &Fn) {
99 // First pass over the function, lower any unknown intrinsic functions
100 // with the IntrinsicLowering class.
101 LowerUnknownIntrinsicFunctionCalls(Fn);
103 F = &MachineFunction::construct(&Fn, TM);
105 // Create all of the machine basic blocks for the function...
106 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
107 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
111 // Set up a frame object for the return address. This is used by the
112 // llvm.returnaddress & llvm.frameaddress intrinisics.
113 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
115 // Copy incoming arguments off of the stack...
116 LoadArgumentsToVirtualRegs(Fn);
118 // Instruction select everything except PHI nodes
121 // Select the PHI nodes
124 // Insert the FP_REG_KILL instructions into blocks that need them.
131 // We always build a machine code representation for the function
135 virtual const char *getPassName() const {
136 return "X86 Simple Instruction Selection";
139 /// visitBasicBlock - This method is called when we are visiting a new basic
140 /// block. This simply creates a new MachineBasicBlock to emit code into
141 /// and adds it to the current MachineFunction. Subsequent visit* for
142 /// instructions will be invoked for all instructions in the basic block.
144 void visitBasicBlock(BasicBlock &LLVM_BB) {
145 BB = MBBMap[&LLVM_BB];
148 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
149 /// function, lowering any calls to unknown intrinsic functions into the
150 /// equivalent LLVM code.
152 void LowerUnknownIntrinsicFunctionCalls(Function &F);
154 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
155 /// from the stack into virtual registers.
157 void LoadArgumentsToVirtualRegs(Function &F);
159 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
160 /// because we have to generate our sources into the source basic blocks,
161 /// not the current one.
163 void SelectPHINodes();
165 /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks
166 /// that need them. This only occurs due to the floating point stackifier
167 /// not being aggressive enough to handle arbitrary global stackification.
169 void InsertFPRegKills();
171 // Visitation methods for various instructions. These methods simply emit
172 // fixed X86 code for each instruction.
175 // Control flow operators
176 void visitReturnInst(ReturnInst &RI);
177 void visitBranchInst(BranchInst &BI);
183 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
184 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
186 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
187 const std::vector<ValueRecord> &Args);
188 void visitCallInst(CallInst &I);
189 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
191 // Arithmetic operators
192 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
193 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
194 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
195 void visitMul(BinaryOperator &B);
197 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
198 void visitRem(BinaryOperator &B) { visitDivRem(B); }
199 void visitDivRem(BinaryOperator &B);
202 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
203 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
204 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
206 // Comparison operators...
207 void visitSetCondInst(SetCondInst &I);
208 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
209 MachineBasicBlock *MBB,
210 MachineBasicBlock::iterator MBBI);
211 void visitSelectInst(SelectInst &SI);
214 // Memory Instructions
215 void visitLoadInst(LoadInst &I);
216 void visitStoreInst(StoreInst &I);
217 void visitGetElementPtrInst(GetElementPtrInst &I);
218 void visitAllocaInst(AllocaInst &I);
219 void visitMallocInst(MallocInst &I);
220 void visitFreeInst(FreeInst &I);
223 void visitShiftInst(ShiftInst &I);
224 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
225 void visitCastInst(CastInst &I);
226 void visitVANextInst(VANextInst &I);
227 void visitVAArgInst(VAArgInst &I);
229 void visitInstruction(Instruction &I) {
230 std::cerr << "Cannot instruction select: " << I;
234 /// promote32 - Make a value 32-bits wide, and put it somewhere.
236 void promote32(unsigned targetReg, const ValueRecord &VR);
238 /// getAddressingMode - Get the addressing mode to use to address the
239 /// specified value. The returned value should be used with addFullAddress.
240 void getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
241 unsigned &IndexReg, unsigned &Disp);
244 /// getGEPIndex - This is used to fold GEP instructions into X86 addressing
246 void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
247 std::vector<Value*> &GEPOps,
248 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
249 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
251 /// isGEPFoldable - Return true if the specified GEP can be completely
252 /// folded into the addressing mode of a load/store or lea instruction.
253 bool isGEPFoldable(MachineBasicBlock *MBB,
254 Value *Src, User::op_iterator IdxBegin,
255 User::op_iterator IdxEnd, unsigned &BaseReg,
256 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
258 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
259 /// constant expression GEP support.
261 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
262 Value *Src, User::op_iterator IdxBegin,
263 User::op_iterator IdxEnd, unsigned TargetReg);
265 /// emitCastOperation - Common code shared between visitCastInst and
266 /// constant expression cast support.
268 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
269 Value *Src, const Type *DestTy, unsigned TargetReg);
271 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
272 /// and constant expression support.
274 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
275 MachineBasicBlock::iterator IP,
276 Value *Op0, Value *Op1,
277 unsigned OperatorClass, unsigned TargetReg);
279 /// emitBinaryFPOperation - This method handles emission of floating point
280 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
281 void emitBinaryFPOperation(MachineBasicBlock *BB,
282 MachineBasicBlock::iterator IP,
283 Value *Op0, Value *Op1,
284 unsigned OperatorClass, unsigned TargetReg);
286 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
287 Value *Op0, Value *Op1, unsigned TargetReg);
289 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
290 unsigned DestReg, const Type *DestTy,
291 unsigned Op0Reg, unsigned Op1Reg);
292 void doMultiplyConst(MachineBasicBlock *MBB,
293 MachineBasicBlock::iterator MBBI,
294 unsigned DestReg, const Type *DestTy,
295 unsigned Op0Reg, unsigned Op1Val);
297 void emitDivRemOperation(MachineBasicBlock *BB,
298 MachineBasicBlock::iterator IP,
299 Value *Op0, Value *Op1, bool isDiv,
302 /// emitSetCCOperation - Common code shared between visitSetCondInst and
303 /// constant expression support.
305 void emitSetCCOperation(MachineBasicBlock *BB,
306 MachineBasicBlock::iterator IP,
307 Value *Op0, Value *Op1, unsigned Opcode,
310 /// emitShiftOperation - Common code shared between visitShiftInst and
311 /// constant expression support.
313 void emitShiftOperation(MachineBasicBlock *MBB,
314 MachineBasicBlock::iterator IP,
315 Value *Op, Value *ShiftAmount, bool isLeftShift,
316 const Type *ResultTy, unsigned DestReg);
318 /// emitSelectOperation - Common code shared between visitSelectInst and the
319 /// constant expression support.
320 void emitSelectOperation(MachineBasicBlock *MBB,
321 MachineBasicBlock::iterator IP,
322 Value *Cond, Value *TrueVal, Value *FalseVal,
325 /// copyConstantToRegister - Output the instructions required to put the
326 /// specified constant into the specified register.
328 void copyConstantToRegister(MachineBasicBlock *MBB,
329 MachineBasicBlock::iterator MBBI,
330 Constant *C, unsigned Reg);
332 void emitUCOMr(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
333 unsigned LHS, unsigned RHS);
335 /// makeAnotherReg - This method returns the next register number we haven't
338 /// Long values are handled somewhat specially. They are always allocated
339 /// as pairs of 32 bit integer values. The register number returned is the
340 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
341 /// of the long value.
343 unsigned makeAnotherReg(const Type *Ty) {
344 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
345 "Current target doesn't have X86 reg info??");
346 const X86RegisterInfo *MRI =
347 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
348 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
349 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
350 // Create the lower part
351 F->getSSARegMap()->createVirtualRegister(RC);
352 // Create the upper part.
353 return F->getSSARegMap()->createVirtualRegister(RC)-1;
356 // Add the mapping of regnumber => reg class to MachineFunction
357 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
358 return F->getSSARegMap()->createVirtualRegister(RC);
361 /// getReg - This method turns an LLVM value into a register number.
363 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
364 unsigned getReg(Value *V) {
365 // Just append to the end of the current bb.
366 MachineBasicBlock::iterator It = BB->end();
367 return getReg(V, BB, It);
369 unsigned getReg(Value *V, MachineBasicBlock *MBB,
370 MachineBasicBlock::iterator IPt);
372 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
373 /// that is to be statically allocated with the initial stack frame
375 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
379 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
380 /// instruction in the entry block, return it. Otherwise, return a null
382 static AllocaInst *dyn_castFixedAlloca(Value *V) {
383 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
384 BasicBlock *BB = AI->getParent();
385 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
391 /// getReg - This method turns an LLVM value into a register number.
393 unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
394 MachineBasicBlock::iterator IPt) {
395 // If this operand is a constant, emit the code to copy the constant into
396 // the register here...
397 if (Constant *C = dyn_cast<Constant>(V)) {
398 unsigned Reg = makeAnotherReg(V->getType());
399 copyConstantToRegister(MBB, IPt, C, Reg);
401 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
402 // Do not emit noop casts at all, unless it's a double -> float cast.
403 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()) &&
404 (CI->getType() != Type::FloatTy ||
405 CI->getOperand(0)->getType() != Type::DoubleTy))
406 return getReg(CI->getOperand(0), MBB, IPt);
407 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
408 // If the alloca address couldn't be folded into the instruction addressing,
409 // emit an explicit LEA as appropriate.
410 unsigned Reg = makeAnotherReg(V->getType());
411 unsigned FI = getFixedSizedAllocaFI(AI);
412 addFrameReference(BuildMI(*MBB, IPt, X86::LEA32r, 4, Reg), FI);
416 unsigned &Reg = RegMap[V];
418 Reg = makeAnotherReg(V->getType());
425 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
426 /// that is to be statically allocated with the initial stack frame
428 unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
429 // Already computed this?
430 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
431 if (I != AllocaMap.end() && I->first == AI) return I->second;
433 const Type *Ty = AI->getAllocatedType();
434 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
435 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
436 TySize *= CUI->getValue(); // Get total allocated size...
437 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
439 // Create a new stack object using the frame manager...
440 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
441 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
446 /// copyConstantToRegister - Output the instructions required to put the
447 /// specified constant into the specified register.
449 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
450 MachineBasicBlock::iterator IP,
451 Constant *C, unsigned R) {
452 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
454 switch (CE->getOpcode()) {
455 case Instruction::GetElementPtr:
456 emitGEPOperation(MBB, IP, CE->getOperand(0),
457 CE->op_begin()+1, CE->op_end(), R);
459 case Instruction::Cast:
460 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
463 case Instruction::Xor: ++Class; // FALL THROUGH
464 case Instruction::Or: ++Class; // FALL THROUGH
465 case Instruction::And: ++Class; // FALL THROUGH
466 case Instruction::Sub: ++Class; // FALL THROUGH
467 case Instruction::Add:
468 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
472 case Instruction::Mul:
473 emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
476 case Instruction::Div:
477 case Instruction::Rem:
478 emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
479 CE->getOpcode() == Instruction::Div, R);
482 case Instruction::SetNE:
483 case Instruction::SetEQ:
484 case Instruction::SetLT:
485 case Instruction::SetGT:
486 case Instruction::SetLE:
487 case Instruction::SetGE:
488 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
492 case Instruction::Shl:
493 case Instruction::Shr:
494 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
495 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
498 case Instruction::Select:
499 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
500 CE->getOperand(2), R);
504 std::cerr << "Offending expr: " << *C << "\n";
505 assert(0 && "Constant expression not yet handled!\n");
509 if (C->getType()->isIntegral()) {
510 unsigned Class = getClassB(C->getType());
512 if (Class == cLong) {
513 // Copy the value into the register pair.
514 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
515 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(Val & 0xFFFFFFFF);
516 BuildMI(*MBB, IP, X86::MOV32ri, 1, R+1).addImm(Val >> 32);
520 assert(Class <= cInt && "Type not handled yet!");
522 static const unsigned IntegralOpcodeTab[] = {
523 X86::MOV8ri, X86::MOV16ri, X86::MOV32ri
526 if (C->getType() == Type::BoolTy) {
527 BuildMI(*MBB, IP, X86::MOV8ri, 1, R).addImm(C == ConstantBool::True);
529 ConstantInt *CI = cast<ConstantInt>(C);
530 BuildMI(*MBB, IP, IntegralOpcodeTab[Class],1,R).addImm(CI->getRawValue());
532 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
533 if (CFP->isExactlyValue(+0.0))
534 BuildMI(*MBB, IP, X86::FLD0, 0, R);
535 else if (CFP->isExactlyValue(+1.0))
536 BuildMI(*MBB, IP, X86::FLD1, 0, R);
538 // Otherwise we need to spill the constant to memory...
539 MachineConstantPool *CP = F->getConstantPool();
540 unsigned CPI = CP->getConstantPoolIndex(CFP);
541 const Type *Ty = CFP->getType();
543 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
544 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLD32m : X86::FLD64m;
545 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 4, R), CPI);
548 } else if (isa<ConstantPointerNull>(C)) {
549 // Copy zero (null pointer) to the register.
550 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(0);
551 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
552 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addGlobalAddress(GV);
554 std::cerr << "Offending constant: " << *C << "\n";
555 assert(0 && "Type not handled yet!");
559 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
560 /// the stack into virtual registers.
562 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
563 // Emit instructions to load the arguments... On entry to a function on the
564 // X86, the stack frame looks like this:
566 // [ESP] -- return address
567 // [ESP + 4] -- first argument (leftmost lexically)
568 // [ESP + 8] -- second argument, if first argument is four bytes in size
571 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
572 MachineFrameInfo *MFI = F->getFrameInfo();
574 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
575 bool ArgLive = !I->use_empty();
576 unsigned Reg = ArgLive ? getReg(*I) : 0;
577 int FI; // Frame object index
579 switch (getClassB(I->getType())) {
582 FI = MFI->CreateFixedObject(1, ArgOffset);
583 addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Reg), FI);
588 FI = MFI->CreateFixedObject(2, ArgOffset);
589 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Reg), FI);
594 FI = MFI->CreateFixedObject(4, ArgOffset);
595 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
600 FI = MFI->CreateFixedObject(8, ArgOffset);
601 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
602 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg+1), FI, 4);
604 ArgOffset += 4; // longs require 4 additional bytes
609 if (I->getType() == Type::FloatTy) {
610 Opcode = X86::FLD32m;
611 FI = MFI->CreateFixedObject(4, ArgOffset);
613 Opcode = X86::FLD64m;
614 FI = MFI->CreateFixedObject(8, ArgOffset);
616 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
618 if (I->getType() == Type::DoubleTy)
619 ArgOffset += 4; // doubles require 4 additional bytes
622 assert(0 && "Unhandled argument type!");
624 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
627 // If the function takes variable number of arguments, add a frame offset for
628 // the start of the first vararg value... this is used to expand
630 if (Fn.getFunctionType()->isVarArg())
631 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
635 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
636 /// because we have to generate our sources into the source basic blocks, not
639 void ISel::SelectPHINodes() {
640 const TargetInstrInfo &TII = *TM.getInstrInfo();
641 const Function &LF = *F->getFunction(); // The LLVM function...
642 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
643 const BasicBlock *BB = I;
644 MachineBasicBlock &MBB = *MBBMap[I];
646 // Loop over all of the PHI nodes in the LLVM basic block...
647 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
648 for (BasicBlock::const_iterator I = BB->begin();
649 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
651 // Create a new machine instr PHI node, and insert it.
652 unsigned PHIReg = getReg(*PN);
653 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
654 X86::PHI, PN->getNumOperands(), PHIReg);
656 MachineInstr *LongPhiMI = 0;
657 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
658 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
659 X86::PHI, PN->getNumOperands(), PHIReg+1);
661 // PHIValues - Map of blocks to incoming virtual registers. We use this
662 // so that we only initialize one incoming value for a particular block,
663 // even if the block has multiple entries in the PHI node.
665 std::map<MachineBasicBlock*, unsigned> PHIValues;
667 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
668 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
670 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
671 PHIValues.lower_bound(PredMBB);
673 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
674 // We already inserted an initialization of the register for this
675 // predecessor. Recycle it.
676 ValReg = EntryIt->second;
679 // Get the incoming value into a virtual register.
681 Value *Val = PN->getIncomingValue(i);
683 // If this is a constant or GlobalValue, we may have to insert code
684 // into the basic block to compute it into a virtual register.
685 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val))) {
686 // Simple constants get emitted at the end of the basic block,
687 // before any terminator instructions. We "know" that the code to
688 // move a constant into a register will never clobber any flags.
689 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
691 // Because we don't want to clobber any values which might be in
692 // physical registers with the computation of this constant (which
693 // might be arbitrarily complex if it is a constant expression),
694 // just insert the computation at the top of the basic block.
695 MachineBasicBlock::iterator PI = PredMBB->begin();
697 // Skip over any PHI nodes though!
698 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
701 ValReg = getReg(Val, PredMBB, PI);
704 // Remember that we inserted a value for this PHI for this predecessor
705 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
708 PhiMI->addRegOperand(ValReg);
709 PhiMI->addMachineBasicBlockOperand(PredMBB);
711 LongPhiMI->addRegOperand(ValReg+1);
712 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
716 // Now that we emitted all of the incoming values for the PHI node, make
717 // sure to reposition the InsertPoint after the PHI that we just added.
718 // This is needed because we might have inserted a constant into this
719 // block, right after the PHI's which is before the old insert point!
720 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
726 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
727 /// compensation code on critical edges. As such, it requires that we kill all
728 /// FP registers on the exit from any blocks that either ARE critical edges, or
729 /// branch to a block that has incoming critical edges.
731 /// Note that this kill instruction will eventually be eliminated when
732 /// restrictions in the stackifier are relaxed.
734 static bool RequiresFPRegKill(const MachineBasicBlock *MBB) {
736 const BasicBlock *BB = MBB->getBasicBlock ();
737 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
738 const BasicBlock *Succ = *SI;
739 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
740 ++PI; // Block have at least one predecessory
741 if (PI != PE) { // If it has exactly one, this isn't crit edge
742 // If this block has more than one predecessor, check all of the
743 // predecessors to see if they have multiple successors. If so, then the
744 // block we are analyzing needs an FPRegKill.
745 for (PI = pred_begin(Succ); PI != PE; ++PI) {
746 const BasicBlock *Pred = *PI;
747 succ_const_iterator SI2 = succ_begin(Pred);
748 ++SI2; // There must be at least one successor of this block.
749 if (SI2 != succ_end(Pred))
750 return true; // Yes, we must insert the kill on this edge.
754 // If we got this far, there is no need to insert the kill instruction.
761 // InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that
762 // need them. This only occurs due to the floating point stackifier not being
763 // aggressive enough to handle arbitrary global stackification.
765 // Currently we insert an FP_REG_KILL instruction into each block that uses or
766 // defines a floating point virtual register.
768 // When the global register allocators (like linear scan) finally update live
769 // variable analysis, we can keep floating point values in registers across
770 // portions of the CFG that do not involve critical edges. This will be a big
771 // win, but we are waiting on the global allocators before we can do this.
773 // With a bit of work, the floating point stackifier pass can be enhanced to
774 // break critical edges as needed (to make a place to put compensation code),
775 // but this will require some infrastructure improvements as well.
777 void ISel::InsertFPRegKills() {
778 SSARegMap &RegMap = *F->getSSARegMap();
780 for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
781 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
782 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
783 MachineOperand& MO = I->getOperand(i);
784 if (MO.isRegister() && MO.getReg()) {
785 unsigned Reg = MO.getReg();
786 if (MRegisterInfo::isVirtualRegister(Reg))
787 if (RegMap.getRegClass(Reg)->getSize() == 10)
791 // If we haven't found an FP register use or def in this basic block, check
792 // to see if any of our successors has an FP PHI node, which will cause a
793 // copy to be inserted into this block.
794 for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(),
795 SE = BB->succ_end(); SI != SE; ++SI) {
796 MachineBasicBlock *SBB = *SI;
797 for (MachineBasicBlock::iterator I = SBB->begin();
798 I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
799 if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
805 // Okay, this block uses an FP register. If the block has successors (ie,
806 // it's not an unwind/return), insert the FP_REG_KILL instruction.
807 if (BB->succ_size () && RequiresFPRegKill(BB)) {
808 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
815 void ISel::getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
816 unsigned &IndexReg, unsigned &Disp) {
817 BaseReg = 0; Scale = 1; IndexReg = 0; Disp = 0;
818 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
819 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
820 BaseReg, Scale, IndexReg, Disp))
822 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
823 if (CE->getOpcode() == Instruction::GetElementPtr)
824 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
825 BaseReg, Scale, IndexReg, Disp))
829 // If it's not foldable, reset addr mode.
830 BaseReg = getReg(Addr);
831 Scale = 1; IndexReg = 0; Disp = 0;
834 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
835 // it into the conditional branch or select instruction which is the only user
836 // of the cc instruction. This is the case if the conditional branch is the
837 // only user of the setcc. We also don't handle long arguments below, so we
838 // reject them here as well.
840 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
841 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
842 if (SCI->hasOneUse()) {
843 Instruction *User = cast<Instruction>(SCI->use_back());
844 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
845 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
846 SCI->getOpcode() == Instruction::SetEQ ||
847 SCI->getOpcode() == Instruction::SetNE))
853 // Return a fixed numbering for setcc instructions which does not depend on the
854 // order of the opcodes.
856 static unsigned getSetCCNumber(unsigned Opcode) {
858 default: assert(0 && "Unknown setcc instruction!");
859 case Instruction::SetEQ: return 0;
860 case Instruction::SetNE: return 1;
861 case Instruction::SetLT: return 2;
862 case Instruction::SetGE: return 3;
863 case Instruction::SetGT: return 4;
864 case Instruction::SetLE: return 5;
868 // LLVM -> X86 signed X86 unsigned
869 // ----- ---------- ------------
870 // seteq -> sete sete
871 // setne -> setne setne
872 // setlt -> setl setb
873 // setge -> setge setae
874 // setgt -> setg seta
875 // setle -> setle setbe
877 // sets // Used by comparison with 0 optimization
879 static const unsigned SetCCOpcodeTab[2][8] = {
880 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
882 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
883 X86::SETSr, X86::SETNSr },
886 /// emitUCOMr - In the future when we support processors before the P6, this
887 /// wraps the logic for emitting an FUCOMr vs FUCOMIr.
888 void ISel::emitUCOMr(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
889 unsigned LHS, unsigned RHS) {
890 if (0) { // for processors prior to the P6
891 BuildMI(*MBB, IP, X86::FUCOMr, 2).addReg(LHS).addReg(RHS);
892 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
893 BuildMI(*MBB, IP, X86::SAHF, 1);
895 BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(LHS).addReg(RHS);
899 // EmitComparison - This function emits a comparison of the two operands,
900 // returning the extended setcc code to use.
901 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
902 MachineBasicBlock *MBB,
903 MachineBasicBlock::iterator IP) {
904 // The arguments are already supposed to be of the same type.
905 const Type *CompTy = Op0->getType();
906 unsigned Class = getClassB(CompTy);
907 unsigned Op0r = getReg(Op0, MBB, IP);
909 // Special case handling of: cmp R, i
910 if (isa<ConstantPointerNull>(Op1)) {
911 if (OpNum < 2) // seteq/setne -> test
912 BuildMI(*MBB, IP, X86::TEST32rr, 2).addReg(Op0r).addReg(Op0r);
914 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(0);
917 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
918 if (Class == cByte || Class == cShort || Class == cInt) {
919 unsigned Op1v = CI->getRawValue();
921 // Mask off any upper bits of the constant, if there are any...
922 Op1v &= (1ULL << (8 << Class)) - 1;
924 // If this is a comparison against zero, emit more efficient code. We
925 // can't handle unsigned comparisons against zero unless they are == or
926 // !=. These should have been strength reduced already anyway.
927 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
928 static const unsigned TESTTab[] = {
929 X86::TEST8rr, X86::TEST16rr, X86::TEST32rr
931 BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
933 if (OpNum == 2) return 6; // Map jl -> js
934 if (OpNum == 3) return 7; // Map jg -> jns
938 static const unsigned CMPTab[] = {
939 X86::CMP8ri, X86::CMP16ri, X86::CMP32ri
942 BuildMI(*MBB, IP, CMPTab[Class], 2).addReg(Op0r).addImm(Op1v);
945 assert(Class == cLong && "Unknown integer class!");
946 unsigned LowCst = CI->getRawValue();
947 unsigned HiCst = CI->getRawValue() >> 32;
948 if (OpNum < 2) { // seteq, setne
949 unsigned LoTmp = Op0r;
951 LoTmp = makeAnotherReg(Type::IntTy);
952 BuildMI(*MBB, IP, X86::XOR32ri, 2, LoTmp).addReg(Op0r).addImm(LowCst);
954 unsigned HiTmp = Op0r+1;
956 HiTmp = makeAnotherReg(Type::IntTy);
957 BuildMI(*MBB, IP, X86::XOR32ri, 2,HiTmp).addReg(Op0r+1).addImm(HiCst);
959 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
960 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
963 // Emit a sequence of code which compares the high and low parts once
964 // each, then uses a conditional move to handle the overflow case. For
965 // example, a setlt for long would generate code like this:
967 // AL = lo(op1) < lo(op2) // Always unsigned comparison
968 // BL = hi(op1) < hi(op2) // Signedness depends on operands
969 // dest = hi(op1) == hi(op2) ? BL : AL;
972 // FIXME: This would be much better if we had hierarchical register
973 // classes! Until then, hardcode registers so that we can deal with
974 // their aliases (because we don't have conditional byte moves).
976 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(LowCst);
977 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
978 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r+1).addImm(HiCst);
979 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0,X86::BL);
980 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
981 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
982 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
984 // NOTE: visitSetCondInst knows that the value is dumped into the BL
985 // register at this point for long values...
991 // Special case handling of comparison against +/- 0.0
992 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
993 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
994 BuildMI(*MBB, IP, X86::FTST, 1).addReg(Op0r);
995 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
996 BuildMI(*MBB, IP, X86::SAHF, 1);
1000 unsigned Op1r = getReg(Op1, MBB, IP);
1002 default: assert(0 && "Unknown type class!");
1003 // Emit: cmp <var1>, <var2> (do the comparison). We can
1004 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
1007 BuildMI(*MBB, IP, X86::CMP8rr, 2).addReg(Op0r).addReg(Op1r);
1010 BuildMI(*MBB, IP, X86::CMP16rr, 2).addReg(Op0r).addReg(Op1r);
1013 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
1016 emitUCOMr(MBB, IP, Op0r, Op1r);
1020 if (OpNum < 2) { // seteq, setne
1021 unsigned LoTmp = makeAnotherReg(Type::IntTy);
1022 unsigned HiTmp = makeAnotherReg(Type::IntTy);
1023 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
1024 BuildMI(*MBB, IP, X86::XOR32rr, 2, LoTmp).addReg(Op0r).addReg(Op1r);
1025 BuildMI(*MBB, IP, X86::XOR32rr, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
1026 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
1027 break; // Allow the sete or setne to be generated from flags set by OR
1029 // Emit a sequence of code which compares the high and low parts once
1030 // each, then uses a conditional move to handle the overflow case. For
1031 // example, a setlt for long would generate code like this:
1033 // AL = lo(op1) < lo(op2) // Signedness depends on operands
1034 // BL = hi(op1) < hi(op2) // Always unsigned comparison
1035 // dest = hi(op1) == hi(op2) ? BL : AL;
1038 // FIXME: This would be much better if we had hierarchical register
1039 // classes! Until then, hardcode registers so that we can deal with their
1040 // aliases (because we don't have conditional byte moves).
1042 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
1043 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
1044 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r+1).addReg(Op1r+1);
1045 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
1046 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
1047 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
1048 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
1050 // NOTE: visitSetCondInst knows that the value is dumped into the BL
1051 // register at this point for long values...
1058 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
1059 /// register, then move it to wherever the result should be.
1061 void ISel::visitSetCondInst(SetCondInst &I) {
1062 if (canFoldSetCCIntoBranchOrSelect(&I))
1063 return; // Fold this into a branch or select.
1065 unsigned DestReg = getReg(I);
1066 MachineBasicBlock::iterator MII = BB->end();
1067 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
1071 /// emitSetCCOperation - Common code shared between visitSetCondInst and
1072 /// constant expression support.
1074 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
1075 MachineBasicBlock::iterator IP,
1076 Value *Op0, Value *Op1, unsigned Opcode,
1077 unsigned TargetReg) {
1078 unsigned OpNum = getSetCCNumber(Opcode);
1079 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
1081 const Type *CompTy = Op0->getType();
1082 unsigned CompClass = getClassB(CompTy);
1083 bool isSigned = CompTy->isSigned() && CompClass != cFP;
1085 if (CompClass != cLong || OpNum < 2) {
1086 // Handle normal comparisons with a setcc instruction...
1087 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
1089 // Handle long comparisons by copying the value which is already in BL into
1090 // the register we want...
1091 BuildMI(*MBB, IP, X86::MOV8rr, 1, TargetReg).addReg(X86::BL);
1095 void ISel::visitSelectInst(SelectInst &SI) {
1096 unsigned DestReg = getReg(SI);
1097 MachineBasicBlock::iterator MII = BB->end();
1098 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1099 SI.getFalseValue(), DestReg);
1102 /// emitSelect - Common code shared between visitSelectInst and the constant
1103 /// expression support.
1104 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
1105 MachineBasicBlock::iterator IP,
1106 Value *Cond, Value *TrueVal, Value *FalseVal,
1108 unsigned SelectClass = getClassB(TrueVal->getType());
1110 // We don't support 8-bit conditional moves. If we have incoming constants,
1111 // transform them into 16-bit constants to avoid having a run-time conversion.
1112 if (SelectClass == cByte) {
1113 if (Constant *T = dyn_cast<Constant>(TrueVal))
1114 TrueVal = ConstantExpr::getCast(T, Type::ShortTy);
1115 if (Constant *F = dyn_cast<Constant>(FalseVal))
1116 FalseVal = ConstantExpr::getCast(F, Type::ShortTy);
1119 unsigned TrueReg = getReg(TrueVal, MBB, IP);
1120 unsigned FalseReg = getReg(FalseVal, MBB, IP);
1121 if (TrueReg == FalseReg) {
1122 static const unsigned Opcode[] = {
1123 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
1125 BuildMI(*MBB, IP, Opcode[SelectClass], 1, DestReg).addReg(TrueReg);
1126 if (SelectClass == cLong)
1127 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(TrueReg+1);
1132 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1133 // We successfully folded the setcc into the select instruction.
1135 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1136 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
1139 const Type *CompTy = SCI->getOperand(0)->getType();
1140 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1142 // LLVM -> X86 signed X86 unsigned
1143 // ----- ---------- ------------
1144 // seteq -> cmovNE cmovNE
1145 // setne -> cmovE cmovE
1146 // setlt -> cmovGE cmovAE
1147 // setge -> cmovL cmovB
1148 // setgt -> cmovLE cmovBE
1149 // setle -> cmovG cmovA
1151 // cmovNS // Used by comparison with 0 optimization
1154 switch (SelectClass) {
1155 default: assert(0 && "Unknown value class!");
1157 // Annoyingly, we don't have a full set of floating point conditional
1159 static const unsigned OpcodeTab[2][8] = {
1160 { X86::FCMOVNE, X86::FCMOVE, X86::FCMOVAE, X86::FCMOVB,
1161 X86::FCMOVBE, X86::FCMOVA, 0, 0 },
1162 { X86::FCMOVNE, X86::FCMOVE, 0, 0, 0, 0, 0, 0 },
1164 Opcode = OpcodeTab[isSigned][OpNum];
1166 // If opcode == 0, we hit a case that we don't support. Output a setcc
1167 // and compare the result against zero.
1169 unsigned CompClass = getClassB(CompTy);
1171 if (CompClass != cLong || OpNum < 2) {
1172 CondReg = makeAnotherReg(Type::BoolTy);
1173 // Handle normal comparisons with a setcc instruction...
1174 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, CondReg);
1176 // Long comparisons end up in the BL register.
1180 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1181 Opcode = X86::FCMOVE;
1187 static const unsigned OpcodeTab[2][8] = {
1188 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVAE16rr, X86::CMOVB16rr,
1189 X86::CMOVBE16rr, X86::CMOVA16rr, 0, 0 },
1190 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVGE16rr, X86::CMOVL16rr,
1191 X86::CMOVLE16rr, X86::CMOVG16rr, X86::CMOVNS16rr, X86::CMOVS16rr },
1193 Opcode = OpcodeTab[isSigned][OpNum];
1198 static const unsigned OpcodeTab[2][8] = {
1199 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVAE32rr, X86::CMOVB32rr,
1200 X86::CMOVBE32rr, X86::CMOVA32rr, 0, 0 },
1201 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVGE32rr, X86::CMOVL32rr,
1202 X86::CMOVLE32rr, X86::CMOVG32rr, X86::CMOVNS32rr, X86::CMOVS32rr },
1204 Opcode = OpcodeTab[isSigned][OpNum];
1209 // Get the value being branched on, and use it to set the condition codes.
1210 unsigned CondReg = getReg(Cond, MBB, IP);
1211 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1212 switch (SelectClass) {
1213 default: assert(0 && "Unknown value class!");
1214 case cFP: Opcode = X86::FCMOVE; break;
1216 case cShort: Opcode = X86::CMOVE16rr; break;
1218 case cLong: Opcode = X86::CMOVE32rr; break;
1222 unsigned RealDestReg = DestReg;
1225 // Annoyingly enough, X86 doesn't HAVE 8-bit conditional moves. Because of
1226 // this, we have to promote the incoming values to 16 bits, perform a 16-bit
1227 // cmove, then truncate the result.
1228 if (SelectClass == cByte) {
1229 DestReg = makeAnotherReg(Type::ShortTy);
1230 if (getClassB(TrueVal->getType()) == cByte) {
1231 // Promote the true value, by storing it into AL, and reading from AX.
1232 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::AL).addReg(TrueReg);
1233 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::AH).addImm(0);
1234 TrueReg = makeAnotherReg(Type::ShortTy);
1235 BuildMI(*MBB, IP, X86::MOV16rr, 1, TrueReg).addReg(X86::AX);
1237 if (getClassB(FalseVal->getType()) == cByte) {
1238 // Promote the true value, by storing it into CL, and reading from CX.
1239 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(FalseReg);
1240 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::CH).addImm(0);
1241 FalseReg = makeAnotherReg(Type::ShortTy);
1242 BuildMI(*MBB, IP, X86::MOV16rr, 1, FalseReg).addReg(X86::CX);
1246 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(TrueReg).addReg(FalseReg);
1248 switch (SelectClass) {
1250 // We did the computation with 16-bit registers. Truncate back to our
1251 // result by copying into AX then copying out AL.
1252 BuildMI(*MBB, IP, X86::MOV16rr, 1, X86::AX).addReg(DestReg);
1253 BuildMI(*MBB, IP, X86::MOV8rr, 1, RealDestReg).addReg(X86::AL);
1256 // Move the upper half of the value as well.
1257 BuildMI(*MBB, IP, Opcode, 2,DestReg+1).addReg(TrueReg+1).addReg(FalseReg+1);
1264 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1265 /// operand, in the specified target register.
1267 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1268 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
1270 Value *Val = VR.Val;
1271 const Type *Ty = VR.Ty;
1273 if (Constant *C = dyn_cast<Constant>(Val)) {
1274 Val = ConstantExpr::getCast(C, Type::IntTy);
1278 // If this is a simple constant, just emit a MOVri directly to avoid the
1280 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1281 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1282 BuildMI(BB, X86::MOV32ri, 1, targetReg).addImm(TheVal);
1287 // Make sure we have the register number for this value...
1288 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1290 switch (getClassB(Ty)) {
1292 // Extend value into target register (8->32)
1294 BuildMI(BB, X86::MOVZX32rr8, 1, targetReg).addReg(Reg);
1296 BuildMI(BB, X86::MOVSX32rr8, 1, targetReg).addReg(Reg);
1299 // Extend value into target register (16->32)
1301 BuildMI(BB, X86::MOVZX32rr16, 1, targetReg).addReg(Reg);
1303 BuildMI(BB, X86::MOVSX32rr16, 1, targetReg).addReg(Reg);
1306 // Move value into target register (32->32)
1307 BuildMI(BB, X86::MOV32rr, 1, targetReg).addReg(Reg);
1310 assert(0 && "Unpromotable operand class in promote32");
1314 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
1315 /// we have the following possibilities:
1317 /// ret void: No return value, simply emit a 'ret' instruction
1318 /// ret sbyte, ubyte : Extend value into EAX and return
1319 /// ret short, ushort: Extend value into EAX and return
1320 /// ret int, uint : Move value into EAX and return
1321 /// ret pointer : Move value into EAX and return
1322 /// ret long, ulong : Move value into EAX/EDX and return
1323 /// ret float/double : Top of FP stack
1325 void ISel::visitReturnInst(ReturnInst &I) {
1326 if (I.getNumOperands() == 0) {
1327 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
1331 Value *RetVal = I.getOperand(0);
1332 switch (getClassB(RetVal->getType())) {
1333 case cByte: // integral return values: extend or move into EAX and return
1336 promote32(X86::EAX, ValueRecord(RetVal));
1337 // Declare that EAX is live on exit
1338 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
1340 case cFP: { // Floats & Doubles: Return in ST(0)
1341 unsigned RetReg = getReg(RetVal);
1342 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
1343 // Declare that top-of-stack is live on exit
1344 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
1348 unsigned RetReg = getReg(RetVal);
1349 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
1350 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
1351 // Declare that EAX & EDX are live on exit
1352 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
1357 visitInstruction(I);
1359 // Emit a 'ret' instruction
1360 BuildMI(BB, X86::RET, 0);
1363 // getBlockAfter - Return the basic block which occurs lexically after the
1365 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1366 Function::iterator I = BB; ++I; // Get iterator to next block
1367 return I != BB->getParent()->end() ? &*I : 0;
1370 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1371 /// that since code layout is frozen at this point, that if we are trying to
1372 /// jump to a block that is the immediate successor of the current block, we can
1373 /// just make a fall-through (but we don't currently).
1375 void ISel::visitBranchInst(BranchInst &BI) {
1376 // Update machine-CFG edges
1377 BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
1378 if (BI.isConditional())
1379 BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
1381 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1383 if (!BI.isConditional()) { // Unconditional branch?
1384 if (BI.getSuccessor(0) != NextBB)
1385 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1389 // See if we can fold the setcc into the branch itself...
1390 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1392 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1393 // computed some other way...
1394 unsigned condReg = getReg(BI.getCondition());
1395 BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
1396 if (BI.getSuccessor(1) == NextBB) {
1397 if (BI.getSuccessor(0) != NextBB)
1398 BuildMI(BB, X86::JNE, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1400 BuildMI(BB, X86::JE, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1402 if (BI.getSuccessor(0) != NextBB)
1403 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1408 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1409 MachineBasicBlock::iterator MII = BB->end();
1410 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1412 const Type *CompTy = SCI->getOperand(0)->getType();
1413 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1416 // LLVM -> X86 signed X86 unsigned
1417 // ----- ---------- ------------
1425 // js // Used by comparison with 0 optimization
1428 static const unsigned OpcodeTab[2][8] = {
1429 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1430 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1431 X86::JS, X86::JNS },
1434 if (BI.getSuccessor(0) != NextBB) {
1435 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
1436 .addMBB(MBBMap[BI.getSuccessor(0)]);
1437 if (BI.getSuccessor(1) != NextBB)
1438 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1440 // Change to the inverse condition...
1441 if (BI.getSuccessor(1) != NextBB) {
1443 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
1444 .addMBB(MBBMap[BI.getSuccessor(1)]);
1450 /// doCall - This emits an abstract call instruction, setting up the arguments
1451 /// and the return value as appropriate. For the actual function call itself,
1452 /// it inserts the specified CallMI instruction into the stream.
1454 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1455 const std::vector<ValueRecord> &Args) {
1457 // Count how many bytes are to be pushed on the stack...
1458 unsigned NumBytes = 0;
1460 if (!Args.empty()) {
1461 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1462 switch (getClassB(Args[i].Ty)) {
1463 case cByte: case cShort: case cInt:
1464 NumBytes += 4; break;
1466 NumBytes += 8; break;
1468 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1470 default: assert(0 && "Unknown class!");
1473 // Adjust the stack pointer for the new arguments...
1474 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1476 // Arguments go on the stack in reverse order, as specified by the ABI.
1477 unsigned ArgOffset = 0;
1478 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1480 switch (getClassB(Args[i].Ty)) {
1482 if (Args[i].Val && isa<ConstantBool>(Args[i].Val)) {
1483 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1484 .addImm(Args[i].Val == ConstantBool::True);
1489 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1490 // Zero/Sign extend constant, then stuff into memory.
1491 ConstantInt *Val = cast<ConstantInt>(Args[i].Val);
1492 Val = cast<ConstantInt>(ConstantExpr::getCast(Val, Type::IntTy));
1493 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1494 .addImm(Val->getRawValue() & 0xFFFFFFFF);
1496 // Promote arg to 32 bits wide into a temporary register...
1497 ArgReg = makeAnotherReg(Type::UIntTy);
1498 promote32(ArgReg, Args[i]);
1499 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1500 X86::ESP, ArgOffset).addReg(ArgReg);
1504 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1505 unsigned Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1506 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1507 X86::ESP, ArgOffset).addImm(Val);
1508 } else if (Args[i].Val && isa<ConstantPointerNull>(Args[i].Val)) {
1509 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1510 X86::ESP, ArgOffset).addImm(0);
1512 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1513 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1514 X86::ESP, ArgOffset).addReg(ArgReg);
1518 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1519 uint64_t Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1520 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1521 X86::ESP, ArgOffset).addImm(Val & ~0U);
1522 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1523 X86::ESP, ArgOffset+4).addImm(Val >> 32ULL);
1525 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1526 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1527 X86::ESP, ArgOffset).addReg(ArgReg);
1528 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1529 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1531 ArgOffset += 4; // 8 byte entry, not 4.
1535 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1536 if (Args[i].Ty == Type::FloatTy) {
1537 addRegOffset(BuildMI(BB, X86::FST32m, 5),
1538 X86::ESP, ArgOffset).addReg(ArgReg);
1540 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1541 addRegOffset(BuildMI(BB, X86::FST64m, 5),
1542 X86::ESP, ArgOffset).addReg(ArgReg);
1543 ArgOffset += 4; // 8 byte entry, not 4.
1547 default: assert(0 && "Unknown class!");
1552 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(0);
1555 BB->push_back(CallMI);
1557 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addImm(NumBytes);
1559 // If there is a return value, scavenge the result from the location the call
1562 if (Ret.Ty != Type::VoidTy) {
1563 unsigned DestClass = getClassB(Ret.Ty);
1564 switch (DestClass) {
1568 // Integral results are in %eax, or the appropriate portion
1570 static const unsigned regRegMove[] = {
1571 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr
1573 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1574 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1577 case cFP: // Floating-point return values live in %ST(0)
1578 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1580 case cLong: // Long values are left in EDX:EAX
1581 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg).addReg(X86::EAX);
1582 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg+1).addReg(X86::EDX);
1584 default: assert(0 && "Unknown class!");
1590 /// visitCallInst - Push args on stack and do a procedure call instruction.
1591 void ISel::visitCallInst(CallInst &CI) {
1592 MachineInstr *TheCall;
1593 if (Function *F = CI.getCalledFunction()) {
1594 // Is it an intrinsic function call?
1595 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1596 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1600 // Emit a CALL instruction with PC-relative displacement.
1601 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1602 } else { // Emit an indirect call...
1603 unsigned Reg = getReg(CI.getCalledValue());
1604 TheCall = BuildMI(X86::CALL32r, 1).addReg(Reg);
1607 std::vector<ValueRecord> Args;
1608 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1609 Args.push_back(ValueRecord(CI.getOperand(i)));
1611 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1612 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1615 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1616 /// function, lowering any calls to unknown intrinsic functions into the
1617 /// equivalent LLVM code.
1619 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1620 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1621 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1622 if (CallInst *CI = dyn_cast<CallInst>(I++))
1623 if (Function *F = CI->getCalledFunction())
1624 switch (F->getIntrinsicID()) {
1625 case Intrinsic::not_intrinsic:
1626 case Intrinsic::vastart:
1627 case Intrinsic::vacopy:
1628 case Intrinsic::vaend:
1629 case Intrinsic::returnaddress:
1630 case Intrinsic::frameaddress:
1631 case Intrinsic::memcpy:
1632 case Intrinsic::memset:
1633 case Intrinsic::isunordered:
1634 case Intrinsic::readport:
1635 case Intrinsic::writeport:
1636 // We directly implement these intrinsics
1638 case Intrinsic::readio: {
1639 // On X86, memory operations are in-order. Lower this intrinsic
1640 // into a volatile load.
1641 Instruction *Before = CI->getPrev();
1642 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1643 CI->replaceAllUsesWith(LI);
1644 BB->getInstList().erase(CI);
1647 case Intrinsic::writeio: {
1648 // On X86, memory operations are in-order. Lower this intrinsic
1649 // into a volatile store.
1650 Instruction *Before = CI->getPrev();
1651 StoreInst *LI = new StoreInst(CI->getOperand(1),
1652 CI->getOperand(2), true, CI);
1653 CI->replaceAllUsesWith(LI);
1654 BB->getInstList().erase(CI);
1658 // All other intrinsic calls we must lower.
1659 Instruction *Before = CI->getPrev();
1660 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1661 if (Before) { // Move iterator to instruction after call
1669 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1670 unsigned TmpReg1, TmpReg2;
1672 case Intrinsic::vastart:
1673 // Get the address of the first vararg value...
1674 TmpReg1 = getReg(CI);
1675 addFrameReference(BuildMI(BB, X86::LEA32r, 5, TmpReg1), VarArgsFrameIndex);
1678 case Intrinsic::vacopy:
1679 TmpReg1 = getReg(CI);
1680 TmpReg2 = getReg(CI.getOperand(1));
1681 BuildMI(BB, X86::MOV32rr, 1, TmpReg1).addReg(TmpReg2);
1683 case Intrinsic::vaend: return; // Noop on X86
1685 case Intrinsic::returnaddress:
1686 case Intrinsic::frameaddress:
1687 TmpReg1 = getReg(CI);
1688 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1689 if (ID == Intrinsic::returnaddress) {
1690 // Just load the return address
1691 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, TmpReg1),
1692 ReturnAddressIndex);
1694 addFrameReference(BuildMI(BB, X86::LEA32r, 4, TmpReg1),
1695 ReturnAddressIndex, -4);
1698 // Values other than zero are not implemented yet.
1699 BuildMI(BB, X86::MOV32ri, 1, TmpReg1).addImm(0);
1703 case Intrinsic::isunordered:
1704 TmpReg1 = getReg(CI.getOperand(1));
1705 TmpReg2 = getReg(CI.getOperand(2));
1706 emitUCOMr(BB, BB->end(), TmpReg2, TmpReg1);
1707 TmpReg2 = getReg(CI);
1708 BuildMI(BB, X86::SETPr, 0, TmpReg2);
1711 case Intrinsic::memcpy: {
1712 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1714 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1715 Align = AlignC->getRawValue();
1716 if (Align == 0) Align = 1;
1719 // Turn the byte code into # iterations
1722 switch (Align & 3) {
1723 case 2: // WORD aligned
1724 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1725 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1727 CountReg = makeAnotherReg(Type::IntTy);
1728 unsigned ByteReg = getReg(CI.getOperand(3));
1729 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1731 Opcode = X86::REP_MOVSW;
1733 case 0: // DWORD aligned
1734 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1735 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1737 CountReg = makeAnotherReg(Type::IntTy);
1738 unsigned ByteReg = getReg(CI.getOperand(3));
1739 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1741 Opcode = X86::REP_MOVSD;
1743 default: // BYTE aligned
1744 CountReg = getReg(CI.getOperand(3));
1745 Opcode = X86::REP_MOVSB;
1749 // No matter what the alignment is, we put the source in ESI, the
1750 // destination in EDI, and the count in ECX.
1751 TmpReg1 = getReg(CI.getOperand(1));
1752 TmpReg2 = getReg(CI.getOperand(2));
1753 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1754 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1755 BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2);
1756 BuildMI(BB, Opcode, 0);
1759 case Intrinsic::memset: {
1760 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1762 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1763 Align = AlignC->getRawValue();
1764 if (Align == 0) Align = 1;
1767 // Turn the byte code into # iterations
1770 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1771 unsigned Val = ValC->getRawValue() & 255;
1773 // If the value is a constant, then we can potentially use larger copies.
1774 switch (Align & 3) {
1775 case 2: // WORD aligned
1776 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1777 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1779 CountReg = makeAnotherReg(Type::IntTy);
1780 unsigned ByteReg = getReg(CI.getOperand(3));
1781 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1783 BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val);
1784 Opcode = X86::REP_STOSW;
1786 case 0: // DWORD aligned
1787 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1788 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1790 CountReg = makeAnotherReg(Type::IntTy);
1791 unsigned ByteReg = getReg(CI.getOperand(3));
1792 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1794 Val = (Val << 8) | Val;
1795 BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val);
1796 Opcode = X86::REP_STOSD;
1798 default: // BYTE aligned
1799 CountReg = getReg(CI.getOperand(3));
1800 BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val);
1801 Opcode = X86::REP_STOSB;
1805 // If it's not a constant value we are storing, just fall back. We could
1806 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1807 unsigned ValReg = getReg(CI.getOperand(2));
1808 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1809 CountReg = getReg(CI.getOperand(3));
1810 Opcode = X86::REP_STOSB;
1813 // No matter what the alignment is, we put the source in ESI, the
1814 // destination in EDI, and the count in ECX.
1815 TmpReg1 = getReg(CI.getOperand(1));
1816 //TmpReg2 = getReg(CI.getOperand(2));
1817 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1818 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1819 BuildMI(BB, Opcode, 0);
1823 case Intrinsic::readport: {
1824 // First, determine that the size of the operand falls within the acceptable
1825 // range for this architecture.
1827 if (getClassB(CI.getOperand(1)->getType()) != cShort) {
1828 std::cerr << "llvm.readport: Address size is not 16 bits\n";
1832 // Now, move the I/O port address into the DX register and use the IN
1833 // instruction to get the input data.
1835 unsigned Class = getClass(CI.getCalledFunction()->getReturnType());
1836 unsigned DestReg = getReg(CI);
1838 // If the port is a single-byte constant, use the immediate form.
1839 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(1)))
1840 if ((C->getRawValue() & 255) == C->getRawValue()) {
1843 BuildMI(BB, X86::IN8ri, 1).addImm((unsigned char)C->getRawValue());
1844 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1847 BuildMI(BB, X86::IN16ri, 1).addImm((unsigned char)C->getRawValue());
1848 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
1851 BuildMI(BB, X86::IN32ri, 1).addImm((unsigned char)C->getRawValue());
1852 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
1857 unsigned Reg = getReg(CI.getOperand(1));
1858 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
1861 BuildMI(BB, X86::IN8rr, 0);
1862 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1865 BuildMI(BB, X86::IN16rr, 0);
1866 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
1869 BuildMI(BB, X86::IN32rr, 0);
1870 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
1873 std::cerr << "Cannot do input on this data type";
1879 case Intrinsic::writeport: {
1880 // First, determine that the size of the operand falls within the
1881 // acceptable range for this architecture.
1882 if (getClass(CI.getOperand(2)->getType()) != cShort) {
1883 std::cerr << "llvm.writeport: Address size is not 16 bits\n";
1887 unsigned Class = getClassB(CI.getOperand(1)->getType());
1888 unsigned ValReg = getReg(CI.getOperand(1));
1891 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1894 BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(ValReg);
1897 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(ValReg);
1900 std::cerr << "llvm.writeport: invalid data type for X86 target";
1905 // If the port is a single-byte constant, use the immediate form.
1906 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(2)))
1907 if ((C->getRawValue() & 255) == C->getRawValue()) {
1908 static const unsigned O[] = { X86::OUT8ir, X86::OUT16ir, X86::OUT32ir };
1909 BuildMI(BB, O[Class], 1).addImm((unsigned char)C->getRawValue());
1913 // Otherwise, move the I/O port address into the DX register and the value
1914 // to write into the AL/AX/EAX register.
1915 static const unsigned Opc[] = { X86::OUT8rr, X86::OUT16rr, X86::OUT32rr };
1916 unsigned Reg = getReg(CI.getOperand(2));
1917 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
1918 BuildMI(BB, Opc[Class], 0);
1922 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1926 static bool isSafeToFoldLoadIntoInstruction(LoadInst &LI, Instruction &User) {
1927 if (LI.getParent() != User.getParent())
1929 BasicBlock::iterator It = &LI;
1930 // Check all of the instructions between the load and the user. We should
1931 // really use alias analysis here, but for now we just do something simple.
1932 for (++It; It != BasicBlock::iterator(&User); ++It) {
1933 switch (It->getOpcode()) {
1934 case Instruction::Free:
1935 case Instruction::Store:
1936 case Instruction::Call:
1937 case Instruction::Invoke:
1939 case Instruction::Load:
1940 if (cast<LoadInst>(It)->isVolatile() && LI.isVolatile())
1948 /// visitSimpleBinary - Implement simple binary operators for integral types...
1949 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1952 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1953 unsigned DestReg = getReg(B);
1954 MachineBasicBlock::iterator MI = BB->end();
1955 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1956 unsigned Class = getClassB(B.getType());
1958 // Special case: op Reg, load [mem]
1959 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1) && Class != cLong &&
1961 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B))
1962 if (!B.swapOperands())
1963 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
1965 if (isa<LoadInst>(Op1) && Class != cLong && Op1->hasOneUse() &&
1966 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op1), B)) {
1970 static const unsigned OpcodeTab[][3] = {
1971 // Arithmetic operators
1972 { X86::ADD8rm, X86::ADD16rm, X86::ADD32rm }, // ADD
1973 { X86::SUB8rm, X86::SUB16rm, X86::SUB32rm }, // SUB
1975 // Bitwise operators
1976 { X86::AND8rm, X86::AND16rm, X86::AND32rm }, // AND
1977 { X86:: OR8rm, X86:: OR16rm, X86:: OR32rm }, // OR
1978 { X86::XOR8rm, X86::XOR16rm, X86::XOR32rm }, // XOR
1980 Opcode = OpcodeTab[OperatorClass][Class];
1982 static const unsigned OpcodeTab[][2] = {
1983 { X86::FADD32m, X86::FADD64m }, // ADD
1984 { X86::FSUB32m, X86::FSUB64m }, // SUB
1986 const Type *Ty = Op0->getType();
1987 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1988 Opcode = OpcodeTab[OperatorClass][Ty == Type::DoubleTy];
1991 unsigned Op0r = getReg(Op0);
1992 if (AllocaInst *AI =
1993 dyn_castFixedAlloca(cast<LoadInst>(Op1)->getOperand(0))) {
1994 unsigned FI = getFixedSizedAllocaFI(AI);
1995 addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r), FI);
1998 unsigned BaseReg, Scale, IndexReg, Disp;
1999 getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), BaseReg,
2000 Scale, IndexReg, Disp);
2002 addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r),
2003 BaseReg, Scale, IndexReg, Disp);
2008 // If this is a floating point subtract, check to see if we can fold the first
2010 if (Class == cFP && OperatorClass == 1 &&
2011 isa<LoadInst>(Op0) &&
2012 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B)) {
2013 const Type *Ty = Op0->getType();
2014 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
2015 unsigned Opcode = Ty == Type::FloatTy ? X86::FSUBR32m : X86::FSUBR64m;
2017 unsigned Op1r = getReg(Op1);
2018 if (AllocaInst *AI =
2019 dyn_castFixedAlloca(cast<LoadInst>(Op0)->getOperand(0))) {
2020 unsigned FI = getFixedSizedAllocaFI(AI);
2021 addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r), FI);
2023 unsigned BaseReg, Scale, IndexReg, Disp;
2024 getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), BaseReg,
2025 Scale, IndexReg, Disp);
2027 addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r),
2028 BaseReg, Scale, IndexReg, Disp);
2033 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
2037 /// emitBinaryFPOperation - This method handles emission of floating point
2038 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
2039 void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
2040 MachineBasicBlock::iterator IP,
2041 Value *Op0, Value *Op1,
2042 unsigned OperatorClass, unsigned DestReg) {
2044 // Special case: op Reg, <const fp>
2045 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1))
2046 if (!Op1C->isExactlyValue(+0.0) && !Op1C->isExactlyValue(+1.0)) {
2047 // Create a constant pool entry for this constant.
2048 MachineConstantPool *CP = F->getConstantPool();
2049 unsigned CPI = CP->getConstantPoolIndex(Op1C);
2050 const Type *Ty = Op1->getType();
2052 static const unsigned OpcodeTab[][4] = {
2053 { X86::FADD32m, X86::FSUB32m, X86::FMUL32m, X86::FDIV32m }, // Float
2054 { X86::FADD64m, X86::FSUB64m, X86::FMUL64m, X86::FDIV64m }, // Double
2057 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
2058 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
2059 unsigned Op0r = getReg(Op0, BB, IP);
2060 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
2061 DestReg).addReg(Op0r), CPI);
2065 // Special case: R1 = op <const fp>, R2
2066 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
2067 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
2069 unsigned op1Reg = getReg(Op1, BB, IP);
2070 BuildMI(*BB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
2072 } else if (!CFP->isExactlyValue(+0.0) && !CFP->isExactlyValue(+1.0)) {
2073 // R1 = op CST, R2 --> R1 = opr R2, CST
2075 // Create a constant pool entry for this constant.
2076 MachineConstantPool *CP = F->getConstantPool();
2077 unsigned CPI = CP->getConstantPoolIndex(CFP);
2078 const Type *Ty = CFP->getType();
2080 static const unsigned OpcodeTab[][4] = {
2081 { X86::FADD32m, X86::FSUBR32m, X86::FMUL32m, X86::FDIVR32m }, // Float
2082 { X86::FADD64m, X86::FSUBR64m, X86::FMUL64m, X86::FDIVR64m }, // Double
2085 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2086 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
2087 unsigned Op1r = getReg(Op1, BB, IP);
2088 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
2089 DestReg).addReg(Op1r), CPI);
2094 static const unsigned OpcodeTab[4] = {
2095 X86::FpADD, X86::FpSUB, X86::FpMUL, X86::FpDIV
2098 unsigned Opcode = OpcodeTab[OperatorClass];
2099 unsigned Op0r = getReg(Op0, BB, IP);
2100 unsigned Op1r = getReg(Op1, BB, IP);
2101 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2104 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
2105 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
2108 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
2109 /// and constant expression support.
2111 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
2112 MachineBasicBlock::iterator IP,
2113 Value *Op0, Value *Op1,
2114 unsigned OperatorClass, unsigned DestReg) {
2115 unsigned Class = getClassB(Op0->getType());
2118 assert(OperatorClass < 2 && "No logical ops for FP!");
2119 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
2123 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
2124 if (OperatorClass == 1) {
2125 static unsigned const NEGTab[] = {
2126 X86::NEG8r, X86::NEG16r, X86::NEG32r, 0, X86::NEG32r
2129 // sub 0, X -> neg X
2130 if (CI->isNullValue()) {
2131 unsigned op1Reg = getReg(Op1, MBB, IP);
2132 BuildMI(*MBB, IP, NEGTab[Class], 1, DestReg).addReg(op1Reg);
2134 if (Class == cLong) {
2135 // We just emitted: Dl = neg Sl
2136 // Now emit : T = addc Sh, 0
2138 unsigned T = makeAnotherReg(Type::IntTy);
2139 BuildMI(*MBB, IP, X86::ADC32ri, 2, T).addReg(op1Reg+1).addImm(0);
2140 BuildMI(*MBB, IP, X86::NEG32r, 1, DestReg+1).addReg(T);
2143 } else if (Op1->hasOneUse() && Class != cLong) {
2144 // sub C, X -> tmp = neg X; DestReg = add tmp, C. This is better
2145 // than copying C into a temporary register, because of register
2146 // pressure (tmp and destreg can share a register.
2147 static unsigned const ADDRITab[] = {
2148 X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri
2150 unsigned op1Reg = getReg(Op1, MBB, IP);
2151 unsigned Tmp = makeAnotherReg(Op0->getType());
2152 BuildMI(*MBB, IP, NEGTab[Class], 1, Tmp).addReg(op1Reg);
2153 BuildMI(*MBB, IP, ADDRITab[Class], 2,
2154 DestReg).addReg(Tmp).addImm(CI->getRawValue());
2159 // Special case: op Reg, <const int>
2160 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
2161 unsigned Op0r = getReg(Op0, MBB, IP);
2163 // xor X, -1 -> not X
2164 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
2165 static unsigned const NOTTab[] = {
2166 X86::NOT8r, X86::NOT16r, X86::NOT32r, 0, X86::NOT32r
2168 BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
2169 if (Class == cLong) // Invert the top part too
2170 BuildMI(*MBB, IP, X86::NOT32r, 1, DestReg+1).addReg(Op0r+1);
2174 // add X, -1 -> dec X
2175 if (OperatorClass == 0 && Op1C->isAllOnesValue() && Class != cLong) {
2176 // Note that we can't use dec for 64-bit decrements, because it does not
2177 // set the carry flag!
2178 static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r };
2179 BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
2183 // add X, 1 -> inc X
2184 if (OperatorClass == 0 && Op1C->equalsInt(1) && Class != cLong) {
2185 // Note that we can't use inc for 64-bit increments, because it does not
2186 // set the carry flag!
2187 static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r };
2188 BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
2192 static const unsigned OpcodeTab[][5] = {
2193 // Arithmetic operators
2194 { X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
2195 { X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
2197 // Bitwise operators
2198 { X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
2199 { X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
2200 { X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
2203 unsigned Opcode = OpcodeTab[OperatorClass][Class];
2204 unsigned Op1l = cast<ConstantInt>(Op1C)->getRawValue();
2206 if (Class != cLong) {
2207 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2211 // If this is a long value and the high or low bits have a special
2212 // property, emit some special cases.
2213 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
2215 // If the constant is zero in the low 32-bits, just copy the low part
2216 // across and apply the normal 32-bit operation to the high parts. There
2217 // will be no carry or borrow into the top.
2219 if (OperatorClass != 2) // All but and...
2220 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0r);
2222 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2223 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg+1)
2224 .addReg(Op0r+1).addImm(Op1h);
2228 // If this is a logical operation and the top 32-bits are zero, just
2229 // operate on the lower 32.
2230 if (Op1h == 0 && OperatorClass > 1) {
2231 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg)
2232 .addReg(Op0r).addImm(Op1l);
2233 if (OperatorClass != 2) // All but and
2234 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(Op0r+1);
2236 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2240 // TODO: We could handle lots of other special cases here, such as AND'ing
2241 // with 0xFFFFFFFF00000000 -> noop, etc.
2243 // Otherwise, code generate the full operation with a constant.
2244 static const unsigned TopTab[] = {
2245 X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
2248 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2249 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
2250 .addReg(Op0r+1).addImm(Op1h);
2254 // Finally, handle the general case now.
2255 static const unsigned OpcodeTab[][5] = {
2256 // Arithmetic operators
2257 { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, 0, X86::ADD32rr }, // ADD
2258 { X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, 0, X86::SUB32rr }, // SUB
2260 // Bitwise operators
2261 { X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
2262 { X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
2263 { X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
2266 unsigned Opcode = OpcodeTab[OperatorClass][Class];
2267 unsigned Op0r = getReg(Op0, MBB, IP);
2268 unsigned Op1r = getReg(Op1, MBB, IP);
2269 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2271 if (Class == cLong) { // Handle the upper 32 bits of long values...
2272 static const unsigned TopTab[] = {
2273 X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
2275 BuildMI(*MBB, IP, TopTab[OperatorClass], 2,
2276 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
2280 /// doMultiply - Emit appropriate instructions to multiply together the
2281 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
2282 /// result should be given as DestTy.
2284 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
2285 unsigned DestReg, const Type *DestTy,
2286 unsigned op0Reg, unsigned op1Reg) {
2287 unsigned Class = getClass(DestTy);
2291 BuildMI(*MBB, MBBI, Class == cInt ? X86::IMUL32rr:X86::IMUL16rr, 2, DestReg)
2292 .addReg(op0Reg).addReg(op1Reg);
2295 // Must use the MUL instruction, which forces use of AL...
2296 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, X86::AL).addReg(op0Reg);
2297 BuildMI(*MBB, MBBI, X86::MUL8r, 1).addReg(op1Reg);
2298 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
2301 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
2305 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
2306 // returns zero when the input is not exactly a power of two.
2307 static unsigned ExactLog2(unsigned Val) {
2308 if (Val == 0 || (Val & (Val-1))) return 0;
2318 /// doMultiplyConst - This function is specialized to efficiently codegen an 8,
2319 /// 16, or 32-bit integer multiply by a constant.
2320 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
2321 MachineBasicBlock::iterator IP,
2322 unsigned DestReg, const Type *DestTy,
2323 unsigned op0Reg, unsigned ConstRHS) {
2324 static const unsigned MOVrrTab[] = {X86::MOV8rr, X86::MOV16rr, X86::MOV32rr};
2325 static const unsigned MOVriTab[] = {X86::MOV8ri, X86::MOV16ri, X86::MOV32ri};
2326 static const unsigned ADDrrTab[] = {X86::ADD8rr, X86::ADD16rr, X86::ADD32rr};
2327 static const unsigned NEGrTab[] = {X86::NEG8r , X86::NEG16r , X86::NEG32r };
2329 unsigned Class = getClass(DestTy);
2332 // Handle special cases here.
2335 TmpReg = makeAnotherReg(DestTy);
2336 BuildMI(*MBB, IP, NEGrTab[Class], 1, TmpReg).addReg(op0Reg);
2337 BuildMI(*MBB, IP, ADDrrTab[Class], 1,DestReg).addReg(TmpReg).addReg(TmpReg);
2340 BuildMI(*MBB, IP, NEGrTab[Class], 1, DestReg).addReg(op0Reg);
2343 BuildMI(*MBB, IP, MOVriTab[Class], 1, DestReg).addImm(0);
2346 BuildMI(*MBB, IP, MOVrrTab[Class], 1, DestReg).addReg(op0Reg);
2349 BuildMI(*MBB, IP, ADDrrTab[Class], 1,DestReg).addReg(op0Reg).addReg(op0Reg);
2354 if (Class == cInt) {
2355 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, DestReg),
2356 op0Reg, ConstRHS-1, op0Reg, 0);
2362 if (Class == cInt) {
2363 TmpReg = makeAnotherReg(DestTy);
2364 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TmpReg),
2365 op0Reg, -ConstRHS-1, op0Reg, 0);
2366 BuildMI(*MBB, IP, NEGrTab[Class], 1, DestReg).addReg(TmpReg);
2371 // If the element size is exactly a power of 2, use a shift to get it.
2372 if (unsigned Shift = ExactLog2(ConstRHS)) {
2374 default: assert(0 && "Unknown class for this function!");
2376 BuildMI(*MBB, IP, X86::SHL8ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2379 BuildMI(*MBB, IP, X86::SHL16ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2382 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2387 // If the element size is a negative power of 2, use a shift/neg to get it.
2388 if (unsigned Shift = ExactLog2(-ConstRHS)) {
2389 TmpReg = makeAnotherReg(DestTy);
2390 BuildMI(*MBB, IP, NEGrTab[Class], 1, TmpReg).addReg(op0Reg);
2392 default: assert(0 && "Unknown class for this function!");
2394 BuildMI(*MBB, IP, X86::SHL8ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2397 BuildMI(*MBB, IP, X86::SHL16ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2400 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2405 if (Class == cShort) {
2406 BuildMI(*MBB, IP, X86::IMUL16rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
2408 } else if (Class == cInt) {
2409 BuildMI(*MBB, IP, X86::IMUL32rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
2413 // Most general case, emit a normal multiply...
2414 TmpReg = makeAnotherReg(DestTy);
2415 BuildMI(*MBB, IP, MOVriTab[Class], 1, TmpReg).addImm(ConstRHS);
2417 // Emit a MUL to multiply the register holding the index by
2418 // elementSize, putting the result in OffsetReg.
2419 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
2422 /// visitMul - Multiplies are not simple binary operators because they must deal
2423 /// with the EAX register explicitly.
2425 void ISel::visitMul(BinaryOperator &I) {
2426 unsigned ResultReg = getReg(I);
2428 Value *Op0 = I.getOperand(0);
2429 Value *Op1 = I.getOperand(1);
2431 // Fold loads into floating point multiplies.
2432 if (getClass(Op0->getType()) == cFP) {
2433 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1))
2434 if (!I.swapOperands())
2435 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
2436 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2437 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2438 const Type *Ty = Op0->getType();
2439 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2440 unsigned Opcode = Ty == Type::FloatTy ? X86::FMUL32m : X86::FMUL64m;
2442 unsigned Op0r = getReg(Op0);
2443 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2444 unsigned FI = getFixedSizedAllocaFI(AI);
2445 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
2447 unsigned BaseReg, Scale, IndexReg, Disp;
2448 getAddressingMode(LI->getOperand(0), BaseReg,
2449 Scale, IndexReg, Disp);
2451 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r),
2452 BaseReg, Scale, IndexReg, Disp);
2458 MachineBasicBlock::iterator IP = BB->end();
2459 emitMultiply(BB, IP, Op0, Op1, ResultReg);
2462 void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
2463 Value *Op0, Value *Op1, unsigned DestReg) {
2464 MachineBasicBlock &BB = *MBB;
2465 TypeClass Class = getClass(Op0->getType());
2467 // Simple scalar multiply?
2468 unsigned Op0Reg = getReg(Op0, &BB, IP);
2473 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2474 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
2475 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
2477 unsigned Op1Reg = getReg(Op1, &BB, IP);
2478 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
2482 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
2488 // Long value. We have to do things the hard way...
2489 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2490 unsigned CLow = CI->getRawValue();
2491 unsigned CHi = CI->getRawValue() >> 32;
2494 // If the low part of the constant is all zeros, things are simple.
2495 BuildMI(BB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2496 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
2500 // Multiply the two low parts... capturing carry into EDX
2501 unsigned OverflowReg = 0;
2503 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0Reg);
2505 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
2506 OverflowReg = makeAnotherReg(Type::UIntTy);
2507 BuildMI(BB, IP, X86::MOV32ri, 1, Op1RegL).addImm(CLow);
2508 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2509 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1RegL); // AL*BL
2511 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2512 BuildMI(BB, IP, X86::MOV32rr, 1,
2513 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2516 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2517 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
2519 unsigned AHBLplusOverflowReg;
2521 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2522 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2523 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2525 AHBLplusOverflowReg = AHBLReg;
2529 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(AHBLplusOverflowReg);
2531 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2532 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
2534 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2535 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2540 // General 64x64 multiply
2542 unsigned Op1Reg = getReg(Op1, &BB, IP);
2543 // Multiply the two low parts... capturing carry into EDX
2544 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2545 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1Reg); // AL*BL
2547 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
2548 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2549 BuildMI(BB, IP, X86::MOV32rr, 1,
2550 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2552 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2553 BuildMI(BB, IP, X86::IMUL32rr, 2,
2554 AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
2556 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2557 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2558 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2560 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2561 BuildMI(BB, IP, X86::IMUL32rr, 2,
2562 ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
2564 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2565 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2569 /// visitDivRem - Handle division and remainder instructions... these
2570 /// instruction both require the same instructions to be generated, they just
2571 /// select the result from a different register. Note that both of these
2572 /// instructions work differently for signed and unsigned operands.
2574 void ISel::visitDivRem(BinaryOperator &I) {
2575 unsigned ResultReg = getReg(I);
2576 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
2578 // Fold loads into floating point divides.
2579 if (getClass(Op0->getType()) == cFP) {
2580 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2581 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2582 const Type *Ty = Op0->getType();
2583 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2584 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIV32m : X86::FDIV64m;
2586 unsigned Op0r = getReg(Op0);
2587 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2588 unsigned FI = getFixedSizedAllocaFI(AI);
2589 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
2591 unsigned BaseReg, Scale, IndexReg, Disp;
2592 getAddressingMode(LI->getOperand(0), BaseReg,
2593 Scale, IndexReg, Disp);
2595 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r),
2596 BaseReg, Scale, IndexReg, Disp);
2601 if (LoadInst *LI = dyn_cast<LoadInst>(Op0))
2602 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2603 const Type *Ty = Op0->getType();
2604 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2605 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIVR32m : X86::FDIVR64m;
2607 unsigned Op1r = getReg(Op1);
2608 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2609 unsigned FI = getFixedSizedAllocaFI(AI);
2610 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r), FI);
2612 unsigned BaseReg, Scale, IndexReg, Disp;
2613 getAddressingMode(LI->getOperand(0), BaseReg, Scale, IndexReg, Disp);
2614 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r),
2615 BaseReg, Scale, IndexReg, Disp);
2622 MachineBasicBlock::iterator IP = BB->end();
2623 emitDivRemOperation(BB, IP, Op0, Op1,
2624 I.getOpcode() == Instruction::Div, ResultReg);
2627 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
2628 MachineBasicBlock::iterator IP,
2629 Value *Op0, Value *Op1, bool isDiv,
2630 unsigned ResultReg) {
2631 const Type *Ty = Op0->getType();
2632 unsigned Class = getClass(Ty);
2634 case cFP: // Floating point divide
2636 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
2638 } else { // Floating point remainder...
2639 unsigned Op0Reg = getReg(Op0, BB, IP);
2640 unsigned Op1Reg = getReg(Op1, BB, IP);
2641 MachineInstr *TheCall =
2642 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
2643 std::vector<ValueRecord> Args;
2644 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
2645 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
2646 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
2650 static const char *FnName[] =
2651 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
2652 unsigned Op0Reg = getReg(Op0, BB, IP);
2653 unsigned Op1Reg = getReg(Op1, BB, IP);
2654 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
2655 MachineInstr *TheCall =
2656 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
2658 std::vector<ValueRecord> Args;
2659 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
2660 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
2661 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
2664 case cByte: case cShort: case cInt:
2665 break; // Small integrals, handled below...
2666 default: assert(0 && "Unknown class!");
2669 static const unsigned MovOpcode[]={ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr };
2670 static const unsigned NEGOpcode[] = { X86::NEG8r, X86::NEG16r, X86::NEG32r };
2671 static const unsigned SAROpcode[]={ X86::SAR8ri, X86::SAR16ri, X86::SAR32ri };
2672 static const unsigned SHROpcode[]={ X86::SHR8ri, X86::SHR16ri, X86::SHR32ri };
2673 static const unsigned ADDOpcode[]={ X86::ADD8rr, X86::ADD16rr, X86::ADD32rr };
2675 // Special case signed division by power of 2.
2677 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
2678 assert(Class != cLong && "This doesn't handle 64-bit divides!");
2679 int V = CI->getValue();
2681 if (V == 1) { // X /s 1 => X
2682 unsigned Op0Reg = getReg(Op0, BB, IP);
2683 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(Op0Reg);
2687 if (V == -1) { // X /s -1 => -X
2688 unsigned Op0Reg = getReg(Op0, BB, IP);
2689 BuildMI(*BB, IP, NEGOpcode[Class], 1, ResultReg).addReg(Op0Reg);
2694 if (V < 0) { // Not a positive power of 2?
2696 isNeg = true; // Maybe it's a negative power of 2.
2698 if (unsigned Log = ExactLog2(V)) {
2700 unsigned Op0Reg = getReg(Op0, BB, IP);
2701 unsigned TmpReg = makeAnotherReg(Op0->getType());
2703 BuildMI(*BB, IP, SAROpcode[Class], 2, TmpReg)
2704 .addReg(Op0Reg).addImm(Log-1);
2706 BuildMI(*BB, IP, MovOpcode[Class], 1, TmpReg).addReg(Op0Reg);
2707 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2708 BuildMI(*BB, IP, SHROpcode[Class], 2, TmpReg2)
2709 .addReg(TmpReg).addImm(32-Log);
2710 unsigned TmpReg3 = makeAnotherReg(Op0->getType());
2711 BuildMI(*BB, IP, ADDOpcode[Class], 2, TmpReg3)
2712 .addReg(Op0Reg).addReg(TmpReg2);
2714 unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
2715 BuildMI(*BB, IP, SAROpcode[Class], 2, TmpReg4)
2716 .addReg(Op0Reg).addImm(Log);
2718 BuildMI(*BB, IP, NEGOpcode[Class], 1, ResultReg).addReg(TmpReg4);
2723 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
2724 static const unsigned ClrOpcode[]={ X86::MOV8ri, X86::MOV16ri, X86::MOV32ri };
2725 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
2727 static const unsigned DivOpcode[][4] = {
2728 { X86::DIV8r , X86::DIV16r , X86::DIV32r , 0 }, // Unsigned division
2729 { X86::IDIV8r, X86::IDIV16r, X86::IDIV32r, 0 }, // Signed division
2732 unsigned Reg = Regs[Class];
2733 unsigned ExtReg = ExtRegs[Class];
2735 // Put the first operand into one of the A registers...
2736 unsigned Op0Reg = getReg(Op0, BB, IP);
2737 unsigned Op1Reg = getReg(Op1, BB, IP);
2738 BuildMI(*BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
2740 if (Ty->isSigned()) {
2741 // Emit a sign extension instruction...
2742 unsigned ShiftResult = makeAnotherReg(Op0->getType());
2743 BuildMI(*BB, IP, SAROpcode[Class], 2,ShiftResult).addReg(Op0Reg).addImm(31);
2744 BuildMI(*BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
2746 // Emit the appropriate divide or remainder instruction...
2747 BuildMI(*BB, IP, DivOpcode[1][Class], 1).addReg(Op1Reg);
2749 // If unsigned, emit a zeroing instruction... (reg = 0)
2750 BuildMI(*BB, IP, ClrOpcode[Class], 2, ExtReg).addImm(0);
2752 // Emit the appropriate divide or remainder instruction...
2753 BuildMI(*BB, IP, DivOpcode[0][Class], 1).addReg(Op1Reg);
2756 // Figure out which register we want to pick the result out of...
2757 unsigned DestReg = isDiv ? Reg : ExtReg;
2759 // Put the result into the destination register...
2760 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
2764 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2765 /// for constant immediate shift values, and for constant immediate
2766 /// shift values equal to 1. Even the general case is sort of special,
2767 /// because the shift amount has to be in CL, not just any old register.
2769 void ISel::visitShiftInst(ShiftInst &I) {
2770 MachineBasicBlock::iterator IP = BB->end ();
2771 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
2772 I.getOpcode () == Instruction::Shl, I.getType (),
2776 /// emitShiftOperation - Common code shared between visitShiftInst and
2777 /// constant expression support.
2778 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2779 MachineBasicBlock::iterator IP,
2780 Value *Op, Value *ShiftAmount, bool isLeftShift,
2781 const Type *ResultTy, unsigned DestReg) {
2782 unsigned SrcReg = getReg (Op, MBB, IP);
2783 bool isSigned = ResultTy->isSigned ();
2784 unsigned Class = getClass (ResultTy);
2786 static const unsigned ConstantOperand[][4] = {
2787 { X86::SHR8ri, X86::SHR16ri, X86::SHR32ri, X86::SHRD32rri8 }, // SHR
2788 { X86::SAR8ri, X86::SAR16ri, X86::SAR32ri, X86::SHRD32rri8 }, // SAR
2789 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SHL
2790 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SAL = SHL
2793 static const unsigned NonConstantOperand[][4] = {
2794 { X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL }, // SHR
2795 { X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL }, // SAR
2796 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SHL
2797 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SAL = SHL
2800 // Longs, as usual, are handled specially...
2801 if (Class == cLong) {
2802 // If we have a constant shift, we can generate much more efficient code
2803 // than otherwise...
2805 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2806 unsigned Amount = CUI->getValue();
2808 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2810 BuildMI(*MBB, IP, Opc[3], 3,
2811 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addImm(Amount);
2812 BuildMI(*MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addImm(Amount);
2814 BuildMI(*MBB, IP, Opc[3], 3,
2815 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addImm(Amount);
2816 BuildMI(*MBB, IP, Opc[2],2,DestReg+1).addReg(SrcReg+1).addImm(Amount);
2818 } else { // Shifting more than 32 bits
2822 BuildMI(*MBB, IP, X86::SHL32ri, 2,
2823 DestReg + 1).addReg(SrcReg).addImm(Amount);
2825 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg);
2827 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2830 BuildMI(*MBB, IP, isSigned ? X86::SAR32ri : X86::SHR32ri, 2,
2831 DestReg).addReg(SrcReg+1).addImm(Amount);
2833 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg+1);
2835 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2839 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2841 if (!isLeftShift && isSigned) {
2842 // If this is a SHR of a Long, then we need to do funny sign extension
2843 // stuff. TmpReg gets the value to use as the high-part if we are
2844 // shifting more than 32 bits.
2845 BuildMI(*MBB, IP, X86::SAR32ri, 2, TmpReg).addReg(SrcReg).addImm(31);
2847 // Other shifts use a fixed zero value if the shift is more than 32
2849 BuildMI(*MBB, IP, X86::MOV32ri, 1, TmpReg).addImm(0);
2852 // Initialize CL with the shift amount...
2853 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
2854 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2856 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2857 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2859 // TmpReg2 = shld inHi, inLo
2860 BuildMI(*MBB, IP, X86::SHLD32rrCL,2,TmpReg2).addReg(SrcReg+1)
2862 // TmpReg3 = shl inLo, CL
2863 BuildMI(*MBB, IP, X86::SHL32rCL, 1, TmpReg3).addReg(SrcReg);
2865 // Set the flags to indicate whether the shift was by more than 32 bits.
2866 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2868 // DestHi = (>32) ? TmpReg3 : TmpReg2;
2869 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2870 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
2871 // DestLo = (>32) ? TmpReg : TmpReg3;
2872 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2873 DestReg).addReg(TmpReg3).addReg(TmpReg);
2875 // TmpReg2 = shrd inLo, inHi
2876 BuildMI(*MBB, IP, X86::SHRD32rrCL,2,TmpReg2).addReg(SrcReg)
2878 // TmpReg3 = s[ah]r inHi, CL
2879 BuildMI(*MBB, IP, isSigned ? X86::SAR32rCL : X86::SHR32rCL, 1, TmpReg3)
2882 // Set the flags to indicate whether the shift was by more than 32 bits.
2883 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2885 // DestLo = (>32) ? TmpReg3 : TmpReg2;
2886 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2887 DestReg).addReg(TmpReg2).addReg(TmpReg3);
2889 // DestHi = (>32) ? TmpReg : TmpReg3;
2890 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2891 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
2897 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2898 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2899 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2901 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2902 BuildMI(*MBB, IP, Opc[Class], 2,
2903 DestReg).addReg(SrcReg).addImm(CUI->getValue());
2904 } else { // The shift amount is non-constant.
2905 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2906 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2908 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
2909 BuildMI(*MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
2914 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
2915 /// instruction. The load and store instructions are the only place where we
2916 /// need to worry about the memory layout of the target machine.
2918 void ISel::visitLoadInst(LoadInst &I) {
2919 // Check to see if this load instruction is going to be folded into a binary
2920 // instruction, like add. If so, we don't want to emit it. Wouldn't a real
2921 // pattern matching instruction selector be nice?
2922 unsigned Class = getClassB(I.getType());
2923 if (I.hasOneUse()) {
2924 Instruction *User = cast<Instruction>(I.use_back());
2925 switch (User->getOpcode()) {
2926 case Instruction::Cast:
2927 // If this is a cast from a signed-integer type to a floating point type,
2928 // fold the cast here.
2929 if (getClassB(User->getType()) == cFP &&
2930 (I.getType() == Type::ShortTy || I.getType() == Type::IntTy ||
2931 I.getType() == Type::LongTy)) {
2932 unsigned DestReg = getReg(User);
2933 static const unsigned Opcode[] = {
2934 0/*BYTE*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m
2937 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
2938 unsigned FI = getFixedSizedAllocaFI(AI);
2939 addFrameReference(BuildMI(BB, Opcode[Class], 4, DestReg), FI);
2941 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
2942 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
2943 addFullAddress(BuildMI(BB, Opcode[Class], 4, DestReg),
2944 BaseReg, Scale, IndexReg, Disp);
2952 case Instruction::Add:
2953 case Instruction::Sub:
2954 case Instruction::And:
2955 case Instruction::Or:
2956 case Instruction::Xor:
2957 if (Class == cLong) User = 0;
2959 case Instruction::Mul:
2960 case Instruction::Div:
2961 if (Class != cFP) User = 0;
2962 break; // Folding only implemented for floating point.
2963 default: User = 0; break;
2967 // Okay, we found a user. If the load is the first operand and there is
2968 // no second operand load, reverse the operand ordering. Note that this
2969 // can fail for a subtract (ie, no change will be made).
2970 bool Swapped = false;
2971 if (!isa<LoadInst>(User->getOperand(1)))
2972 Swapped = !cast<BinaryOperator>(User)->swapOperands();
2974 // Okay, now that everything is set up, if this load is used by the second
2975 // operand, and if there are no instructions that invalidate the load
2976 // before the binary operator, eliminate the load.
2977 if (User->getOperand(1) == &I &&
2978 isSafeToFoldLoadIntoInstruction(I, *User))
2979 return; // Eliminate the load!
2981 // If this is a floating point sub or div, we won't be able to swap the
2982 // operands, but we will still be able to eliminate the load.
2983 if (Class == cFP && User->getOperand(0) == &I &&
2984 !isa<LoadInst>(User->getOperand(1)) &&
2985 (User->getOpcode() == Instruction::Sub ||
2986 User->getOpcode() == Instruction::Div) &&
2987 isSafeToFoldLoadIntoInstruction(I, *User))
2988 return; // Eliminate the load!
2990 // If we swapped the operands to the instruction, but couldn't fold the
2991 // load anyway, swap them back. We don't want to break add X, int
2993 if (Swapped) cast<BinaryOperator>(User)->swapOperands();
2997 static const unsigned Opcodes[] = {
2998 X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m, X86::MOV32rm
3000 unsigned Opcode = Opcodes[Class];
3001 if (I.getType() == Type::DoubleTy) Opcode = X86::FLD64m;
3003 unsigned DestReg = getReg(I);
3005 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
3006 unsigned FI = getFixedSizedAllocaFI(AI);
3007 if (Class == cLong) {
3008 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, DestReg), FI);
3009 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), FI, 4);
3011 addFrameReference(BuildMI(BB, Opcode, 4, DestReg), FI);
3014 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
3015 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
3017 if (Class == cLong) {
3018 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg),
3019 BaseReg, Scale, IndexReg, Disp);
3020 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1),
3021 BaseReg, Scale, IndexReg, Disp+4);
3023 addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
3024 BaseReg, Scale, IndexReg, Disp);
3029 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
3032 void ISel::visitStoreInst(StoreInst &I) {
3033 unsigned BaseReg = ~0U, Scale = ~0U, IndexReg = ~0U, Disp = ~0U;
3034 unsigned AllocaFrameIdx = ~0U;
3036 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(1)))
3037 AllocaFrameIdx = getFixedSizedAllocaFI(AI);
3039 getAddressingMode(I.getOperand(1), BaseReg, Scale, IndexReg, Disp);
3041 const Type *ValTy = I.getOperand(0)->getType();
3042 unsigned Class = getClassB(ValTy);
3044 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
3045 uint64_t Val = CI->getRawValue();
3046 if (Class == cLong) {
3047 if (AllocaFrameIdx != ~0U) {
3048 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3049 AllocaFrameIdx).addImm(Val & ~0U);
3050 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3051 AllocaFrameIdx, 4).addImm(Val>>32);
3053 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3054 BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U);
3055 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3056 BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32);
3059 static const unsigned Opcodes[] = {
3060 X86::MOV8mi, X86::MOV16mi, X86::MOV32mi
3062 unsigned Opcode = Opcodes[Class];
3063 if (AllocaFrameIdx != ~0U)
3064 addFrameReference(BuildMI(BB, Opcode, 5), AllocaFrameIdx).addImm(Val);
3066 addFullAddress(BuildMI(BB, Opcode, 5),
3067 BaseReg, Scale, IndexReg, Disp).addImm(Val);
3069 } else if (isa<ConstantPointerNull>(I.getOperand(0))) {
3070 if (AllocaFrameIdx != ~0U)
3071 addFrameReference(BuildMI(BB, X86::MOV32mi, 5), AllocaFrameIdx).addImm(0);
3073 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3074 BaseReg, Scale, IndexReg, Disp).addImm(0);
3076 } else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
3077 if (AllocaFrameIdx != ~0U)
3078 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
3079 AllocaFrameIdx).addImm(CB->getValue());
3081 addFullAddress(BuildMI(BB, X86::MOV8mi, 5),
3082 BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue());
3083 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) {
3084 // Store constant FP values with integer instructions to avoid having to
3085 // load the constants from the constant pool then do a store.
3086 if (CFP->getType() == Type::FloatTy) {
3091 V.F = CFP->getValue();
3092 if (AllocaFrameIdx != ~0U)
3093 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3094 AllocaFrameIdx).addImm(V.I);
3096 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3097 BaseReg, Scale, IndexReg, Disp).addImm(V.I);
3103 V.F = CFP->getValue();
3104 if (AllocaFrameIdx != ~0U) {
3105 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3106 AllocaFrameIdx).addImm((unsigned)V.I);
3107 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3108 AllocaFrameIdx, 4).addImm(unsigned(V.I >> 32));
3110 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3111 BaseReg, Scale, IndexReg, Disp).addImm((unsigned)V.I);
3112 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3113 BaseReg, Scale, IndexReg, Disp+4).addImm(
3114 unsigned(V.I >> 32));
3118 } else if (Class == cLong) {
3119 unsigned ValReg = getReg(I.getOperand(0));
3120 if (AllocaFrameIdx != ~0U) {
3121 addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
3122 AllocaFrameIdx).addReg(ValReg);
3123 addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
3124 AllocaFrameIdx, 4).addReg(ValReg+1);
3126 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
3127 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
3128 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
3129 BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
3132 unsigned ValReg = getReg(I.getOperand(0));
3133 static const unsigned Opcodes[] = {
3134 X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST32m
3136 unsigned Opcode = Opcodes[Class];
3137 if (ValTy == Type::DoubleTy) Opcode = X86::FST64m;
3139 if (AllocaFrameIdx != ~0U)
3140 addFrameReference(BuildMI(BB, Opcode, 5), AllocaFrameIdx).addReg(ValReg);
3142 addFullAddress(BuildMI(BB, Opcode, 1+4),
3143 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
3148 /// visitCastInst - Here we have various kinds of copying with or without sign
3149 /// extension going on.
3151 void ISel::visitCastInst(CastInst &CI) {
3152 Value *Op = CI.getOperand(0);
3154 unsigned SrcClass = getClassB(Op->getType());
3155 unsigned DestClass = getClassB(CI.getType());
3156 // Noop casts are not emitted: getReg will return the source operand as the
3157 // register to use for any uses of the noop cast.
3158 if (DestClass == SrcClass) {
3159 // The only detail in this plan is that casts from double -> float are
3160 // truncating operations that we have to codegen through memory (despite
3161 // the fact that the source/dest registers are the same class).
3162 if (CI.getType() != Type::FloatTy || Op->getType() != Type::DoubleTy)
3166 // If this is a cast from a 32-bit integer to a Long type, and the only uses
3167 // of the case are GEP instructions, then the cast does not need to be
3168 // generated explicitly, it will be folded into the GEP.
3169 if (DestClass == cLong && SrcClass == cInt) {
3170 bool AllUsesAreGEPs = true;
3171 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
3172 if (!isa<GetElementPtrInst>(*I)) {
3173 AllUsesAreGEPs = false;
3177 // No need to codegen this cast if all users are getelementptr instrs...
3178 if (AllUsesAreGEPs) return;
3181 // If this cast converts a load from a short,int, or long integer to a FP
3182 // value, we will have folded this cast away.
3183 if (DestClass == cFP && isa<LoadInst>(Op) && Op->hasOneUse() &&
3184 (Op->getType() == Type::ShortTy || Op->getType() == Type::IntTy ||
3185 Op->getType() == Type::LongTy))
3189 unsigned DestReg = getReg(CI);
3190 MachineBasicBlock::iterator MI = BB->end();
3191 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
3194 /// emitCastOperation - Common code shared between visitCastInst and constant
3195 /// expression cast support.
3197 void ISel::emitCastOperation(MachineBasicBlock *BB,
3198 MachineBasicBlock::iterator IP,
3199 Value *Src, const Type *DestTy,
3201 const Type *SrcTy = Src->getType();
3202 unsigned SrcClass = getClassB(SrcTy);
3203 unsigned DestClass = getClassB(DestTy);
3204 unsigned SrcReg = getReg(Src, BB, IP);
3206 // Implement casts to bool by using compare on the operand followed by set if
3207 // not zero on the result.
3208 if (DestTy == Type::BoolTy) {
3211 BuildMI(*BB, IP, X86::TEST8rr, 2).addReg(SrcReg).addReg(SrcReg);
3214 BuildMI(*BB, IP, X86::TEST16rr, 2).addReg(SrcReg).addReg(SrcReg);
3217 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg).addReg(SrcReg);
3220 unsigned TmpReg = makeAnotherReg(Type::IntTy);
3221 BuildMI(*BB, IP, X86::OR32rr, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
3225 BuildMI(*BB, IP, X86::FTST, 1).addReg(SrcReg);
3226 BuildMI(*BB, IP, X86::FNSTSW8r, 0);
3227 BuildMI(*BB, IP, X86::SAHF, 1);
3231 // If the zero flag is not set, then the value is true, set the byte to
3233 BuildMI(*BB, IP, X86::SETNEr, 1, DestReg);
3237 static const unsigned RegRegMove[] = {
3238 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
3241 // Implement casts between values of the same type class (as determined by
3242 // getClass) by using a register-to-register move.
3243 if (SrcClass == DestClass) {
3244 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
3245 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
3246 } else if (SrcClass == cFP) {
3247 if (SrcTy == Type::FloatTy) { // double -> float
3248 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
3249 BuildMI(*BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
3250 } else { // float -> double
3251 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
3252 "Unknown cFP member!");
3253 // Truncate from double to float by storing to memory as short, then
3255 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
3256 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
3257 addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5), FrameIdx).addReg(SrcReg);
3258 addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx);
3260 } else if (SrcClass == cLong) {
3261 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
3262 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg+1);
3264 assert(0 && "Cannot handle this type of cast instruction!");
3270 // Handle cast of SMALLER int to LARGER int using a move with sign extension
3271 // or zero extension, depending on whether the source type was signed.
3272 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
3273 SrcClass < DestClass) {
3274 bool isLong = DestClass == cLong;
3275 if (isLong) DestClass = cInt;
3277 static const unsigned Opc[][4] = {
3278 { X86::MOVSX16rr8, X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOV32rr }, // s
3279 { X86::MOVZX16rr8, X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOV32rr } // u
3282 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
3283 BuildMI(*BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
3284 DestReg).addReg(SrcReg);
3286 if (isLong) { // Handle upper 32 bits as appropriate...
3287 if (isUnsigned) // Zero out top bits...
3288 BuildMI(*BB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
3289 else // Sign extend bottom half...
3290 BuildMI(*BB, IP, X86::SAR32ri, 2, DestReg+1).addReg(DestReg).addImm(31);
3295 // Special case long -> int ...
3296 if (SrcClass == cLong && DestClass == cInt) {
3297 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
3301 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
3302 // move out of AX or AL.
3303 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
3304 && SrcClass > DestClass) {
3305 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
3306 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
3307 BuildMI(*BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
3311 // Handle casts from integer to floating point now...
3312 if (DestClass == cFP) {
3313 // Promote the integer to a type supported by FLD. We do this because there
3314 // are no unsigned FLD instructions, so we must promote an unsigned value to
3315 // a larger signed value, then use FLD on the larger value.
3317 const Type *PromoteType = 0;
3318 unsigned PromoteOpcode = 0;
3319 unsigned RealDestReg = DestReg;
3320 switch (SrcTy->getTypeID()) {
3321 case Type::BoolTyID:
3322 case Type::SByteTyID:
3323 // We don't have the facilities for directly loading byte sized data from
3324 // memory (even signed). Promote it to 16 bits.
3325 PromoteType = Type::ShortTy;
3326 PromoteOpcode = X86::MOVSX16rr8;
3328 case Type::UByteTyID:
3329 PromoteType = Type::ShortTy;
3330 PromoteOpcode = X86::MOVZX16rr8;
3332 case Type::UShortTyID:
3333 PromoteType = Type::IntTy;
3334 PromoteOpcode = X86::MOVZX32rr16;
3336 case Type::UIntTyID: {
3337 // Make a 64 bit temporary... and zero out the top of it...
3338 unsigned TmpReg = makeAnotherReg(Type::LongTy);
3339 BuildMI(*BB, IP, X86::MOV32rr, 1, TmpReg).addReg(SrcReg);
3340 BuildMI(*BB, IP, X86::MOV32ri, 1, TmpReg+1).addImm(0);
3341 SrcTy = Type::LongTy;
3346 case Type::ULongTyID:
3347 // Don't fild into the read destination.
3348 DestReg = makeAnotherReg(Type::DoubleTy);
3350 default: // No promotion needed...
3355 unsigned TmpReg = makeAnotherReg(PromoteType);
3356 BuildMI(*BB, IP, PromoteOpcode, 1, TmpReg).addReg(SrcReg);
3357 SrcTy = PromoteType;
3358 SrcClass = getClass(PromoteType);
3362 // Spill the integer to memory and reload it from there...
3364 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
3366 if (SrcClass == cLong) {
3367 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
3368 FrameIdx).addReg(SrcReg);
3369 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
3370 FrameIdx, 4).addReg(SrcReg+1);
3372 static const unsigned Op1[] = { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr };
3373 addFrameReference(BuildMI(*BB, IP, Op1[SrcClass], 5),
3374 FrameIdx).addReg(SrcReg);
3377 static const unsigned Op2[] =
3378 { 0/*byte*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m };
3379 addFrameReference(BuildMI(*BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
3381 // We need special handling for unsigned 64-bit integer sources. If the
3382 // input number has the "sign bit" set, then we loaded it incorrectly as a
3383 // negative 64-bit number. In this case, add an offset value.
3384 if (SrcTy == Type::ULongTy) {
3385 // Emit a test instruction to see if the dynamic input value was signed.
3386 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg+1).addReg(SrcReg+1);
3388 // If the sign bit is set, get a pointer to an offset, otherwise get a
3389 // pointer to a zero.
3390 MachineConstantPool *CP = F->getConstantPool();
3391 unsigned Zero = makeAnotherReg(Type::IntTy);
3392 Constant *Null = Constant::getNullValue(Type::UIntTy);
3393 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero),
3394 CP->getConstantPoolIndex(Null));
3395 unsigned Offset = makeAnotherReg(Type::IntTy);
3396 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
3398 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Offset),
3399 CP->getConstantPoolIndex(OffsetCst));
3400 unsigned Addr = makeAnotherReg(Type::IntTy);
3401 BuildMI(*BB, IP, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset);
3403 // Load the constant for an add. FIXME: this could make an 'fadd' that
3404 // reads directly from memory, but we don't support these yet.
3405 unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
3406 addDirectMem(BuildMI(*BB, IP, X86::FLD32m, 4, ConstReg), Addr);
3408 BuildMI(*BB, IP, X86::FpADD, 2, RealDestReg)
3409 .addReg(ConstReg).addReg(DestReg);
3415 // Handle casts from floating point to integer now...
3416 if (SrcClass == cFP) {
3417 // Change the floating point control register to use "round towards zero"
3418 // mode when truncating to an integer value.
3420 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
3421 addFrameReference(BuildMI(*BB, IP, X86::FNSTCW16m, 4), CWFrameIdx);
3423 // Load the old value of the high byte of the control word...
3424 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
3425 addFrameReference(BuildMI(*BB, IP, X86::MOV8rm, 4, HighPartOfCW),
3428 // Set the high part to be round to zero...
3429 addFrameReference(BuildMI(*BB, IP, X86::MOV8mi, 5),
3430 CWFrameIdx, 1).addImm(12);
3432 // Reload the modified control word now...
3433 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
3435 // Restore the memory image of control word to original value
3436 addFrameReference(BuildMI(*BB, IP, X86::MOV8mr, 5),
3437 CWFrameIdx, 1).addReg(HighPartOfCW);
3439 // We don't have the facilities for directly storing byte sized data to
3440 // memory. Promote it to 16 bits. We also must promote unsigned values to
3441 // larger classes because we only have signed FP stores.
3442 unsigned StoreClass = DestClass;
3443 const Type *StoreTy = DestTy;
3444 if (StoreClass == cByte || DestTy->isUnsigned())
3445 switch (StoreClass) {
3446 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
3447 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
3448 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
3449 // The following treatment of cLong may not be perfectly right,
3450 // but it survives chains of casts of the form
3451 // double->ulong->double.
3452 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
3453 default: assert(0 && "Unknown store class!");
3456 // Spill the integer to memory and reload it from there...
3458 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
3460 static const unsigned Op1[] =
3461 { 0, X86::FIST16m, X86::FIST32m, 0, X86::FISTP64m };
3462 addFrameReference(BuildMI(*BB, IP, Op1[StoreClass], 5),
3463 FrameIdx).addReg(SrcReg);
3465 if (DestClass == cLong) {
3466 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg), FrameIdx);
3467 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg+1),
3470 static const unsigned Op2[] = { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm };
3471 addFrameReference(BuildMI(*BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
3474 // Reload the original control word now...
3475 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
3479 // Anything we haven't handled already, we can't (yet) handle at all.
3480 assert(0 && "Unhandled cast instruction!");
3484 /// visitVANextInst - Implement the va_next instruction...
3486 void ISel::visitVANextInst(VANextInst &I) {
3487 unsigned VAList = getReg(I.getOperand(0));
3488 unsigned DestReg = getReg(I);
3491 switch (I.getArgType()->getTypeID()) {
3494 assert(0 && "Error: bad type for va_next instruction!");
3496 case Type::PointerTyID:
3497 case Type::UIntTyID:
3501 case Type::ULongTyID:
3502 case Type::LongTyID:
3503 case Type::DoubleTyID:
3508 // Increment the VAList pointer...
3509 BuildMI(BB, X86::ADD32ri, 2, DestReg).addReg(VAList).addImm(Size);
3512 void ISel::visitVAArgInst(VAArgInst &I) {
3513 unsigned VAList = getReg(I.getOperand(0));
3514 unsigned DestReg = getReg(I);
3516 switch (I.getType()->getTypeID()) {
3519 assert(0 && "Error: bad type for va_next instruction!");
3521 case Type::PointerTyID:
3522 case Type::UIntTyID:
3524 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3526 case Type::ULongTyID:
3527 case Type::LongTyID:
3528 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3529 addRegOffset(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), VAList, 4);
3531 case Type::DoubleTyID:
3532 addDirectMem(BuildMI(BB, X86::FLD64m, 4, DestReg), VAList);
3537 /// visitGetElementPtrInst - instruction-select GEP instructions
3539 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
3540 // If this GEP instruction will be folded into all of its users, we don't need
3541 // to explicitly calculate it!
3542 unsigned A, B, C, D;
3543 if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) {
3544 // Check all of the users of the instruction to see if they are loads and
3546 bool AllWillFold = true;
3547 for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI)
3548 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Load)
3549 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Store ||
3550 cast<Instruction>(*UI)->getOperand(0) == &I) {
3551 AllWillFold = false;
3555 // If the instruction is foldable, and will be folded into all users, don't
3557 if (AllWillFold) return;
3560 unsigned outputReg = getReg(I);
3561 emitGEPOperation(BB, BB->end(), I.getOperand(0),
3562 I.op_begin()+1, I.op_end(), outputReg);
3565 /// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and
3566 /// GEPTypes (the derived types being stepped through at each level). On return
3567 /// from this function, if some indexes of the instruction are representable as
3568 /// an X86 lea instruction, the machine operands are put into the Ops
3569 /// instruction and the consumed indexes are poped from the GEPOps/GEPTypes
3570 /// lists. Otherwise, GEPOps.size() is returned. If this returns a an
3571 /// addressing mode that only partially consumes the input, the BaseReg input of
3572 /// the addressing mode must be left free.
3574 /// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
3576 void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
3577 std::vector<Value*> &GEPOps,
3578 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
3579 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
3580 const TargetData &TD = TM.getTargetData();
3582 // Clear out the state we are working with...
3583 BaseReg = 0; // No base register
3584 Scale = 1; // Unit scale
3585 IndexReg = 0; // No index register
3586 Disp = 0; // No displacement
3588 // While there are GEP indexes that can be folded into the current address,
3589 // keep processing them.
3590 while (!GEPTypes.empty()) {
3591 if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
3592 // It's a struct access. CUI is the index into the structure,
3593 // which names the field. This index must have unsigned type.
3594 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
3596 // Use the TargetData structure to pick out what the layout of the
3597 // structure is in memory. Since the structure index must be constant, we
3598 // can get its value and use it to find the right byte offset from the
3599 // StructLayout class's list of structure member offsets.
3600 Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
3601 GEPOps.pop_back(); // Consume a GEP operand
3602 GEPTypes.pop_back();
3604 // It's an array or pointer access: [ArraySize x ElementType].
3605 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3606 Value *idx = GEPOps.back();
3608 // idx is the index into the array. Unlike with structure
3609 // indices, we may not know its actual value at code-generation
3612 // If idx is a constant, fold it into the offset.
3613 unsigned TypeSize = TD.getTypeSize(SqTy->getElementType());
3614 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
3615 Disp += TypeSize*CSI->getValue();
3616 } else if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(idx)) {
3617 Disp += TypeSize*CUI->getValue();
3619 // If the index reg is already taken, we can't handle this index.
3620 if (IndexReg) return;
3622 // If this is a size that we can handle, then add the index as
3624 case 1: case 2: case 4: case 8:
3625 // These are all acceptable scales on X86.
3629 // Otherwise, we can't handle this scale
3633 if (CastInst *CI = dyn_cast<CastInst>(idx))
3634 if (CI->getOperand(0)->getType() == Type::IntTy ||
3635 CI->getOperand(0)->getType() == Type::UIntTy)
3636 idx = CI->getOperand(0);
3638 IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
3641 GEPOps.pop_back(); // Consume a GEP operand
3642 GEPTypes.pop_back();
3646 // GEPTypes is empty, which means we have a single operand left. Set it as
3647 // the base register.
3649 assert(BaseReg == 0);
3651 #if 0 // FIXME: TODO!
3652 if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
3653 // FIXME: When we can add FrameIndex values as the first operand, we can
3654 // make GEP's of allocas MUCH more efficient!
3655 unsigned FI = getFixedSizedAllocaFI(AI);
3658 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
3659 // FIXME: When addressing modes are more powerful/correct, we could load
3660 // global addresses directly as 32-bit immediates.
3664 BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
3665 GEPOps.pop_back(); // Consume the last GEP operand
3669 /// isGEPFoldable - Return true if the specified GEP can be completely
3670 /// folded into the addressing mode of a load/store or lea instruction.
3671 bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
3672 Value *Src, User::op_iterator IdxBegin,
3673 User::op_iterator IdxEnd, unsigned &BaseReg,
3674 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
3676 std::vector<Value*> GEPOps;
3677 GEPOps.resize(IdxEnd-IdxBegin+1);
3679 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3681 std::vector<const Type*>
3682 GEPTypes(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3683 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
3685 MachineBasicBlock::iterator IP;
3686 if (MBB) IP = MBB->end();
3687 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
3689 // We can fold it away iff the getGEPIndex call eliminated all operands.
3690 return GEPOps.empty();
3693 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
3694 MachineBasicBlock::iterator IP,
3695 Value *Src, User::op_iterator IdxBegin,
3696 User::op_iterator IdxEnd, unsigned TargetReg) {
3697 const TargetData &TD = TM.getTargetData();
3699 // If this is a getelementptr null, with all constant integer indices, just
3700 // replace it with TargetReg = 42.
3701 if (isa<ConstantPointerNull>(Src)) {
3702 User::op_iterator I = IdxBegin;
3703 for (; I != IdxEnd; ++I)
3704 if (!isa<ConstantInt>(*I))
3706 if (I == IdxEnd) { // All constant indices
3707 unsigned Offset = TD.getIndexedOffset(Src->getType(),
3708 std::vector<Value*>(IdxBegin, IdxEnd));
3709 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addImm(Offset);
3714 std::vector<Value*> GEPOps;
3715 GEPOps.resize(IdxEnd-IdxBegin+1);
3717 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3719 std::vector<const Type*> GEPTypes;
3720 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3721 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
3723 // Keep emitting instructions until we consume the entire GEP instruction.
3724 while (!GEPOps.empty()) {
3725 unsigned OldSize = GEPOps.size();
3726 unsigned BaseReg, Scale, IndexReg, Disp;
3727 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
3729 if (GEPOps.size() != OldSize) {
3730 // getGEPIndex consumed some of the input. Build an LEA instruction here.
3731 unsigned NextTarget = 0;
3732 if (!GEPOps.empty()) {
3733 assert(BaseReg == 0 &&
3734 "getGEPIndex should have left the base register open for chaining!");
3735 NextTarget = BaseReg = makeAnotherReg(Type::UIntTy);
3738 if (IndexReg == 0 && Disp == 0)
3739 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
3741 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg),
3742 BaseReg, Scale, IndexReg, Disp);
3744 TargetReg = NextTarget;
3745 } else if (GEPTypes.empty()) {
3746 // The getGEPIndex operation didn't want to build an LEA. Check to see if
3747 // all operands are consumed but the base pointer. If so, just load it
3748 // into the register.
3749 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps[0])) {
3750 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addGlobalAddress(GV);
3752 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
3753 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
3755 break; // we are now done
3758 // It's an array or pointer access: [ArraySize x ElementType].
3759 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3760 Value *idx = GEPOps.back();
3761 GEPOps.pop_back(); // Consume a GEP operand
3762 GEPTypes.pop_back();
3764 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
3765 // operand on X86. Handle this case directly now...
3766 if (CastInst *CI = dyn_cast<CastInst>(idx))
3767 if (CI->getOperand(0)->getType() == Type::IntTy ||
3768 CI->getOperand(0)->getType() == Type::UIntTy)
3769 idx = CI->getOperand(0);
3771 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
3772 // must find the size of the pointed-to type (Not coincidentally, the next
3773 // type is the type of the elements in the array).
3774 const Type *ElTy = SqTy->getElementType();
3775 unsigned elementSize = TD.getTypeSize(ElTy);
3777 // If idxReg is a constant, we don't need to perform the multiply!
3778 if (ConstantInt *CSI = dyn_cast<ConstantInt>(idx)) {
3779 if (!CSI->isNullValue()) {
3780 unsigned Offset = elementSize*CSI->getRawValue();
3781 unsigned Reg = makeAnotherReg(Type::UIntTy);
3782 BuildMI(*MBB, IP, X86::ADD32ri, 2, TargetReg)
3783 .addReg(Reg).addImm(Offset);
3784 --IP; // Insert the next instruction before this one.
3785 TargetReg = Reg; // Codegen the rest of the GEP into this
3787 } else if (elementSize == 1) {
3788 // If the element size is 1, we don't have to multiply, just add
3789 unsigned idxReg = getReg(idx, MBB, IP);
3790 unsigned Reg = makeAnotherReg(Type::UIntTy);
3791 BuildMI(*MBB, IP, X86::ADD32rr, 2,TargetReg).addReg(Reg).addReg(idxReg);
3792 --IP; // Insert the next instruction before this one.
3793 TargetReg = Reg; // Codegen the rest of the GEP into this
3795 unsigned idxReg = getReg(idx, MBB, IP);
3796 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
3798 // Make sure we can back the iterator up to point to the first
3799 // instruction emitted.
3800 MachineBasicBlock::iterator BeforeIt = IP;
3801 if (IP == MBB->begin())
3802 BeforeIt = MBB->end();
3805 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
3807 // Emit an ADD to add OffsetReg to the basePtr.
3808 unsigned Reg = makeAnotherReg(Type::UIntTy);
3809 BuildMI(*MBB, IP, X86::ADD32rr, 2, TargetReg)
3810 .addReg(Reg).addReg(OffsetReg);
3812 // Step to the first instruction of the multiply.
3813 if (BeforeIt == MBB->end())
3818 TargetReg = Reg; // Codegen the rest of the GEP into this
3824 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
3825 /// frame manager, otherwise do it the hard way.
3827 void ISel::visitAllocaInst(AllocaInst &I) {
3828 // If this is a fixed size alloca in the entry block for the function, we
3829 // statically stack allocate the space, so we don't need to do anything here.
3831 if (dyn_castFixedAlloca(&I)) return;
3833 // Find the data size of the alloca inst's getAllocatedType.
3834 const Type *Ty = I.getAllocatedType();
3835 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
3837 // Create a register to hold the temporary result of multiplying the type size
3838 // constant by the variable amount.
3839 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
3840 unsigned SrcReg1 = getReg(I.getArraySize());
3842 // TotalSizeReg = mul <numelements>, <TypeSize>
3843 MachineBasicBlock::iterator MBBI = BB->end();
3844 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
3846 // AddedSize = add <TotalSizeReg>, 15
3847 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
3848 BuildMI(BB, X86::ADD32ri, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
3850 // AlignedSize = and <AddedSize>, ~15
3851 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
3852 BuildMI(BB, X86::AND32ri, 2, AlignedSize).addReg(AddedSizeReg).addImm(~15);
3854 // Subtract size from stack pointer, thereby allocating some space.
3855 BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
3857 // Put a pointer to the space into the result register, by copying
3858 // the stack pointer.
3859 BuildMI(BB, X86::MOV32rr, 1, getReg(I)).addReg(X86::ESP);
3861 // Inform the Frame Information that we have just allocated a variable-sized
3863 F->getFrameInfo()->CreateVariableSizedObject();
3866 /// visitMallocInst - Malloc instructions are code generated into direct calls
3867 /// to the library malloc.
3869 void ISel::visitMallocInst(MallocInst &I) {
3870 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
3873 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
3874 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
3876 Arg = makeAnotherReg(Type::UIntTy);
3877 unsigned Op0Reg = getReg(I.getOperand(0));
3878 MachineBasicBlock::iterator MBBI = BB->end();
3879 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
3882 std::vector<ValueRecord> Args;
3883 Args.push_back(ValueRecord(Arg, Type::UIntTy));
3884 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
3885 1).addExternalSymbol("malloc", true);
3886 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
3890 /// visitFreeInst - Free instructions are code gen'd to call the free libc
3893 void ISel::visitFreeInst(FreeInst &I) {
3894 std::vector<ValueRecord> Args;
3895 Args.push_back(ValueRecord(I.getOperand(0)));
3896 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
3897 1).addExternalSymbol("free", true);
3898 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
3901 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
3902 /// into a machine code representation is a very simple peep-hole fashion. The
3903 /// generated code sucks but the implementation is nice and simple.
3905 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
3906 return new ISel(TM);