1 //===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86IntelInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "MCTargetDesc/X86MCTargetDesc.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/FormattedStream.h"
27 #include "X86GenAsmWriter1.inc"
29 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
30 OS << getRegisterName(RegNo);
33 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
35 printInstruction(MI, OS);
37 // Next always print the annotation.
38 printAnnotation(OS, Annot);
40 // If verbose assembly is enabled, we can print some informative comments.
42 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
44 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
45 return MII.getName(Opcode);
48 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
50 switch (MI->getOperand(Op).getImm()) {
51 default: llvm_unreachable("Invalid ssecc argument!");
52 case 0: O << "eq"; break;
53 case 1: O << "lt"; break;
54 case 2: O << "le"; break;
55 case 3: O << "unord"; break;
56 case 4: O << "neq"; break;
57 case 5: O << "nlt"; break;
58 case 6: O << "nle"; break;
59 case 7: O << "ord"; break;
60 case 8: O << "eq_uq"; break;
61 case 9: O << "nge"; break;
62 case 0xa: O << "ngt"; break;
63 case 0xb: O << "false"; break;
64 case 0xc: O << "neq_oq"; break;
65 case 0xd: O << "ge"; break;
66 case 0xe: O << "gt"; break;
67 case 0xf: O << "true"; break;
68 case 0x10: O << "eq_os"; break;
69 case 0x11: O << "lt_oq"; break;
70 case 0x12: O << "le_oq"; break;
71 case 0x13: O << "unord_s"; break;
72 case 0x14: O << "neq_us"; break;
73 case 0x15: O << "nlt_uq"; break;
74 case 0x16: O << "nle_uq"; break;
75 case 0x17: O << "ord_s"; break;
76 case 0x18: O << "eq_us"; break;
77 case 0x19: O << "nge_uq"; break;
78 case 0x1a: O << "ngt_uq"; break;
79 case 0x1b: O << "false_os"; break;
80 case 0x1c: O << "neq_os"; break;
81 case 0x1d: O << "ge_oq"; break;
82 case 0x1e: O << "gt_oq"; break;
83 case 0x1f: O << "true_us"; break;
88 /// print_pcrel_imm - This is used to print an immediate value that ends up
89 /// being encoded as a pc-relative value.
90 void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
92 const MCOperand &Op = MI->getOperand(OpNo);
96 assert(Op.isExpr() && "unknown pcrel immediate operand");
97 // If a symbolic branch target was added as a constant expression then print
98 // that address in hex.
99 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
101 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
103 O.write_hex(Address);
106 // Otherwise, just print the expression.
112 static void PrintRegName(raw_ostream &O, StringRef RegName) {
113 for (unsigned i = 0, e = RegName.size(); i != e; ++i)
114 O << (char)toupper(RegName[i]);
117 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
119 const MCOperand &Op = MI->getOperand(OpNo);
121 PrintRegName(O, getRegisterName(Op.getReg()));
122 } else if (Op.isImm()) {
125 assert(Op.isExpr() && "unknown operand kind in printOperand");
130 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
132 const MCOperand &BaseReg = MI->getOperand(Op);
133 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
134 const MCOperand &IndexReg = MI->getOperand(Op+2);
135 const MCOperand &DispSpec = MI->getOperand(Op+3);
136 const MCOperand &SegReg = MI->getOperand(Op+4);
138 // If this has a segment register, print it.
139 if (SegReg.getReg()) {
140 printOperand(MI, Op+4, O);
146 bool NeedPlus = false;
147 if (BaseReg.getReg()) {
148 printOperand(MI, Op, O);
152 if (IndexReg.getReg()) {
153 if (NeedPlus) O << " + ";
155 O << ScaleVal << '*';
156 printOperand(MI, Op+2, O);
161 if (!DispSpec.isImm()) {
162 if (NeedPlus) O << " + ";
163 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
164 O << *DispSpec.getExpr();
166 int64_t DispVal = DispSpec.getImm();
167 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {