1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
13 //===----------------------------------------------------------------------===//
15 #include "X86InstComments.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/CodeGen/MachineValueType.h"
20 #include "llvm/Support/raw_ostream.h"
24 static unsigned getVectorRegSize(unsigned RegNo) {
25 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
27 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
29 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
31 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
34 llvm_unreachable("Unknown vector reg!");
38 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
39 unsigned OperandIndex) {
40 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
41 return MVT::getVectorVT(ScalarVT,
42 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
45 /// \brief Extracts the src/dst types for a given zero extension instruction.
46 /// \note While the number of elements in DstVT type correct, the
47 /// number in the SrcVT type is expanded to fill the src xmm register and the
48 /// upper elements may not be included in the dst xmm/ymm register.
49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
50 switch (MI->getOpcode()) {
52 llvm_unreachable("Unknown zero extension instruction");
56 case X86::VPMOVZXBWrm:
57 case X86::VPMOVZXBWrr:
61 case X86::VPMOVZXBWYrm:
62 case X86::VPMOVZXBWYrr:
68 case X86::VPMOVZXBDrm:
69 case X86::VPMOVZXBDrr:
73 case X86::VPMOVZXBDYrm:
74 case X86::VPMOVZXBDYrr:
80 case X86::VPMOVZXBQrm:
81 case X86::VPMOVZXBQrr:
85 case X86::VPMOVZXBQYrm:
86 case X86::VPMOVZXBQYrr:
93 case X86::VPMOVZXWDrm:
94 case X86::VPMOVZXWDrr:
98 case X86::VPMOVZXWDYrm:
99 case X86::VPMOVZXWDYrr:
103 case X86::PMOVZXWQrm:
104 case X86::PMOVZXWQrr:
105 case X86::VPMOVZXWQrm:
106 case X86::VPMOVZXWQrr:
110 case X86::VPMOVZXWQYrm:
111 case X86::VPMOVZXWQYrr:
115 // i32 zero extension
116 case X86::PMOVZXDQrm:
117 case X86::PMOVZXDQrr:
118 case X86::VPMOVZXDQrm:
119 case X86::VPMOVZXDQrr:
123 case X86::VPMOVZXDQYrm:
124 case X86::VPMOVZXDQYrr:
131 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
132 case X86::V##Inst##Suffix##src: \
133 case X86::V##Inst##Suffix##src##k: \
134 case X86::V##Inst##Suffix##src##kz:
136 #define CASE_SSE_INS_COMMON(Inst, src) \
139 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
140 case X86::V##Inst##Suffix##src:
142 #define CASE_MOVDUP(Inst, src) \
143 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
144 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
145 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
146 CASE_AVX_INS_COMMON(Inst, , r##src) \
147 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
148 CASE_SSE_INS_COMMON(Inst, r##src) \
150 #define CASE_UNPCK(Inst, src) \
151 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
152 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
153 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
154 CASE_AVX_INS_COMMON(Inst, , r##src) \
155 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
156 CASE_SSE_INS_COMMON(Inst, r##src) \
158 #define CASE_SHUF(Inst, src) \
159 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
160 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
161 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) \
162 CASE_AVX_INS_COMMON(Inst, , r##src##i) \
163 CASE_AVX_INS_COMMON(Inst, Y, r##src##i) \
164 CASE_SSE_INS_COMMON(Inst, r##src##i) \
166 #define CASE_VPERM(Inst, src) \
167 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
168 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
169 CASE_MASK_INS_COMMON(Inst, Z128, src##i) \
170 CASE_AVX_INS_COMMON(Inst, , src##i) \
171 CASE_AVX_INS_COMMON(Inst, Y, src##i) \
173 #define CASE_VSHUF(Inst, src) \
174 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
175 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
176 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
177 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \
179 /// \brief Extracts the types and if it has memory operand for a given
180 /// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
181 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
183 switch (MI->getOpcode()) {
185 llvm_unreachable("Unknown VSHUF64x2 family instructions.");
188 HasMemOp = true; // FALL THROUGH.
190 VT = getRegOperandVectorVT(MI, MVT::i64, 0);
193 HasMemOp = true; // FALL THROUGH.
195 VT = getRegOperandVectorVT(MI, MVT::i32, 0);
200 //===----------------------------------------------------------------------===//
201 // Top Level Entrypoint
202 //===----------------------------------------------------------------------===//
204 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
205 /// newline terminated strings to the specified string if desired. This
206 /// information is shown in disassembly dumps when verbose assembly is enabled.
207 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
208 const char *(*getRegName)(unsigned)) {
209 // If this is a shuffle operation, the switch should fill in this state.
210 SmallVector<int, 8> ShuffleMask;
211 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
213 switch (MI->getOpcode()) {
215 // Not an instruction for which we can decode comments.
218 case X86::BLENDPDrri:
219 case X86::VBLENDPDrri:
220 case X86::VBLENDPDYrri:
221 Src2Name = getRegName(MI->getOperand(2).getReg());
223 case X86::BLENDPDrmi:
224 case X86::VBLENDPDrmi:
225 case X86::VBLENDPDYrmi:
226 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
227 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
228 MI->getOperand(MI->getNumOperands() - 1).getImm(),
230 Src1Name = getRegName(MI->getOperand(1).getReg());
231 DestName = getRegName(MI->getOperand(0).getReg());
234 case X86::BLENDPSrri:
235 case X86::VBLENDPSrri:
236 case X86::VBLENDPSYrri:
237 Src2Name = getRegName(MI->getOperand(2).getReg());
239 case X86::BLENDPSrmi:
240 case X86::VBLENDPSrmi:
241 case X86::VBLENDPSYrmi:
242 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
243 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
244 MI->getOperand(MI->getNumOperands() - 1).getImm(),
246 Src1Name = getRegName(MI->getOperand(1).getReg());
247 DestName = getRegName(MI->getOperand(0).getReg());
250 case X86::PBLENDWrri:
251 case X86::VPBLENDWrri:
252 case X86::VPBLENDWYrri:
253 Src2Name = getRegName(MI->getOperand(2).getReg());
255 case X86::PBLENDWrmi:
256 case X86::VPBLENDWrmi:
257 case X86::VPBLENDWYrmi:
258 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
259 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
260 MI->getOperand(MI->getNumOperands() - 1).getImm(),
262 Src1Name = getRegName(MI->getOperand(1).getReg());
263 DestName = getRegName(MI->getOperand(0).getReg());
266 case X86::VPBLENDDrri:
267 case X86::VPBLENDDYrri:
268 Src2Name = getRegName(MI->getOperand(2).getReg());
270 case X86::VPBLENDDrmi:
271 case X86::VPBLENDDYrmi:
272 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
273 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
274 MI->getOperand(MI->getNumOperands() - 1).getImm(),
276 Src1Name = getRegName(MI->getOperand(1).getReg());
277 DestName = getRegName(MI->getOperand(0).getReg());
280 case X86::INSERTPSrr:
281 case X86::VINSERTPSrr:
282 Src2Name = getRegName(MI->getOperand(2).getReg());
284 case X86::INSERTPSrm:
285 case X86::VINSERTPSrm:
286 DestName = getRegName(MI->getOperand(0).getReg());
287 Src1Name = getRegName(MI->getOperand(1).getReg());
288 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
289 DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
294 case X86::VMOVLHPSrr:
295 Src2Name = getRegName(MI->getOperand(2).getReg());
296 Src1Name = getRegName(MI->getOperand(1).getReg());
297 DestName = getRegName(MI->getOperand(0).getReg());
298 DecodeMOVLHPSMask(2, ShuffleMask);
302 case X86::VMOVHLPSrr:
303 Src2Name = getRegName(MI->getOperand(2).getReg());
304 Src1Name = getRegName(MI->getOperand(1).getReg());
305 DestName = getRegName(MI->getOperand(0).getReg());
306 DecodeMOVHLPSMask(2, ShuffleMask);
309 CASE_MOVDUP(MOVSLDUP, r)
310 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
312 CASE_MOVDUP(MOVSLDUP, m) {
313 MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
314 DestName = getRegName(MI->getOperand(0).getReg());
315 DecodeMOVSLDUPMask(VT, ShuffleMask);
319 CASE_MOVDUP(MOVSHDUP, r)
320 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
322 CASE_MOVDUP(MOVSHDUP, m) {
323 MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
324 DestName = getRegName(MI->getOperand(0).getReg());
325 DecodeMOVSHDUPMask(VT, ShuffleMask);
329 case X86::VMOVDDUPYrr:
330 Src1Name = getRegName(MI->getOperand(1).getReg());
332 case X86::VMOVDDUPYrm:
333 DestName = getRegName(MI->getOperand(0).getReg());
334 DecodeMOVDDUPMask(MVT::v4f64, ShuffleMask);
338 case X86::VMOVDDUPrr:
339 Src1Name = getRegName(MI->getOperand(1).getReg());
342 case X86::VMOVDDUPrm:
343 DestName = getRegName(MI->getOperand(0).getReg());
344 DecodeMOVDDUPMask(MVT::v2f64, ShuffleMask);
349 case X86::VPSLLDQYri:
350 Src1Name = getRegName(MI->getOperand(1).getReg());
351 DestName = getRegName(MI->getOperand(0).getReg());
352 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
353 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
354 MI->getOperand(MI->getNumOperands() - 1).getImm(),
360 case X86::VPSRLDQYri:
361 Src1Name = getRegName(MI->getOperand(1).getReg());
362 DestName = getRegName(MI->getOperand(0).getReg());
363 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
364 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
365 MI->getOperand(MI->getNumOperands() - 1).getImm(),
369 case X86::PALIGNR128rr:
370 case X86::VPALIGNR128rr:
371 case X86::VPALIGNR256rr:
372 Src1Name = getRegName(MI->getOperand(2).getReg());
374 case X86::PALIGNR128rm:
375 case X86::VPALIGNR128rm:
376 case X86::VPALIGNR256rm:
377 Src2Name = getRegName(MI->getOperand(1).getReg());
378 DestName = getRegName(MI->getOperand(0).getReg());
379 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
380 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
381 MI->getOperand(MI->getNumOperands() - 1).getImm(),
387 case X86::VPSHUFDYri:
388 Src1Name = getRegName(MI->getOperand(1).getReg());
392 case X86::VPSHUFDYmi:
393 DestName = getRegName(MI->getOperand(0).getReg());
394 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
395 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
396 MI->getOperand(MI->getNumOperands() - 1).getImm(),
401 case X86::VPSHUFHWri:
402 case X86::VPSHUFHWYri:
403 Src1Name = getRegName(MI->getOperand(1).getReg());
406 case X86::VPSHUFHWmi:
407 case X86::VPSHUFHWYmi:
408 DestName = getRegName(MI->getOperand(0).getReg());
409 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
410 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
411 MI->getOperand(MI->getNumOperands() - 1).getImm(),
416 case X86::VPSHUFLWri:
417 case X86::VPSHUFLWYri:
418 Src1Name = getRegName(MI->getOperand(1).getReg());
421 case X86::VPSHUFLWmi:
422 case X86::VPSHUFLWYmi:
423 DestName = getRegName(MI->getOperand(0).getReg());
424 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
425 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
426 MI->getOperand(MI->getNumOperands() - 1).getImm(),
430 case X86::MMX_PSHUFWri:
431 Src1Name = getRegName(MI->getOperand(1).getReg());
433 case X86::MMX_PSHUFWmi:
434 DestName = getRegName(MI->getOperand(0).getReg());
435 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
436 DecodePSHUFMask(MVT::v4i16,
437 MI->getOperand(MI->getNumOperands() - 1).getImm(),
442 Src1Name = getRegName(MI->getOperand(1).getReg());
445 DestName = getRegName(MI->getOperand(0).getReg());
446 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
449 CASE_UNPCK(PUNPCKHBW, r)
450 case X86::MMX_PUNPCKHBWirr:
451 Src2Name = getRegName(MI->getOperand(2).getReg());
453 CASE_UNPCK(PUNPCKHBW, m)
454 case X86::MMX_PUNPCKHBWirm:
455 Src1Name = getRegName(MI->getOperand(1).getReg());
456 DestName = getRegName(MI->getOperand(0).getReg());
457 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
460 CASE_UNPCK(PUNPCKHWD, r)
461 case X86::MMX_PUNPCKHWDirr:
462 Src2Name = getRegName(MI->getOperand(2).getReg());
464 CASE_UNPCK(PUNPCKHWD, m)
465 case X86::MMX_PUNPCKHWDirm:
466 Src1Name = getRegName(MI->getOperand(1).getReg());
467 DestName = getRegName(MI->getOperand(0).getReg());
468 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
471 CASE_UNPCK(PUNPCKHDQ, r)
472 case X86::MMX_PUNPCKHDQirr:
473 Src2Name = getRegName(MI->getOperand(2).getReg());
475 CASE_UNPCK(PUNPCKHDQ, m)
476 case X86::MMX_PUNPCKHDQirm:
477 Src1Name = getRegName(MI->getOperand(1).getReg());
478 DestName = getRegName(MI->getOperand(0).getReg());
479 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
482 CASE_UNPCK(PUNPCKHQDQ, r)
483 Src2Name = getRegName(MI->getOperand(2).getReg());
485 CASE_UNPCK(PUNPCKHQDQ, m)
486 Src1Name = getRegName(MI->getOperand(1).getReg());
487 DestName = getRegName(MI->getOperand(0).getReg());
488 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
491 CASE_UNPCK(PUNPCKLBW, r)
492 case X86::MMX_PUNPCKLBWirr:
493 Src2Name = getRegName(MI->getOperand(2).getReg());
495 CASE_UNPCK(PUNPCKLBW, m)
496 case X86::MMX_PUNPCKLBWirm:
497 Src1Name = getRegName(MI->getOperand(1).getReg());
498 DestName = getRegName(MI->getOperand(0).getReg());
499 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
502 CASE_UNPCK(PUNPCKLWD, r)
503 case X86::MMX_PUNPCKLWDirr:
504 Src2Name = getRegName(MI->getOperand(2).getReg());
506 CASE_UNPCK(PUNPCKLWD, m)
507 case X86::MMX_PUNPCKLWDirm:
508 Src1Name = getRegName(MI->getOperand(1).getReg());
509 DestName = getRegName(MI->getOperand(0).getReg());
510 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
513 CASE_UNPCK(PUNPCKLDQ, r)
514 case X86::MMX_PUNPCKLDQirr:
515 Src2Name = getRegName(MI->getOperand(2).getReg());
517 CASE_UNPCK(PUNPCKLDQ, m)
518 case X86::MMX_PUNPCKLDQirm:
519 Src1Name = getRegName(MI->getOperand(1).getReg());
520 DestName = getRegName(MI->getOperand(0).getReg());
521 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
524 CASE_UNPCK(PUNPCKLQDQ, r)
525 Src2Name = getRegName(MI->getOperand(2).getReg());
527 CASE_UNPCK(PUNPCKLQDQ, m)
528 Src1Name = getRegName(MI->getOperand(1).getReg());
529 DestName = getRegName(MI->getOperand(0).getReg());
530 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
534 Src2Name = getRegName(MI->getOperand(2).getReg());
537 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
538 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
539 MI->getOperand(MI->getNumOperands() - 1).getImm(),
541 Src1Name = getRegName(MI->getOperand(1).getReg());
542 DestName = getRegName(MI->getOperand(0).getReg());
546 Src2Name = getRegName(MI->getOperand(2).getReg());
549 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
550 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
551 MI->getOperand(MI->getNumOperands() - 1).getImm(),
553 Src1Name = getRegName(MI->getOperand(1).getReg());
554 DestName = getRegName(MI->getOperand(0).getReg());
560 CASE_VSHUF(32X4, m) {
563 unsigned NumOp = MI->getNumOperands();
564 getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
565 decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
567 DestName = getRegName(MI->getOperand(0).getReg());
569 assert((NumOp >= 8) && "Expected at least 8 operands!");
570 Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
572 assert((NumOp >= 4) && "Expected at least 4 operands!");
573 Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
574 Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
579 CASE_UNPCK(UNPCKLPD, r)
580 Src2Name = getRegName(MI->getOperand(2).getReg());
582 CASE_UNPCK(UNPCKLPD, m)
583 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
584 Src1Name = getRegName(MI->getOperand(1).getReg());
585 DestName = getRegName(MI->getOperand(0).getReg());
588 CASE_UNPCK(UNPCKLPS, r)
589 Src2Name = getRegName(MI->getOperand(2).getReg());
591 CASE_UNPCK(UNPCKLPS, m)
592 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
593 Src1Name = getRegName(MI->getOperand(1).getReg());
594 DestName = getRegName(MI->getOperand(0).getReg());
597 CASE_UNPCK(UNPCKHPD, r)
598 Src2Name = getRegName(MI->getOperand(2).getReg());
600 CASE_UNPCK(UNPCKHPD, m)
601 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
602 Src1Name = getRegName(MI->getOperand(1).getReg());
603 DestName = getRegName(MI->getOperand(0).getReg());
606 CASE_UNPCK(UNPCKHPS, r)
607 Src2Name = getRegName(MI->getOperand(2).getReg());
609 CASE_UNPCK(UNPCKHPS, m)
610 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
611 Src1Name = getRegName(MI->getOperand(1).getReg());
612 DestName = getRegName(MI->getOperand(0).getReg());
615 CASE_VPERM(PERMILPS, r)
616 Src1Name = getRegName(MI->getOperand(1).getReg());
618 CASE_VPERM(PERMILPS, m)
619 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
620 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
621 MI->getOperand(MI->getNumOperands() - 1).getImm(),
623 DestName = getRegName(MI->getOperand(0).getReg());
626 CASE_VPERM(PERMILPD, r)
627 Src1Name = getRegName(MI->getOperand(1).getReg());
629 CASE_VPERM(PERMILPD, m)
630 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
631 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
632 MI->getOperand(MI->getNumOperands() - 1).getImm(),
634 DestName = getRegName(MI->getOperand(0).getReg());
637 case X86::VPERM2F128rr:
638 case X86::VPERM2I128rr:
639 Src2Name = getRegName(MI->getOperand(2).getReg());
641 case X86::VPERM2F128rm:
642 case X86::VPERM2I128rm:
643 // For instruction comments purpose, assume the 256-bit vector is v4i64.
644 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
645 DecodeVPERM2X128Mask(MVT::v4i64,
646 MI->getOperand(MI->getNumOperands() - 1).getImm(),
648 Src1Name = getRegName(MI->getOperand(1).getReg());
649 DestName = getRegName(MI->getOperand(0).getReg());
653 case X86::VPERMPDYri:
654 Src1Name = getRegName(MI->getOperand(1).getReg());
657 case X86::VPERMPDYmi:
658 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
659 DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
661 DestName = getRegName(MI->getOperand(0).getReg());
666 Src2Name = getRegName(MI->getOperand(2).getReg());
667 Src1Name = getRegName(MI->getOperand(1).getReg());
671 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
672 DestName = getRegName(MI->getOperand(0).getReg());
676 Src2Name = getRegName(MI->getOperand(2).getReg());
677 Src1Name = getRegName(MI->getOperand(1).getReg());
681 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
682 DestName = getRegName(MI->getOperand(0).getReg());
685 case X86::MOVPQI2QIrr:
686 case X86::MOVZPQILo2PQIrr:
687 case X86::VMOVPQI2QIrr:
688 case X86::VMOVZPQILo2PQIrr:
689 Src1Name = getRegName(MI->getOperand(1).getReg());
691 case X86::MOVQI2PQIrm:
692 case X86::MOVZQI2PQIrm:
693 case X86::MOVZPQILo2PQIrm:
694 case X86::VMOVQI2PQIrm:
695 case X86::VMOVZQI2PQIrm:
696 case X86::VMOVZPQILo2PQIrm:
697 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
698 DestName = getRegName(MI->getOperand(0).getReg());
701 case X86::MOVDI2PDIrm:
702 case X86::VMOVDI2PDIrm:
703 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
704 DestName = getRegName(MI->getOperand(0).getReg());
708 if (MI->getOperand(2).isImm() &&
709 MI->getOperand(3).isImm())
710 DecodeEXTRQIMask(MI->getOperand(2).getImm(),
711 MI->getOperand(3).getImm(),
714 DestName = getRegName(MI->getOperand(0).getReg());
715 Src1Name = getRegName(MI->getOperand(1).getReg());
719 if (MI->getOperand(3).isImm() &&
720 MI->getOperand(4).isImm())
721 DecodeINSERTQIMask(MI->getOperand(3).getImm(),
722 MI->getOperand(4).getImm(),
725 DestName = getRegName(MI->getOperand(0).getReg());
726 Src1Name = getRegName(MI->getOperand(1).getReg());
727 Src2Name = getRegName(MI->getOperand(2).getReg());
730 case X86::PMOVZXBWrr:
731 case X86::PMOVZXBDrr:
732 case X86::PMOVZXBQrr:
733 case X86::PMOVZXWDrr:
734 case X86::PMOVZXWQrr:
735 case X86::PMOVZXDQrr:
736 case X86::VPMOVZXBWrr:
737 case X86::VPMOVZXBDrr:
738 case X86::VPMOVZXBQrr:
739 case X86::VPMOVZXWDrr:
740 case X86::VPMOVZXWQrr:
741 case X86::VPMOVZXDQrr:
742 case X86::VPMOVZXBWYrr:
743 case X86::VPMOVZXBDYrr:
744 case X86::VPMOVZXBQYrr:
745 case X86::VPMOVZXWDYrr:
746 case X86::VPMOVZXWQYrr:
747 case X86::VPMOVZXDQYrr:
748 Src1Name = getRegName(MI->getOperand(1).getReg());
750 case X86::PMOVZXBWrm:
751 case X86::PMOVZXBDrm:
752 case X86::PMOVZXBQrm:
753 case X86::PMOVZXWDrm:
754 case X86::PMOVZXWQrm:
755 case X86::PMOVZXDQrm:
756 case X86::VPMOVZXBWrm:
757 case X86::VPMOVZXBDrm:
758 case X86::VPMOVZXBQrm:
759 case X86::VPMOVZXWDrm:
760 case X86::VPMOVZXWQrm:
761 case X86::VPMOVZXDQrm:
762 case X86::VPMOVZXBWYrm:
763 case X86::VPMOVZXBDYrm:
764 case X86::VPMOVZXBQYrm:
765 case X86::VPMOVZXWDYrm:
766 case X86::VPMOVZXWQYrm:
767 case X86::VPMOVZXDQYrm: {
769 getZeroExtensionTypes(MI, SrcVT, DstVT);
770 DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask);
771 DestName = getRegName(MI->getOperand(0).getReg());
775 // The only comments we decode are shuffles, so give up if we were unable to
776 // decode a shuffle mask.
777 if (ShuffleMask.empty())
780 if (!DestName) DestName = Src1Name;
781 OS << (DestName ? DestName : "mem") << " = ";
783 // If the two sources are the same, canonicalize the input elements to be
784 // from the first src so that we get larger element spans.
785 if (Src1Name == Src2Name) {
786 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
787 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
788 ShuffleMask[i] >= (int)e) // From second mask.
793 // The shuffle mask specifies which elements of the src1/src2 fill in the
794 // destination, with a few sentinel values. Loop through and print them
796 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
799 if (ShuffleMask[i] == SM_SentinelZero) {
804 // Otherwise, it must come from src1 or src2. Print the span of elements
805 // that comes from this src.
806 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
807 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
808 OS << (SrcName ? SrcName : "mem") << '[';
810 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
811 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
816 if (ShuffleMask[i] == SM_SentinelUndef)
819 OS << ShuffleMask[i] % ShuffleMask.size();
823 --i; // For loop increments element #.
828 // We successfully added a comment to this instruction.