1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
13 //===----------------------------------------------------------------------===//
15 #include "X86InstComments.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/CodeGen/MachineValueType.h"
20 #include "llvm/Support/raw_ostream.h"
24 static unsigned getVectorRegSize(unsigned RegNo) {
25 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
27 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
29 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
31 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
34 llvm_unreachable("Unknown vector reg!");
38 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
39 unsigned OperandIndex) {
40 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
41 return MVT::getVectorVT(ScalarVT,
42 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
45 /// \brief Extracts the src/dst types for a given zero extension instruction.
46 /// \note While the number of elements in DstVT type correct, the
47 /// number in the SrcVT type is expanded to fill the src xmm register and the
48 /// upper elements may not be included in the dst xmm/ymm register.
49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
50 switch (MI->getOpcode()) {
52 llvm_unreachable("Unknown zero extension instruction");
56 case X86::VPMOVZXBWrm:
57 case X86::VPMOVZXBWrr:
61 case X86::VPMOVZXBWYrm:
62 case X86::VPMOVZXBWYrr:
68 case X86::VPMOVZXBDrm:
69 case X86::VPMOVZXBDrr:
73 case X86::VPMOVZXBDYrm:
74 case X86::VPMOVZXBDYrr:
80 case X86::VPMOVZXBQrm:
81 case X86::VPMOVZXBQrr:
85 case X86::VPMOVZXBQYrm:
86 case X86::VPMOVZXBQYrr:
93 case X86::VPMOVZXWDrm:
94 case X86::VPMOVZXWDrr:
98 case X86::VPMOVZXWDYrm:
99 case X86::VPMOVZXWDYrr:
103 case X86::PMOVZXWQrm:
104 case X86::PMOVZXWQrr:
105 case X86::VPMOVZXWQrm:
106 case X86::VPMOVZXWQrr:
110 case X86::VPMOVZXWQYrm:
111 case X86::VPMOVZXWQYrr:
115 // i32 zero extension
116 case X86::PMOVZXDQrm:
117 case X86::PMOVZXDQrr:
118 case X86::VPMOVZXDQrm:
119 case X86::VPMOVZXDQrr:
123 case X86::VPMOVZXDQYrm:
124 case X86::VPMOVZXDQYrr:
131 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
132 case X86::V##Inst##Suffix##src: \
133 case X86::V##Inst##Suffix##src##k: \
134 case X86::V##Inst##Suffix##src##kz:
136 #define CASE_SSE_INS_COMMON(Inst, src) \
139 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
140 case X86::V##Inst##Suffix##src:
142 #define CASE_MOVDUP(Inst, src) \
143 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
144 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
145 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
146 CASE_AVX_INS_COMMON(Inst, , r##src) \
147 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
148 CASE_SSE_INS_COMMON(Inst, r##src) \
150 #define CASE_UNPCK(Inst, src) \
151 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
152 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
153 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
154 CASE_AVX_INS_COMMON(Inst, , r##src) \
155 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
156 CASE_SSE_INS_COMMON(Inst, r##src) \
158 #define CASE_SHUF(Inst, src) \
159 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
160 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
161 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) \
162 CASE_AVX_INS_COMMON(Inst, , r##src##i) \
163 CASE_AVX_INS_COMMON(Inst, Y, r##src##i) \
164 CASE_SSE_INS_COMMON(Inst, r##src##i) \
166 #define CASE_VPERM(Inst, src) \
167 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
168 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
169 CASE_MASK_INS_COMMON(Inst, Z128, src##i) \
170 CASE_AVX_INS_COMMON(Inst, , src##i) \
171 CASE_AVX_INS_COMMON(Inst, Y, src##i) \
173 #define CASE_VSHUF(Inst, src) \
174 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
175 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
176 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
177 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \
179 /// \brief Extracts the types and if it has memory operand for a given
180 /// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
181 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
183 switch (MI->getOpcode()) {
185 llvm_unreachable("Unknown VSHUF64x2 family instructions.");
188 HasMemOp = true; // FALL THROUGH.
190 VT = getRegOperandVectorVT(MI, MVT::i64, 0);
193 HasMemOp = true; // FALL THROUGH.
195 VT = getRegOperandVectorVT(MI, MVT::i32, 0);
200 //===----------------------------------------------------------------------===//
201 // Top Level Entrypoint
202 //===----------------------------------------------------------------------===//
204 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
205 /// newline terminated strings to the specified string if desired. This
206 /// information is shown in disassembly dumps when verbose assembly is enabled.
207 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
208 const char *(*getRegName)(unsigned)) {
209 // If this is a shuffle operation, the switch should fill in this state.
210 SmallVector<int, 8> ShuffleMask;
211 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
213 switch (MI->getOpcode()) {
215 // Not an instruction for which we can decode comments.
218 case X86::BLENDPDrri:
219 case X86::VBLENDPDrri:
220 case X86::VBLENDPDYrri:
221 Src2Name = getRegName(MI->getOperand(2).getReg());
223 case X86::BLENDPDrmi:
224 case X86::VBLENDPDrmi:
225 case X86::VBLENDPDYrmi:
226 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
227 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
228 MI->getOperand(MI->getNumOperands() - 1).getImm(),
230 Src1Name = getRegName(MI->getOperand(1).getReg());
231 DestName = getRegName(MI->getOperand(0).getReg());
234 case X86::BLENDPSrri:
235 case X86::VBLENDPSrri:
236 case X86::VBLENDPSYrri:
237 Src2Name = getRegName(MI->getOperand(2).getReg());
239 case X86::BLENDPSrmi:
240 case X86::VBLENDPSrmi:
241 case X86::VBLENDPSYrmi:
242 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
243 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
244 MI->getOperand(MI->getNumOperands() - 1).getImm(),
246 Src1Name = getRegName(MI->getOperand(1).getReg());
247 DestName = getRegName(MI->getOperand(0).getReg());
250 case X86::PBLENDWrri:
251 case X86::VPBLENDWrri:
252 case X86::VPBLENDWYrri:
253 Src2Name = getRegName(MI->getOperand(2).getReg());
255 case X86::PBLENDWrmi:
256 case X86::VPBLENDWrmi:
257 case X86::VPBLENDWYrmi:
258 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
259 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
260 MI->getOperand(MI->getNumOperands() - 1).getImm(),
262 Src1Name = getRegName(MI->getOperand(1).getReg());
263 DestName = getRegName(MI->getOperand(0).getReg());
266 case X86::VPBLENDDrri:
267 case X86::VPBLENDDYrri:
268 Src2Name = getRegName(MI->getOperand(2).getReg());
270 case X86::VPBLENDDrmi:
271 case X86::VPBLENDDYrmi:
272 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
273 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
274 MI->getOperand(MI->getNumOperands() - 1).getImm(),
276 Src1Name = getRegName(MI->getOperand(1).getReg());
277 DestName = getRegName(MI->getOperand(0).getReg());
280 case X86::INSERTPSrr:
281 case X86::VINSERTPSrr:
282 Src2Name = getRegName(MI->getOperand(2).getReg());
284 case X86::INSERTPSrm:
285 case X86::VINSERTPSrm:
286 DestName = getRegName(MI->getOperand(0).getReg());
287 Src1Name = getRegName(MI->getOperand(1).getReg());
288 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
289 DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
294 case X86::VMOVLHPSrr:
295 Src2Name = getRegName(MI->getOperand(2).getReg());
296 Src1Name = getRegName(MI->getOperand(1).getReg());
297 DestName = getRegName(MI->getOperand(0).getReg());
298 DecodeMOVLHPSMask(2, ShuffleMask);
302 case X86::VMOVHLPSrr:
303 Src2Name = getRegName(MI->getOperand(2).getReg());
304 Src1Name = getRegName(MI->getOperand(1).getReg());
305 DestName = getRegName(MI->getOperand(0).getReg());
306 DecodeMOVHLPSMask(2, ShuffleMask);
309 CASE_MOVDUP(MOVSLDUP, r)
310 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
312 CASE_MOVDUP(MOVSLDUP, m)
313 DestName = getRegName(MI->getOperand(0).getReg());
314 DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
317 CASE_MOVDUP(MOVSHDUP, r)
318 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
320 CASE_MOVDUP(MOVSHDUP, m)
321 DestName = getRegName(MI->getOperand(0).getReg());
322 DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
325 CASE_MOVDUP(MOVDDUP, r)
326 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
328 CASE_MOVDUP(MOVDDUP, m)
329 DestName = getRegName(MI->getOperand(0).getReg());
330 DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
335 case X86::VPSLLDQYri:
336 Src1Name = getRegName(MI->getOperand(1).getReg());
337 DestName = getRegName(MI->getOperand(0).getReg());
338 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
339 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
340 MI->getOperand(MI->getNumOperands() - 1).getImm(),
346 case X86::VPSRLDQYri:
347 Src1Name = getRegName(MI->getOperand(1).getReg());
348 DestName = getRegName(MI->getOperand(0).getReg());
349 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
350 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
351 MI->getOperand(MI->getNumOperands() - 1).getImm(),
355 case X86::PALIGNR128rr:
356 case X86::VPALIGNR128rr:
357 case X86::VPALIGNR256rr:
358 Src1Name = getRegName(MI->getOperand(2).getReg());
360 case X86::PALIGNR128rm:
361 case X86::VPALIGNR128rm:
362 case X86::VPALIGNR256rm:
363 Src2Name = getRegName(MI->getOperand(1).getReg());
364 DestName = getRegName(MI->getOperand(0).getReg());
365 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
366 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
367 MI->getOperand(MI->getNumOperands() - 1).getImm(),
373 case X86::VPSHUFDYri:
374 Src1Name = getRegName(MI->getOperand(1).getReg());
378 case X86::VPSHUFDYmi:
379 DestName = getRegName(MI->getOperand(0).getReg());
380 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
381 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
382 MI->getOperand(MI->getNumOperands() - 1).getImm(),
387 case X86::VPSHUFHWri:
388 case X86::VPSHUFHWYri:
389 Src1Name = getRegName(MI->getOperand(1).getReg());
392 case X86::VPSHUFHWmi:
393 case X86::VPSHUFHWYmi:
394 DestName = getRegName(MI->getOperand(0).getReg());
395 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
396 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
397 MI->getOperand(MI->getNumOperands() - 1).getImm(),
402 case X86::VPSHUFLWri:
403 case X86::VPSHUFLWYri:
404 Src1Name = getRegName(MI->getOperand(1).getReg());
407 case X86::VPSHUFLWmi:
408 case X86::VPSHUFLWYmi:
409 DestName = getRegName(MI->getOperand(0).getReg());
410 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
411 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
412 MI->getOperand(MI->getNumOperands() - 1).getImm(),
416 case X86::MMX_PSHUFWri:
417 Src1Name = getRegName(MI->getOperand(1).getReg());
419 case X86::MMX_PSHUFWmi:
420 DestName = getRegName(MI->getOperand(0).getReg());
421 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
422 DecodePSHUFMask(MVT::v4i16,
423 MI->getOperand(MI->getNumOperands() - 1).getImm(),
428 Src1Name = getRegName(MI->getOperand(1).getReg());
431 DestName = getRegName(MI->getOperand(0).getReg());
432 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
435 CASE_UNPCK(PUNPCKHBW, r)
436 case X86::MMX_PUNPCKHBWirr:
437 Src2Name = getRegName(MI->getOperand(2).getReg());
439 CASE_UNPCK(PUNPCKHBW, m)
440 case X86::MMX_PUNPCKHBWirm:
441 Src1Name = getRegName(MI->getOperand(1).getReg());
442 DestName = getRegName(MI->getOperand(0).getReg());
443 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
446 CASE_UNPCK(PUNPCKHWD, r)
447 case X86::MMX_PUNPCKHWDirr:
448 Src2Name = getRegName(MI->getOperand(2).getReg());
450 CASE_UNPCK(PUNPCKHWD, m)
451 case X86::MMX_PUNPCKHWDirm:
452 Src1Name = getRegName(MI->getOperand(1).getReg());
453 DestName = getRegName(MI->getOperand(0).getReg());
454 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
457 CASE_UNPCK(PUNPCKHDQ, r)
458 case X86::MMX_PUNPCKHDQirr:
459 Src2Name = getRegName(MI->getOperand(2).getReg());
461 CASE_UNPCK(PUNPCKHDQ, m)
462 case X86::MMX_PUNPCKHDQirm:
463 Src1Name = getRegName(MI->getOperand(1).getReg());
464 DestName = getRegName(MI->getOperand(0).getReg());
465 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
468 CASE_UNPCK(PUNPCKHQDQ, r)
469 Src2Name = getRegName(MI->getOperand(2).getReg());
471 CASE_UNPCK(PUNPCKHQDQ, m)
472 Src1Name = getRegName(MI->getOperand(1).getReg());
473 DestName = getRegName(MI->getOperand(0).getReg());
474 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
477 CASE_UNPCK(PUNPCKLBW, r)
478 case X86::MMX_PUNPCKLBWirr:
479 Src2Name = getRegName(MI->getOperand(2).getReg());
481 CASE_UNPCK(PUNPCKLBW, m)
482 case X86::MMX_PUNPCKLBWirm:
483 Src1Name = getRegName(MI->getOperand(1).getReg());
484 DestName = getRegName(MI->getOperand(0).getReg());
485 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
488 CASE_UNPCK(PUNPCKLWD, r)
489 case X86::MMX_PUNPCKLWDirr:
490 Src2Name = getRegName(MI->getOperand(2).getReg());
492 CASE_UNPCK(PUNPCKLWD, m)
493 case X86::MMX_PUNPCKLWDirm:
494 Src1Name = getRegName(MI->getOperand(1).getReg());
495 DestName = getRegName(MI->getOperand(0).getReg());
496 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
499 CASE_UNPCK(PUNPCKLDQ, r)
500 case X86::MMX_PUNPCKLDQirr:
501 Src2Name = getRegName(MI->getOperand(2).getReg());
503 CASE_UNPCK(PUNPCKLDQ, m)
504 case X86::MMX_PUNPCKLDQirm:
505 Src1Name = getRegName(MI->getOperand(1).getReg());
506 DestName = getRegName(MI->getOperand(0).getReg());
507 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
510 CASE_UNPCK(PUNPCKLQDQ, r)
511 Src2Name = getRegName(MI->getOperand(2).getReg());
513 CASE_UNPCK(PUNPCKLQDQ, m)
514 Src1Name = getRegName(MI->getOperand(1).getReg());
515 DestName = getRegName(MI->getOperand(0).getReg());
516 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
520 Src2Name = getRegName(MI->getOperand(2).getReg());
523 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
524 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
525 MI->getOperand(MI->getNumOperands() - 1).getImm(),
527 Src1Name = getRegName(MI->getOperand(1).getReg());
528 DestName = getRegName(MI->getOperand(0).getReg());
532 Src2Name = getRegName(MI->getOperand(2).getReg());
535 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
536 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
537 MI->getOperand(MI->getNumOperands() - 1).getImm(),
539 Src1Name = getRegName(MI->getOperand(1).getReg());
540 DestName = getRegName(MI->getOperand(0).getReg());
546 CASE_VSHUF(32X4, m) {
549 unsigned NumOp = MI->getNumOperands();
550 getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
551 decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
553 DestName = getRegName(MI->getOperand(0).getReg());
555 assert((NumOp >= 8) && "Expected at least 8 operands!");
556 Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
558 assert((NumOp >= 4) && "Expected at least 4 operands!");
559 Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
560 Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
565 CASE_UNPCK(UNPCKLPD, r)
566 Src2Name = getRegName(MI->getOperand(2).getReg());
568 CASE_UNPCK(UNPCKLPD, m)
569 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
570 Src1Name = getRegName(MI->getOperand(1).getReg());
571 DestName = getRegName(MI->getOperand(0).getReg());
574 CASE_UNPCK(UNPCKLPS, r)
575 Src2Name = getRegName(MI->getOperand(2).getReg());
577 CASE_UNPCK(UNPCKLPS, m)
578 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
579 Src1Name = getRegName(MI->getOperand(1).getReg());
580 DestName = getRegName(MI->getOperand(0).getReg());
583 CASE_UNPCK(UNPCKHPD, r)
584 Src2Name = getRegName(MI->getOperand(2).getReg());
586 CASE_UNPCK(UNPCKHPD, m)
587 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
588 Src1Name = getRegName(MI->getOperand(1).getReg());
589 DestName = getRegName(MI->getOperand(0).getReg());
592 CASE_UNPCK(UNPCKHPS, r)
593 Src2Name = getRegName(MI->getOperand(2).getReg());
595 CASE_UNPCK(UNPCKHPS, m)
596 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
597 Src1Name = getRegName(MI->getOperand(1).getReg());
598 DestName = getRegName(MI->getOperand(0).getReg());
601 CASE_VPERM(PERMILPS, r)
602 Src1Name = getRegName(MI->getOperand(1).getReg());
604 CASE_VPERM(PERMILPS, m)
605 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
606 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
607 MI->getOperand(MI->getNumOperands() - 1).getImm(),
609 DestName = getRegName(MI->getOperand(0).getReg());
612 CASE_VPERM(PERMILPD, r)
613 Src1Name = getRegName(MI->getOperand(1).getReg());
615 CASE_VPERM(PERMILPD, m)
616 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
617 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
618 MI->getOperand(MI->getNumOperands() - 1).getImm(),
620 DestName = getRegName(MI->getOperand(0).getReg());
623 case X86::VPERM2F128rr:
624 case X86::VPERM2I128rr:
625 Src2Name = getRegName(MI->getOperand(2).getReg());
627 case X86::VPERM2F128rm:
628 case X86::VPERM2I128rm:
629 // For instruction comments purpose, assume the 256-bit vector is v4i64.
630 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
631 DecodeVPERM2X128Mask(MVT::v4i64,
632 MI->getOperand(MI->getNumOperands() - 1).getImm(),
634 Src1Name = getRegName(MI->getOperand(1).getReg());
635 DestName = getRegName(MI->getOperand(0).getReg());
639 case X86::VPERMPDYri:
640 Src1Name = getRegName(MI->getOperand(1).getReg());
643 case X86::VPERMPDYmi:
644 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
645 DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
647 DestName = getRegName(MI->getOperand(0).getReg());
652 Src2Name = getRegName(MI->getOperand(2).getReg());
653 Src1Name = getRegName(MI->getOperand(1).getReg());
657 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
658 DestName = getRegName(MI->getOperand(0).getReg());
662 Src2Name = getRegName(MI->getOperand(2).getReg());
663 Src1Name = getRegName(MI->getOperand(1).getReg());
667 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
668 DestName = getRegName(MI->getOperand(0).getReg());
671 case X86::MOVPQI2QIrr:
672 case X86::MOVZPQILo2PQIrr:
673 case X86::VMOVPQI2QIrr:
674 case X86::VMOVZPQILo2PQIrr:
675 Src1Name = getRegName(MI->getOperand(1).getReg());
677 case X86::MOVQI2PQIrm:
678 case X86::MOVZQI2PQIrm:
679 case X86::MOVZPQILo2PQIrm:
680 case X86::VMOVQI2PQIrm:
681 case X86::VMOVZQI2PQIrm:
682 case X86::VMOVZPQILo2PQIrm:
683 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
684 DestName = getRegName(MI->getOperand(0).getReg());
687 case X86::MOVDI2PDIrm:
688 case X86::VMOVDI2PDIrm:
689 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
690 DestName = getRegName(MI->getOperand(0).getReg());
694 if (MI->getOperand(2).isImm() &&
695 MI->getOperand(3).isImm())
696 DecodeEXTRQIMask(MI->getOperand(2).getImm(),
697 MI->getOperand(3).getImm(),
700 DestName = getRegName(MI->getOperand(0).getReg());
701 Src1Name = getRegName(MI->getOperand(1).getReg());
705 if (MI->getOperand(3).isImm() &&
706 MI->getOperand(4).isImm())
707 DecodeINSERTQIMask(MI->getOperand(3).getImm(),
708 MI->getOperand(4).getImm(),
711 DestName = getRegName(MI->getOperand(0).getReg());
712 Src1Name = getRegName(MI->getOperand(1).getReg());
713 Src2Name = getRegName(MI->getOperand(2).getReg());
716 case X86::PMOVZXBWrr:
717 case X86::PMOVZXBDrr:
718 case X86::PMOVZXBQrr:
719 case X86::PMOVZXWDrr:
720 case X86::PMOVZXWQrr:
721 case X86::PMOVZXDQrr:
722 case X86::VPMOVZXBWrr:
723 case X86::VPMOVZXBDrr:
724 case X86::VPMOVZXBQrr:
725 case X86::VPMOVZXWDrr:
726 case X86::VPMOVZXWQrr:
727 case X86::VPMOVZXDQrr:
728 case X86::VPMOVZXBWYrr:
729 case X86::VPMOVZXBDYrr:
730 case X86::VPMOVZXBQYrr:
731 case X86::VPMOVZXWDYrr:
732 case X86::VPMOVZXWQYrr:
733 case X86::VPMOVZXDQYrr:
734 Src1Name = getRegName(MI->getOperand(1).getReg());
736 case X86::PMOVZXBWrm:
737 case X86::PMOVZXBDrm:
738 case X86::PMOVZXBQrm:
739 case X86::PMOVZXWDrm:
740 case X86::PMOVZXWQrm:
741 case X86::PMOVZXDQrm:
742 case X86::VPMOVZXBWrm:
743 case X86::VPMOVZXBDrm:
744 case X86::VPMOVZXBQrm:
745 case X86::VPMOVZXWDrm:
746 case X86::VPMOVZXWQrm:
747 case X86::VPMOVZXDQrm:
748 case X86::VPMOVZXBWYrm:
749 case X86::VPMOVZXBDYrm:
750 case X86::VPMOVZXBQYrm:
751 case X86::VPMOVZXWDYrm:
752 case X86::VPMOVZXWQYrm:
753 case X86::VPMOVZXDQYrm: {
755 getZeroExtensionTypes(MI, SrcVT, DstVT);
756 DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask);
757 DestName = getRegName(MI->getOperand(0).getReg());
761 // The only comments we decode are shuffles, so give up if we were unable to
762 // decode a shuffle mask.
763 if (ShuffleMask.empty())
766 if (!DestName) DestName = Src1Name;
767 OS << (DestName ? DestName : "mem") << " = ";
769 // If the two sources are the same, canonicalize the input elements to be
770 // from the first src so that we get larger element spans.
771 if (Src1Name == Src2Name) {
772 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
773 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
774 ShuffleMask[i] >= (int)e) // From second mask.
779 // The shuffle mask specifies which elements of the src1/src2 fill in the
780 // destination, with a few sentinel values. Loop through and print them
782 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
785 if (ShuffleMask[i] == SM_SentinelZero) {
790 // Otherwise, it must come from src1 or src2. Print the span of elements
791 // that comes from this src.
792 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
793 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
794 OS << (SrcName ? SrcName : "mem") << '[';
796 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
797 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
802 if (ShuffleMask[i] == SM_SentinelUndef)
805 OS << ShuffleMask[i] % ShuffleMask.size();
809 --i; // For loop increments element #.
814 // We successfully added a comment to this instruction.