1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #include "X86ATTInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86MCTargetDesc.h"
18 #include "X86InstComments.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/Format.h"
26 #include "llvm/Support/FormattedStream.h"
30 #define DEBUG_TYPE "asm-printer"
32 // Include the auto-generated portion of the assembly writer.
33 #define PRINT_ALIAS_INSTR
34 #include "X86GenAsmWriter.inc"
36 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
37 unsigned RegNo) const {
39 << '%' << getRegisterName(RegNo)
43 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
45 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
46 uint64_t TSFlags = Desc.TSFlags;
48 // If verbose assembly is enabled, we can print some informative comments.
50 HasCustomInstComment =
51 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
53 if (TSFlags & X86II::LOCK)
56 // Try to print any aliases first.
57 if (!printAliasInstr(MI, OS))
58 printInstruction(MI, OS);
60 // Next always print the annotation.
61 printAnnotation(OS, Annot);
64 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
66 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
68 default: llvm_unreachable("Invalid ssecc argument!");
69 case 0: O << "eq"; break;
70 case 1: O << "lt"; break;
71 case 2: O << "le"; break;
72 case 3: O << "unord"; break;
73 case 4: O << "neq"; break;
74 case 5: O << "nlt"; break;
75 case 6: O << "nle"; break;
76 case 7: O << "ord"; break;
77 case 8: O << "eq_uq"; break;
78 case 9: O << "nge"; break;
79 case 0xa: O << "ngt"; break;
80 case 0xb: O << "false"; break;
81 case 0xc: O << "neq_oq"; break;
82 case 0xd: O << "ge"; break;
83 case 0xe: O << "gt"; break;
84 case 0xf: O << "true"; break;
88 void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
90 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
92 default: llvm_unreachable("Invalid avxcc argument!");
93 case 0: O << "eq"; break;
94 case 1: O << "lt"; break;
95 case 2: O << "le"; break;
96 case 3: O << "unord"; break;
97 case 4: O << "neq"; break;
98 case 5: O << "nlt"; break;
99 case 6: O << "nle"; break;
100 case 7: O << "ord"; break;
101 case 8: O << "eq_uq"; break;
102 case 9: O << "nge"; break;
103 case 0xa: O << "ngt"; break;
104 case 0xb: O << "false"; break;
105 case 0xc: O << "neq_oq"; break;
106 case 0xd: O << "ge"; break;
107 case 0xe: O << "gt"; break;
108 case 0xf: O << "true"; break;
109 case 0x10: O << "eq_os"; break;
110 case 0x11: O << "lt_oq"; break;
111 case 0x12: O << "le_oq"; break;
112 case 0x13: O << "unord_s"; break;
113 case 0x14: O << "neq_us"; break;
114 case 0x15: O << "nlt_uq"; break;
115 case 0x16: O << "nle_uq"; break;
116 case 0x17: O << "ord_s"; break;
117 case 0x18: O << "eq_us"; break;
118 case 0x19: O << "nge_uq"; break;
119 case 0x1a: O << "ngt_uq"; break;
120 case 0x1b: O << "false_os"; break;
121 case 0x1c: O << "neq_os"; break;
122 case 0x1d: O << "ge_oq"; break;
123 case 0x1e: O << "gt_oq"; break;
124 case 0x1f: O << "true_us"; break;
128 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
132 case 0: O << "{rn-sae}"; break;
133 case 1: O << "{rd-sae}"; break;
134 case 2: O << "{ru-sae}"; break;
135 case 3: O << "{rz-sae}"; break;
138 /// printPCRelImm - This is used to print an immediate value that ends up
139 /// being encoded as a pc-relative value (e.g. for jumps and calls). These
140 /// print slightly differently than normal immediates. For example, a $ is not
142 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
144 const MCOperand &Op = MI->getOperand(OpNo);
146 O << formatImm(Op.getImm());
148 assert(Op.isExpr() && "unknown pcrel immediate operand");
149 // If a symbolic branch target was added as a constant expression then print
150 // that address in hex.
151 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
153 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
154 O << formatHex((uint64_t)Address);
157 // Otherwise, just print the expression.
163 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
165 const MCOperand &Op = MI->getOperand(OpNo);
167 printRegName(O, Op.getReg());
168 } else if (Op.isImm()) {
169 // Print X86 immediates as signed values.
171 << '$' << formatImm((int64_t)Op.getImm())
174 // If there are no instruction-specific comments, add a comment clarifying
175 // the hex value of the immediate operand when it isn't in the range
177 if (CommentStream && !HasCustomInstComment &&
178 (Op.getImm() > 255 || Op.getImm() < -256))
179 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
182 assert(Op.isExpr() && "unknown operand kind in printOperand");
184 << '$' << *Op.getExpr()
189 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
191 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
192 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
193 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
194 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
196 O << markup("<mem:");
198 // If this has a segment register, print it.
199 if (SegReg.getReg()) {
200 printOperand(MI, Op+X86::AddrSegmentReg, O);
204 if (DispSpec.isImm()) {
205 int64_t DispVal = DispSpec.getImm();
206 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
207 O << formatImm(DispVal);
209 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
210 O << *DispSpec.getExpr();
213 if (IndexReg.getReg() || BaseReg.getReg()) {
215 if (BaseReg.getReg())
216 printOperand(MI, Op+X86::AddrBaseReg, O);
218 if (IndexReg.getReg()) {
220 printOperand(MI, Op+X86::AddrIndexReg, O);
221 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
225 << ScaleVal // never printed in hex.
235 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
237 const MCOperand &SegReg = MI->getOperand(Op+1);
239 O << markup("<mem:");
241 // If this has a segment register, print it.
242 if (SegReg.getReg()) {
243 printOperand(MI, Op+1, O);
248 printOperand(MI, Op, O);
254 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
256 O << markup("<mem:");
259 printOperand(MI, Op, O);
265 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
267 const MCOperand &DispSpec = MI->getOperand(Op);
268 const MCOperand &SegReg = MI->getOperand(Op+1);
270 O << markup("<mem:");
272 // If this has a segment register, print it.
273 if (SegReg.getReg()) {
274 printOperand(MI, Op+1, O);
278 if (DispSpec.isImm()) {
279 O << formatImm(DispSpec.getImm());
281 assert(DispSpec.isExpr() && "non-immediate displacement?");
282 O << *DispSpec.getExpr();