1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #include "X86ATTInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86MCTargetDesc.h"
18 #include "X86InstComments.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/Format.h"
26 #include "llvm/Support/FormattedStream.h"
30 #define DEBUG_TYPE "asm-printer"
32 // Include the auto-generated portion of the assembly writer.
33 #define PRINT_ALIAS_INSTR
34 #include "X86GenAsmWriter.inc"
36 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
37 unsigned RegNo) const {
39 << '%' << getRegisterName(RegNo)
43 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
45 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
46 uint64_t TSFlags = Desc.TSFlags;
48 // If verbose assembly is enabled, we can print some informative comments.
50 HasCustomInstComment =
51 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
53 if (TSFlags & X86II::LOCK)
56 // Output CALLpcrel32 as "callq" in 64-bit mode.
57 // In Intel annotation it's always emitted as "call".
59 // TODO: Probably this hack should be redesigned via InstAlias in
60 // InstrInfo.td as soon as Requires clause is supported properly
62 if (MI->getOpcode() == X86::CALLpcrel32 &&
63 (getAvailableFeatures() & X86::Mode64Bit) != 0) {
65 printPCRelImm(MI, 0, OS);
67 // Try to print any aliases first.
68 else if (!printAliasInstr(MI, OS))
69 printInstruction(MI, OS);
71 // Next always print the annotation.
72 printAnnotation(OS, Annot);
75 void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
77 int64_t Imm = MI->getOperand(Op).getImm();
79 default: llvm_unreachable("Invalid ssecc/avxcc argument!");
80 case 0: O << "eq"; break;
81 case 1: O << "lt"; break;
82 case 2: O << "le"; break;
83 case 3: O << "unord"; break;
84 case 4: O << "neq"; break;
85 case 5: O << "nlt"; break;
86 case 6: O << "nle"; break;
87 case 7: O << "ord"; break;
88 case 8: O << "eq_uq"; break;
89 case 9: O << "nge"; break;
90 case 0xa: O << "ngt"; break;
91 case 0xb: O << "false"; break;
92 case 0xc: O << "neq_oq"; break;
93 case 0xd: O << "ge"; break;
94 case 0xe: O << "gt"; break;
95 case 0xf: O << "true"; break;
96 case 0x10: O << "eq_os"; break;
97 case 0x11: O << "lt_oq"; break;
98 case 0x12: O << "le_oq"; break;
99 case 0x13: O << "unord_s"; break;
100 case 0x14: O << "neq_us"; break;
101 case 0x15: O << "nlt_uq"; break;
102 case 0x16: O << "nle_uq"; break;
103 case 0x17: O << "ord_s"; break;
104 case 0x18: O << "eq_us"; break;
105 case 0x19: O << "nge_uq"; break;
106 case 0x1a: O << "ngt_uq"; break;
107 case 0x1b: O << "false_os"; break;
108 case 0x1c: O << "neq_os"; break;
109 case 0x1d: O << "ge_oq"; break;
110 case 0x1e: O << "gt_oq"; break;
111 case 0x1f: O << "true_us"; break;
115 void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
117 int64_t Imm = MI->getOperand(Op).getImm();
119 default: llvm_unreachable("Invalid xopcc argument!");
120 case 0: O << "lt"; break;
121 case 1: O << "le"; break;
122 case 2: O << "gt"; break;
123 case 3: O << "ge"; break;
124 case 4: O << "eq"; break;
125 case 5: O << "neq"; break;
126 case 6: O << "false"; break;
127 case 7: O << "true"; break;
131 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
133 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
135 case 0: O << "{rn-sae}"; break;
136 case 1: O << "{rd-sae}"; break;
137 case 2: O << "{ru-sae}"; break;
138 case 3: O << "{rz-sae}"; break;
141 /// printPCRelImm - This is used to print an immediate value that ends up
142 /// being encoded as a pc-relative value (e.g. for jumps and calls). These
143 /// print slightly differently than normal immediates. For example, a $ is not
145 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
147 const MCOperand &Op = MI->getOperand(OpNo);
149 O << formatImm(Op.getImm());
151 assert(Op.isExpr() && "unknown pcrel immediate operand");
152 // If a symbolic branch target was added as a constant expression then print
153 // that address in hex.
154 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
156 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
157 O << formatHex((uint64_t)Address);
159 // Otherwise, just print the expression.
165 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
167 const MCOperand &Op = MI->getOperand(OpNo);
169 printRegName(O, Op.getReg());
170 } else if (Op.isImm()) {
171 // Print X86 immediates as signed values.
173 << '$' << formatImm((int64_t)Op.getImm())
176 // If there are no instruction-specific comments, add a comment clarifying
177 // the hex value of the immediate operand when it isn't in the range
179 if (CommentStream && !HasCustomInstComment &&
180 (Op.getImm() > 255 || Op.getImm() < -256))
181 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
184 assert(Op.isExpr() && "unknown operand kind in printOperand");
186 << '$' << *Op.getExpr()
191 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
193 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
194 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
195 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
196 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
198 O << markup("<mem:");
200 // If this has a segment register, print it.
201 if (SegReg.getReg()) {
202 printOperand(MI, Op+X86::AddrSegmentReg, O);
206 if (DispSpec.isImm()) {
207 int64_t DispVal = DispSpec.getImm();
208 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
209 O << formatImm(DispVal);
211 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
212 O << *DispSpec.getExpr();
215 if (IndexReg.getReg() || BaseReg.getReg()) {
217 if (BaseReg.getReg())
218 printOperand(MI, Op+X86::AddrBaseReg, O);
220 if (IndexReg.getReg()) {
222 printOperand(MI, Op+X86::AddrIndexReg, O);
223 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
227 << ScaleVal // never printed in hex.
237 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
239 const MCOperand &SegReg = MI->getOperand(Op+1);
241 O << markup("<mem:");
243 // If this has a segment register, print it.
244 if (SegReg.getReg()) {
245 printOperand(MI, Op+1, O);
250 printOperand(MI, Op, O);
256 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
258 O << markup("<mem:");
261 printOperand(MI, Op, O);
267 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
269 const MCOperand &DispSpec = MI->getOperand(Op);
270 const MCOperand &SegReg = MI->getOperand(Op+1);
272 O << markup("<mem:");
274 // If this has a segment register, print it.
275 if (SegReg.getReg()) {
276 printOperand(MI, Op+1, O);
280 if (DispSpec.isImm()) {
281 O << formatImm(DispSpec.getImm());
283 assert(DispSpec.isExpr() && "non-immediate displacement?");
284 O << *DispSpec.getExpr();
290 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
293 << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)