1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86ATTInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "X86Subtarget.h"
19 #include "MCTargetDesc/X86TargetDesc.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/FormattedStream.h"
29 // Include the auto-generated portion of the assembly writer.
30 #define GET_INSTRUCTION_NAME
31 #define PRINT_ALIAS_INSTR
32 #include "X86GenAsmWriter.inc"
34 X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
35 : MCInstPrinter(MAI) {
36 // Initialize the set of available features.
37 setAvailableFeatures(ComputeAvailableFeatures(
38 &TM.getSubtarget<X86Subtarget>()));
41 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
42 unsigned RegNo) const {
43 OS << '%' << getRegisterName(RegNo);
46 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
47 // Try to print any aliases first.
48 if (!printAliasInstr(MI, OS))
49 printInstruction(MI, OS);
51 // If verbose assembly is enabled, we can print some informative comments.
53 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
56 StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
57 return getInstructionName(Opcode);
60 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
62 switch (MI->getOperand(Op).getImm()) {
63 default: assert(0 && "Invalid ssecc argument!");
64 case 0: O << "eq"; break;
65 case 1: O << "lt"; break;
66 case 2: O << "le"; break;
67 case 3: O << "unord"; break;
68 case 4: O << "neq"; break;
69 case 5: O << "nlt"; break;
70 case 6: O << "nle"; break;
71 case 7: O << "ord"; break;
75 /// print_pcrel_imm - This is used to print an immediate value that ends up
76 /// being encoded as a pc-relative value (e.g. for jumps and calls). These
77 /// print slightly differently than normal immediates. For example, a $ is not
79 void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
81 const MCOperand &Op = MI->getOperand(OpNo);
83 // Print this as a signed 32-bit value.
84 O << (int)Op.getImm();
86 assert(Op.isExpr() && "unknown pcrel immediate operand");
91 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
93 const MCOperand &Op = MI->getOperand(OpNo);
95 O << '%' << getRegisterName(Op.getReg());
96 } else if (Op.isImm()) {
97 O << '$' << Op.getImm();
99 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
100 *CommentStream << format("imm = 0x%llX\n", (long long)Op.getImm());
103 assert(Op.isExpr() && "unknown operand kind in printOperand");
104 O << '$' << *Op.getExpr();
108 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
110 const MCOperand &BaseReg = MI->getOperand(Op);
111 const MCOperand &IndexReg = MI->getOperand(Op+2);
112 const MCOperand &DispSpec = MI->getOperand(Op+3);
113 const MCOperand &SegReg = MI->getOperand(Op+4);
115 // If this has a segment register, print it.
116 if (SegReg.getReg()) {
117 printOperand(MI, Op+4, O);
121 if (DispSpec.isImm()) {
122 int64_t DispVal = DispSpec.getImm();
123 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
126 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
127 O << *DispSpec.getExpr();
130 if (IndexReg.getReg() || BaseReg.getReg()) {
132 if (BaseReg.getReg())
133 printOperand(MI, Op, O);
135 if (IndexReg.getReg()) {
137 printOperand(MI, Op+2, O);
138 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
140 O << ',' << ScaleVal;