1 /*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===*
3 * The LLVM Compiler Infrastructure
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
8 *===----------------------------------------------------------------------===*
10 * This file is part of the X86 Disassembler.
11 * It contains the implementation of the instruction decoder.
12 * Documentation for the disassembler can be found in X86Disassembler.h.
14 *===----------------------------------------------------------------------===*/
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 #include "X86GenDisassemblerTables.inc"
29 #define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
31 #define debug(s) do { } while (0)
36 * contextForAttrs - Client for the instruction context table. Takes a set of
37 * attributes and returns the appropriate decode context.
39 * @param attrMask - Attributes, from the enumeration attributeBits.
40 * @return - The InstructionContext to use when looking up an
41 * an instruction with these attributes.
43 static InstructionContext contextForAttrs(uint16_t attrMask) {
44 return CONTEXTS_SYM[attrMask];
48 * modRMRequired - Reads the appropriate instruction table to determine whether
49 * the ModR/M byte is required to decode a particular instruction.
51 * @param type - The opcode type (i.e., how many bytes it has).
52 * @param insnContext - The context for the instruction, as returned by
54 * @param opcode - The last byte of the instruction's opcode, not counting
55 * ModR/M extensions and escapes.
56 * @return - TRUE if the ModR/M byte is required, FALSE otherwise.
58 static int modRMRequired(OpcodeType type,
59 InstructionContext insnContext,
61 const struct ContextDecision* decision = 0;
65 decision = &ONEBYTE_SYM;
68 decision = &TWOBYTE_SYM;
71 decision = &THREEBYTE38_SYM;
74 decision = &THREEBYTE3A_SYM;
77 decision = &THREEBYTEA6_SYM;
80 decision = &THREEBYTEA7_SYM;
83 decision = &XOP8_MAP_SYM;
86 decision = &XOP9_MAP_SYM;
89 decision = &XOPA_MAP_SYM;
93 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
94 modrm_type != MODRM_ONEENTRY;
98 * decode - Reads the appropriate instruction table to obtain the unique ID of
101 * @param type - See modRMRequired().
102 * @param insnContext - See modRMRequired().
103 * @param opcode - See modRMRequired().
104 * @param modRM - The ModR/M byte if required, or any value if not.
105 * @return - The UID of the instruction, or 0 on failure.
107 static InstrUID decode(OpcodeType type,
108 InstructionContext insnContext,
111 const struct ModRMDecision* dec = 0;
115 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
118 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
121 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
124 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
127 dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
130 dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
133 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
136 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
139 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
143 switch (dec->modrm_type) {
145 debug("Corrupt table! Unknown modrm_type");
148 return modRMTable[dec->instructionIDs];
150 if (modFromModRM(modRM) == 0x3)
151 return modRMTable[dec->instructionIDs+1];
152 return modRMTable[dec->instructionIDs];
154 if (modFromModRM(modRM) == 0x3)
155 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
156 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
157 case MODRM_SPLITMISC:
158 if (modFromModRM(modRM) == 0x3)
159 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
160 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
162 return modRMTable[dec->instructionIDs+modRM];
167 * specifierForUID - Given a UID, returns the name and operand specification for
170 * @param uid - The unique ID for the instruction. This should be returned by
171 * decode(); specifierForUID will not check bounds.
172 * @return - A pointer to the specification for that instruction.
174 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
175 return &INSTRUCTIONS_SYM[uid];
179 * consumeByte - Uses the reader function provided by the user to consume one
180 * byte from the instruction's memory and advance the cursor.
182 * @param insn - The instruction with the reader function to use. The cursor
183 * for this instruction is advanced.
184 * @param byte - A pointer to a pre-allocated memory buffer to be populated
185 * with the data read.
186 * @return - 0 if the read was successful; nonzero otherwise.
188 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
189 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
192 ++(insn->readerCursor);
198 * lookAtByte - Like consumeByte, but does not advance the cursor.
200 * @param insn - See consumeByte().
201 * @param byte - See consumeByte().
202 * @return - See consumeByte().
204 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
205 return insn->reader(insn->readerArg, byte, insn->readerCursor);
208 static void unconsumeByte(struct InternalInstruction* insn) {
209 insn->readerCursor--;
212 #define CONSUME_FUNC(name, type) \
213 static int name(struct InternalInstruction* insn, type* ptr) { \
216 for (offset = 0; offset < sizeof(type); ++offset) { \
218 int ret = insn->reader(insn->readerArg, \
220 insn->readerCursor + offset); \
223 combined = combined | ((uint64_t)byte << (offset * 8)); \
226 insn->readerCursor += sizeof(type); \
231 * consume* - Use the reader function provided by the user to consume data
232 * values of various sizes from the instruction's memory and advance the
233 * cursor appropriately. These readers perform endian conversion.
235 * @param insn - See consumeByte().
236 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
237 * be populated with the data read.
238 * @return - See consumeByte().
240 CONSUME_FUNC(consumeInt8, int8_t)
241 CONSUME_FUNC(consumeInt16, int16_t)
242 CONSUME_FUNC(consumeInt32, int32_t)
243 CONSUME_FUNC(consumeUInt16, uint16_t)
244 CONSUME_FUNC(consumeUInt32, uint32_t)
245 CONSUME_FUNC(consumeUInt64, uint64_t)
248 * dbgprintf - Uses the logging function provided by the user to log a single
249 * message, typically without a carriage-return.
251 * @param insn - The instruction containing the logging function.
252 * @param format - See printf().
253 * @param ... - See printf().
255 static void dbgprintf(struct InternalInstruction* insn,
264 va_start(ap, format);
265 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
268 insn->dlog(insn->dlogArg, buffer);
274 * setPrefixPresent - Marks that a particular prefix is present at a particular
277 * @param insn - The instruction to be marked as having the prefix.
278 * @param prefix - The prefix that is present.
279 * @param location - The location where the prefix is located (in the address
280 * space of the instruction's reader).
282 static void setPrefixPresent(struct InternalInstruction* insn,
286 insn->prefixPresent[prefix] = 1;
287 insn->prefixLocations[prefix] = location;
291 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
292 * present at a given location.
294 * @param insn - The instruction to be queried.
295 * @param prefix - The prefix.
296 * @param location - The location to query.
297 * @return - Whether the prefix is at that location.
299 static BOOL isPrefixAtLocation(struct InternalInstruction* insn,
303 if (insn->prefixPresent[prefix] == 1 &&
304 insn->prefixLocations[prefix] == location)
311 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
312 * instruction as having them. Also sets the instruction's default operand,
313 * address, and other relevant data sizes to report operands correctly.
315 * @param insn - The instruction whose prefixes are to be read.
316 * @return - 0 if the instruction could be read until the end of the prefix
317 * bytes, and no prefixes conflicted; nonzero otherwise.
319 static int readPrefixes(struct InternalInstruction* insn) {
320 BOOL isPrefix = TRUE;
321 BOOL prefixGroups[4] = { FALSE };
322 uint64_t prefixLocation;
326 BOOL hasAdSize = FALSE;
327 BOOL hasOpSize = FALSE;
329 dbgprintf(insn, "readPrefixes()");
332 prefixLocation = insn->readerCursor;
334 /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
335 if (consumeByte(insn, &byte))
339 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
340 * break and let it be disassembled as a normal "instruction".
342 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0)
345 if (insn->readerCursor - 1 == insn->startLocation
346 && (byte == 0xf2 || byte == 0xf3)
347 && !lookAtByte(insn, &nextByte))
350 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
352 * - it is followed by a LOCK (0xf0) prefix
353 * - it is followed by an xchg instruction
354 * then it should be disassembled as a xacquire/xrelease not repne/rep.
356 if ((byte == 0xf2 || byte == 0xf3) &&
357 ((nextByte == 0xf0) |
358 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90)))
359 insn->xAcquireRelease = TRUE;
361 * Also if the byte is 0xf3, and the following condition is met:
362 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
363 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
364 * then it should be disassembled as an xrelease not rep.
367 (nextByte == 0x88 || nextByte == 0x89 ||
368 nextByte == 0xc6 || nextByte == 0xc7))
369 insn->xAcquireRelease = TRUE;
370 if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) {
371 if (consumeByte(insn, &nextByte))
373 if (lookAtByte(insn, &nextByte))
377 if (nextByte != 0x0f && nextByte != 0x90)
382 case 0xf0: /* LOCK */
383 case 0xf2: /* REPNE/REPNZ */
384 case 0xf3: /* REP or REPE/REPZ */
386 dbgprintf(insn, "Redundant Group 1 prefix");
387 prefixGroups[0] = TRUE;
388 setPrefixPresent(insn, byte, prefixLocation);
390 case 0x2e: /* CS segment override -OR- Branch not taken */
391 case 0x36: /* SS segment override -OR- Branch taken */
392 case 0x3e: /* DS segment override */
393 case 0x26: /* ES segment override */
394 case 0x64: /* FS segment override */
395 case 0x65: /* GS segment override */
398 insn->segmentOverride = SEG_OVERRIDE_CS;
401 insn->segmentOverride = SEG_OVERRIDE_SS;
404 insn->segmentOverride = SEG_OVERRIDE_DS;
407 insn->segmentOverride = SEG_OVERRIDE_ES;
410 insn->segmentOverride = SEG_OVERRIDE_FS;
413 insn->segmentOverride = SEG_OVERRIDE_GS;
416 debug("Unhandled override");
420 dbgprintf(insn, "Redundant Group 2 prefix");
421 prefixGroups[1] = TRUE;
422 setPrefixPresent(insn, byte, prefixLocation);
424 case 0x66: /* Operand-size override */
426 dbgprintf(insn, "Redundant Group 3 prefix");
427 prefixGroups[2] = TRUE;
429 setPrefixPresent(insn, byte, prefixLocation);
431 case 0x67: /* Address-size override */
433 dbgprintf(insn, "Redundant Group 4 prefix");
434 prefixGroups[3] = TRUE;
436 setPrefixPresent(insn, byte, prefixLocation);
438 default: /* Not a prefix byte */
444 dbgprintf(insn, "Found prefix 0x%hhx", byte);
447 insn->vectorExtensionType = TYPE_NO_VEX_XOP;
450 uint8_t byte1, byte2;
452 if (consumeByte(insn, &byte1)) {
453 dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
457 if (lookAtByte(insn, &byte2)) {
458 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
462 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
463 ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
464 insn->vectorExtensionType = TYPE_EVEX;
467 unconsumeByte(insn); /* unconsume byte1 */
468 unconsumeByte(insn); /* unconsume byte */
469 insn->necessaryPrefixLocation = insn->readerCursor - 2;
472 if (insn->vectorExtensionType == TYPE_EVEX) {
473 insn->vectorExtensionPrefix[0] = byte;
474 insn->vectorExtensionPrefix[1] = byte1;
475 if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
476 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
479 if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
480 dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
484 /* We simulate the REX prefix for simplicity's sake */
485 if (insn->mode == MODE_64BIT) {
486 insn->rexPrefix = 0x40
487 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
488 | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
489 | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
490 | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
493 dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
494 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
495 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
498 else if (byte == 0xc4) {
501 if (lookAtByte(insn, &byte1)) {
502 dbgprintf(insn, "Couldn't read second byte of VEX");
506 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
507 insn->vectorExtensionType = TYPE_VEX_3B;
508 insn->necessaryPrefixLocation = insn->readerCursor - 1;
512 insn->necessaryPrefixLocation = insn->readerCursor - 1;
515 if (insn->vectorExtensionType == TYPE_VEX_3B) {
516 insn->vectorExtensionPrefix[0] = byte;
517 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
518 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
520 /* We simulate the REX prefix for simplicity's sake */
522 if (insn->mode == MODE_64BIT) {
523 insn->rexPrefix = 0x40
524 | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
525 | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
526 | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
527 | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
530 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
531 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
532 insn->vectorExtensionPrefix[2]);
535 else if (byte == 0xc5) {
538 if (lookAtByte(insn, &byte1)) {
539 dbgprintf(insn, "Couldn't read second byte of VEX");
543 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
544 insn->vectorExtensionType = TYPE_VEX_2B;
550 if (insn->vectorExtensionType == TYPE_VEX_2B) {
551 insn->vectorExtensionPrefix[0] = byte;
552 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
554 if (insn->mode == MODE_64BIT) {
555 insn->rexPrefix = 0x40
556 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
559 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1]))
568 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
569 insn->vectorExtensionPrefix[0],
570 insn->vectorExtensionPrefix[1]);
573 else if (byte == 0x8f) {
576 if (lookAtByte(insn, &byte1)) {
577 dbgprintf(insn, "Couldn't read second byte of XOP");
581 if ((byte1 & 0x38) != 0x0) { /* 0 in these 3 bits is a POP instruction. */
582 insn->vectorExtensionType = TYPE_XOP;
583 insn->necessaryPrefixLocation = insn->readerCursor - 1;
587 insn->necessaryPrefixLocation = insn->readerCursor - 1;
590 if (insn->vectorExtensionType == TYPE_XOP) {
591 insn->vectorExtensionPrefix[0] = byte;
592 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
593 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
595 /* We simulate the REX prefix for simplicity's sake */
597 if (insn->mode == MODE_64BIT) {
598 insn->rexPrefix = 0x40
599 | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
600 | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
601 | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
602 | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
605 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2]))
614 dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
615 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
616 insn->vectorExtensionPrefix[2]);
620 if (insn->mode == MODE_64BIT) {
621 if ((byte & 0xf0) == 0x40) {
624 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
625 dbgprintf(insn, "Redundant REX prefix");
629 insn->rexPrefix = byte;
630 insn->necessaryPrefixLocation = insn->readerCursor - 2;
632 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
635 insn->necessaryPrefixLocation = insn->readerCursor - 1;
639 insn->necessaryPrefixLocation = insn->readerCursor - 1;
643 if (insn->mode == MODE_16BIT) {
644 insn->registerSize = (hasOpSize ? 4 : 2);
645 insn->addressSize = (hasAdSize ? 4 : 2);
646 insn->displacementSize = (hasAdSize ? 4 : 2);
647 insn->immediateSize = (hasOpSize ? 4 : 2);
648 } else if (insn->mode == MODE_32BIT) {
649 insn->registerSize = (hasOpSize ? 2 : 4);
650 insn->addressSize = (hasAdSize ? 2 : 4);
651 insn->displacementSize = (hasAdSize ? 2 : 4);
652 insn->immediateSize = (hasOpSize ? 2 : 4);
653 } else if (insn->mode == MODE_64BIT) {
654 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
655 insn->registerSize = 8;
656 insn->addressSize = (hasAdSize ? 4 : 8);
657 insn->displacementSize = 4;
658 insn->immediateSize = 4;
659 } else if (insn->rexPrefix) {
660 insn->registerSize = (hasOpSize ? 2 : 4);
661 insn->addressSize = (hasAdSize ? 4 : 8);
662 insn->displacementSize = (hasOpSize ? 2 : 4);
663 insn->immediateSize = (hasOpSize ? 2 : 4);
665 insn->registerSize = (hasOpSize ? 2 : 4);
666 insn->addressSize = (hasAdSize ? 4 : 8);
667 insn->displacementSize = (hasOpSize ? 2 : 4);
668 insn->immediateSize = (hasOpSize ? 2 : 4);
676 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
677 * extended or escape opcodes).
679 * @param insn - The instruction whose opcode is to be read.
680 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
682 static int readOpcode(struct InternalInstruction* insn) {
683 /* Determine the length of the primary opcode */
687 dbgprintf(insn, "readOpcode()");
689 insn->opcodeType = ONEBYTE;
691 if (insn->vectorExtensionType == TYPE_EVEX)
693 switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
695 dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
696 mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
699 insn->opcodeType = TWOBYTE;
700 return consumeByte(insn, &insn->opcode);
702 insn->opcodeType = THREEBYTE_38;
703 return consumeByte(insn, &insn->opcode);
705 insn->opcodeType = THREEBYTE_3A;
706 return consumeByte(insn, &insn->opcode);
709 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
710 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
712 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
713 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
716 insn->opcodeType = TWOBYTE;
717 return consumeByte(insn, &insn->opcode);
719 insn->opcodeType = THREEBYTE_38;
720 return consumeByte(insn, &insn->opcode);
722 insn->opcodeType = THREEBYTE_3A;
723 return consumeByte(insn, &insn->opcode);
726 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
727 insn->opcodeType = TWOBYTE;
728 return consumeByte(insn, &insn->opcode);
730 else if (insn->vectorExtensionType == TYPE_XOP) {
731 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
733 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
734 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
736 case XOP_MAP_SELECT_8:
737 insn->opcodeType = XOP8_MAP;
738 return consumeByte(insn, &insn->opcode);
739 case XOP_MAP_SELECT_9:
740 insn->opcodeType = XOP9_MAP;
741 return consumeByte(insn, &insn->opcode);
742 case XOP_MAP_SELECT_A:
743 insn->opcodeType = XOPA_MAP;
744 return consumeByte(insn, &insn->opcode);
748 if (consumeByte(insn, ¤t))
751 if (current == 0x0f) {
752 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
754 if (consumeByte(insn, ¤t))
757 if (current == 0x38) {
758 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
760 if (consumeByte(insn, ¤t))
763 insn->opcodeType = THREEBYTE_38;
764 } else if (current == 0x3a) {
765 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
767 if (consumeByte(insn, ¤t))
770 insn->opcodeType = THREEBYTE_3A;
771 } else if (current == 0xa6) {
772 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
774 if (consumeByte(insn, ¤t))
777 insn->opcodeType = THREEBYTE_A6;
778 } else if (current == 0xa7) {
779 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
781 if (consumeByte(insn, ¤t))
784 insn->opcodeType = THREEBYTE_A7;
786 dbgprintf(insn, "Didn't find a three-byte escape prefix");
788 insn->opcodeType = TWOBYTE;
793 * At this point we have consumed the full opcode.
794 * Anything we consume from here on must be unconsumed.
797 insn->opcode = current;
802 static int readModRM(struct InternalInstruction* insn);
805 * getIDWithAttrMask - Determines the ID of an instruction, consuming
806 * the ModR/M byte as appropriate for extended and escape opcodes,
807 * and using a supplied attribute mask.
809 * @param instructionID - A pointer whose target is filled in with the ID of the
811 * @param insn - The instruction whose ID is to be determined.
812 * @param attrMask - The attribute mask to search.
813 * @return - 0 if the ModR/M could be read when needed or was not
814 * needed; nonzero otherwise.
816 static int getIDWithAttrMask(uint16_t* instructionID,
817 struct InternalInstruction* insn,
819 BOOL hasModRMExtension;
821 uint16_t instructionClass;
823 instructionClass = contextForAttrs(attrMask);
825 hasModRMExtension = modRMRequired(insn->opcodeType,
829 if (hasModRMExtension) {
833 *instructionID = decode(insn->opcodeType,
838 *instructionID = decode(insn->opcodeType,
848 * is16BitEquivalent - Determines whether two instruction names refer to
849 * equivalent instructions but one is 16-bit whereas the other is not.
851 * @param orig - The instruction that is not 16-bit
852 * @param equiv - The instruction that is 16-bit
854 static BOOL is16BitEquivalent(const char* orig, const char* equiv) {
858 if (orig[i] == '\0' && equiv[i] == '\0')
860 if (orig[i] == '\0' || equiv[i] == '\0')
862 if (orig[i] != equiv[i]) {
863 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
865 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
867 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
875 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
876 * appropriate for extended and escape opcodes. Determines the attributes and
877 * context for the instruction before doing so.
879 * @param insn - The instruction whose ID is to be determined.
880 * @return - 0 if the ModR/M could be read when needed or was not needed;
883 static int getID(struct InternalInstruction* insn, const void *miiArg) {
885 uint16_t instructionID;
887 dbgprintf(insn, "getID()");
889 attrMask = ATTR_NONE;
891 if (insn->mode == MODE_64BIT)
892 attrMask |= ATTR_64BIT;
894 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
895 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
897 if (insn->vectorExtensionType == TYPE_EVEX) {
898 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
900 attrMask |= ATTR_OPSIZE;
910 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
911 attrMask |= ATTR_EVEXKZ;
912 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
913 attrMask |= ATTR_EVEXB;
914 if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
915 attrMask |= ATTR_EVEXK;
916 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
917 attrMask |= ATTR_EVEXL;
918 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
919 attrMask |= ATTR_EVEXL2;
921 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
922 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
924 attrMask |= ATTR_OPSIZE;
934 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
935 attrMask |= ATTR_VEXL;
937 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
938 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
940 attrMask |= ATTR_OPSIZE;
950 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
951 attrMask |= ATTR_VEXL;
953 else if (insn->vectorExtensionType == TYPE_XOP) {
954 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
956 attrMask |= ATTR_OPSIZE;
966 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
967 attrMask |= ATTR_VEXL;
974 if (insn->mode != MODE_16BIT && isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
975 attrMask |= ATTR_OPSIZE;
976 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
977 attrMask |= ATTR_ADSIZE;
978 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
980 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
984 if (insn->rexPrefix & 0x08)
985 attrMask |= ATTR_REXW;
987 if (getIDWithAttrMask(&instructionID, insn, attrMask))
991 * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
992 * of the AdSize prefix is inverted w.r.t. 32-bit mode.
994 if (insn->mode == MODE_16BIT && insn->opcode == 0xE3) {
995 const struct InstructionSpecifier *spec;
996 spec = specifierForUID(instructionID);
999 * Check for Ii8PCRel instructions. We could alternatively do a
1000 * string-compare on the names, but this is probably cheaper.
1002 if (x86OperandSets[spec->operands][0].type == TYPE_REL8) {
1003 attrMask ^= ATTR_ADSIZE;
1004 if (getIDWithAttrMask(&instructionID, insn, attrMask))
1009 /* The following clauses compensate for limitations of the tables. */
1011 if ((insn->mode == MODE_16BIT || insn->prefixPresent[0x66]) &&
1012 !(attrMask & ATTR_OPSIZE)) {
1014 * The instruction tables make no distinction between instructions that
1015 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1016 * particular spot (i.e., many MMX operations). In general we're
1017 * conservative, but in the specific case where OpSize is present but not
1018 * in the right place we check if there's a 16-bit operation.
1021 const struct InstructionSpecifier *spec;
1022 uint16_t instructionIDWithOpsize;
1023 const char *specName, *specWithOpSizeName;
1025 spec = specifierForUID(instructionID);
1027 if (getIDWithAttrMask(&instructionIDWithOpsize,
1029 attrMask | ATTR_OPSIZE)) {
1031 * ModRM required with OpSize but not present; give up and return version
1032 * without OpSize set
1035 insn->instructionID = instructionID;
1040 specName = x86DisassemblerGetInstrName(instructionID, miiArg);
1041 specWithOpSizeName =
1042 x86DisassemblerGetInstrName(instructionIDWithOpsize, miiArg);
1044 if (is16BitEquivalent(specName, specWithOpSizeName) &&
1045 (insn->mode == MODE_16BIT) ^ insn->prefixPresent[0x66]) {
1046 insn->instructionID = instructionIDWithOpsize;
1047 insn->spec = specifierForUID(instructionIDWithOpsize);
1049 insn->instructionID = instructionID;
1055 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1056 insn->rexPrefix & 0x01) {
1058 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1059 * it should decode as XCHG %r8, %eax.
1062 const struct InstructionSpecifier *spec;
1063 uint16_t instructionIDWithNewOpcode;
1064 const struct InstructionSpecifier *specWithNewOpcode;
1066 spec = specifierForUID(instructionID);
1068 /* Borrow opcode from one of the other XCHGar opcodes */
1069 insn->opcode = 0x91;
1071 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1074 insn->opcode = 0x90;
1076 insn->instructionID = instructionID;
1081 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1084 insn->opcode = 0x90;
1086 insn->instructionID = instructionIDWithNewOpcode;
1087 insn->spec = specWithNewOpcode;
1092 insn->instructionID = instructionID;
1093 insn->spec = specifierForUID(insn->instructionID);
1099 * readSIB - Consumes the SIB byte to determine addressing information for an
1102 * @param insn - The instruction whose SIB byte is to be read.
1103 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
1105 static int readSIB(struct InternalInstruction* insn) {
1106 SIBIndex sibIndexBase = 0;
1107 SIBBase sibBaseBase = 0;
1108 uint8_t index, base;
1110 dbgprintf(insn, "readSIB()");
1112 if (insn->consumedSIB)
1115 insn->consumedSIB = TRUE;
1117 switch (insn->addressSize) {
1119 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1123 sibIndexBase = SIB_INDEX_EAX;
1124 sibBaseBase = SIB_BASE_EAX;
1127 sibIndexBase = SIB_INDEX_RAX;
1128 sibBaseBase = SIB_BASE_RAX;
1132 if (consumeByte(insn, &insn->sib))
1135 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1136 if (insn->vectorExtensionType == TYPE_EVEX)
1137 index |= v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4;
1141 insn->sibIndex = SIB_INDEX_NONE;
1144 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
1145 if (insn->sibIndex == SIB_INDEX_sib ||
1146 insn->sibIndex == SIB_INDEX_sib64)
1147 insn->sibIndex = SIB_INDEX_NONE;
1151 switch (scaleFromSIB(insn->sib)) {
1166 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1170 switch (modFromModRM(insn->modRM)) {
1172 insn->eaDisplacement = EA_DISP_32;
1173 insn->sibBase = SIB_BASE_NONE;
1176 insn->eaDisplacement = EA_DISP_8;
1177 insn->sibBase = (insn->addressSize == 4 ?
1178 SIB_BASE_EBP : SIB_BASE_RBP);
1181 insn->eaDisplacement = EA_DISP_32;
1182 insn->sibBase = (insn->addressSize == 4 ?
1183 SIB_BASE_EBP : SIB_BASE_RBP);
1186 debug("Cannot have Mod = 0b11 and a SIB byte");
1191 insn->sibBase = (SIBBase)(sibBaseBase + base);
1199 * readDisplacement - Consumes the displacement of an instruction.
1201 * @param insn - The instruction whose displacement is to be read.
1202 * @return - 0 if the displacement byte was successfully read; nonzero
1205 static int readDisplacement(struct InternalInstruction* insn) {
1210 dbgprintf(insn, "readDisplacement()");
1212 if (insn->consumedDisplacement)
1215 insn->consumedDisplacement = TRUE;
1216 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1218 switch (insn->eaDisplacement) {
1220 insn->consumedDisplacement = FALSE;
1223 if (consumeInt8(insn, &d8))
1225 insn->displacement = d8;
1228 if (consumeInt16(insn, &d16))
1230 insn->displacement = d16;
1233 if (consumeInt32(insn, &d32))
1235 insn->displacement = d32;
1239 insn->consumedDisplacement = TRUE;
1244 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1245 * displacement) for an instruction and interprets it.
1247 * @param insn - The instruction whose addressing information is to be read.
1248 * @return - 0 if the information was successfully read; nonzero otherwise.
1250 static int readModRM(struct InternalInstruction* insn) {
1251 uint8_t mod, rm, reg;
1253 dbgprintf(insn, "readModRM()");
1255 if (insn->consumedModRM)
1258 if (consumeByte(insn, &insn->modRM))
1260 insn->consumedModRM = TRUE;
1262 mod = modFromModRM(insn->modRM);
1263 rm = rmFromModRM(insn->modRM);
1264 reg = regFromModRM(insn->modRM);
1267 * This goes by insn->registerSize to pick the correct register, which messes
1268 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1271 switch (insn->registerSize) {
1273 insn->regBase = MODRM_REG_AX;
1274 insn->eaRegBase = EA_REG_AX;
1277 insn->regBase = MODRM_REG_EAX;
1278 insn->eaRegBase = EA_REG_EAX;
1281 insn->regBase = MODRM_REG_RAX;
1282 insn->eaRegBase = EA_REG_RAX;
1286 reg |= rFromREX(insn->rexPrefix) << 3;
1287 rm |= bFromREX(insn->rexPrefix) << 3;
1288 if (insn->vectorExtensionType == TYPE_EVEX) {
1289 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1290 rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1293 insn->reg = (Reg)(insn->regBase + reg);
1295 switch (insn->addressSize) {
1297 insn->eaBaseBase = EA_BASE_BX_SI;
1302 insn->eaBase = EA_BASE_NONE;
1303 insn->eaDisplacement = EA_DISP_16;
1304 if (readDisplacement(insn))
1307 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1308 insn->eaDisplacement = EA_DISP_NONE;
1312 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1313 insn->eaDisplacement = EA_DISP_8;
1314 insn->displacementSize = 1;
1315 if (readDisplacement(insn))
1319 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1320 insn->eaDisplacement = EA_DISP_16;
1321 if (readDisplacement(insn))
1325 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1326 if (readDisplacement(insn))
1333 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1337 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1341 case 0xc: /* in case REXW.b is set */
1342 insn->eaBase = (insn->addressSize == 4 ?
1343 EA_BASE_sib : EA_BASE_sib64);
1345 if (readDisplacement(insn))
1349 insn->eaBase = EA_BASE_NONE;
1350 insn->eaDisplacement = EA_DISP_32;
1351 if (readDisplacement(insn))
1355 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1360 insn->displacementSize = 1;
1363 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1367 case 0xc: /* in case REXW.b is set */
1368 insn->eaBase = EA_BASE_sib;
1370 if (readDisplacement(insn))
1374 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1375 if (readDisplacement(insn))
1381 insn->eaDisplacement = EA_DISP_NONE;
1382 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1386 } /* switch (insn->addressSize) */
1391 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1392 static uint8_t name(struct InternalInstruction *insn, \
1399 debug("Unhandled register type"); \
1403 return base + index; \
1405 if (insn->rexPrefix && \
1406 index >= 4 && index <= 7) { \
1407 return prefix##_SPL + (index - 4); \
1409 return prefix##_AL + index; \
1412 return prefix##_AX + index; \
1414 return prefix##_EAX + index; \
1416 return prefix##_RAX + index; \
1418 return prefix##_ZMM0 + index; \
1420 return prefix##_YMM0 + index; \
1425 return prefix##_XMM0 + index; \
1429 return prefix##_K0 + index; \
1435 return prefix##_MM0 + index; \
1436 case TYPE_SEGMENTREG: \
1439 return prefix##_ES + index; \
1440 case TYPE_DEBUGREG: \
1443 return prefix##_DR0 + index; \
1444 case TYPE_CONTROLREG: \
1447 return prefix##_CR0 + index; \
1452 * fixup*Value - Consults an operand type to determine the meaning of the
1453 * reg or R/M field. If the operand is an XMM operand, for example, an
1454 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1455 * misinterpret it as.
1457 * @param insn - The instruction containing the operand.
1458 * @param type - The operand type.
1459 * @param index - The existing value of the field as reported by readModRM().
1460 * @param valid - The address of a uint8_t. The target is set to 1 if the
1461 * field is valid for the register class; 0 if not.
1462 * @return - The proper value.
1464 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1465 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1468 * fixupReg - Consults an operand specifier to determine which of the
1469 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1471 * @param insn - See fixup*Value().
1472 * @param op - The operand specifier.
1473 * @return - 0 if fixup was successful; -1 if the register returned was
1474 * invalid for its class.
1476 static int fixupReg(struct InternalInstruction *insn,
1477 const struct OperandSpecifier *op) {
1480 dbgprintf(insn, "fixupReg()");
1482 switch ((OperandEncoding)op->encoding) {
1484 debug("Expected a REG or R/M encoding in fixupReg");
1487 insn->vvvv = (Reg)fixupRegValue(insn,
1488 (OperandType)op->type,
1495 insn->reg = (Reg)fixupRegValue(insn,
1496 (OperandType)op->type,
1497 insn->reg - insn->regBase,
1503 if (insn->eaBase >= insn->eaRegBase) {
1504 insn->eaBase = (EABase)fixupRMValue(insn,
1505 (OperandType)op->type,
1506 insn->eaBase - insn->eaRegBase,
1518 * readOpcodeRegister - Reads an operand from the opcode field of an
1519 * instruction and interprets it appropriately given the operand width.
1520 * Handles AddRegFrm instructions.
1522 * @param insn - the instruction whose opcode field is to be read.
1523 * @param size - The width (in bytes) of the register being specified.
1524 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1526 * @return - 0 on success; nonzero otherwise.
1528 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1529 dbgprintf(insn, "readOpcodeRegister()");
1532 size = insn->registerSize;
1536 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1537 | (insn->opcode & 7)));
1538 if (insn->rexPrefix &&
1539 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1540 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1541 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1542 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1547 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1548 + ((bFromREX(insn->rexPrefix) << 3)
1549 | (insn->opcode & 7)));
1552 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1553 + ((bFromREX(insn->rexPrefix) << 3)
1554 | (insn->opcode & 7)));
1557 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1558 + ((bFromREX(insn->rexPrefix) << 3)
1559 | (insn->opcode & 7)));
1567 * readImmediate - Consumes an immediate operand from an instruction, given the
1568 * desired operand size.
1570 * @param insn - The instruction whose operand is to be read.
1571 * @param size - The width (in bytes) of the operand.
1572 * @return - 0 if the immediate was successfully consumed; nonzero
1575 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1581 dbgprintf(insn, "readImmediate()");
1583 if (insn->numImmediatesConsumed == 2) {
1584 debug("Already consumed two immediates");
1589 size = insn->immediateSize;
1591 insn->immediateSize = size;
1592 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1596 if (consumeByte(insn, &imm8))
1598 insn->immediates[insn->numImmediatesConsumed] = imm8;
1601 if (consumeUInt16(insn, &imm16))
1603 insn->immediates[insn->numImmediatesConsumed] = imm16;
1606 if (consumeUInt32(insn, &imm32))
1608 insn->immediates[insn->numImmediatesConsumed] = imm32;
1611 if (consumeUInt64(insn, &imm64))
1613 insn->immediates[insn->numImmediatesConsumed] = imm64;
1617 insn->numImmediatesConsumed++;
1623 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1625 * @param insn - The instruction whose operand is to be read.
1626 * @return - 0 if the vvvv was successfully consumed; nonzero
1629 static int readVVVV(struct InternalInstruction* insn) {
1630 dbgprintf(insn, "readVVVV()");
1632 if (insn->vectorExtensionType == TYPE_EVEX)
1633 insn->vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
1634 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1635 insn->vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1636 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1637 insn->vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1638 else if (insn->vectorExtensionType == TYPE_XOP)
1639 insn->vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1643 if (insn->mode != MODE_64BIT)
1650 * readMaskRegister - Reads an mask register from the opcode field of an
1653 * @param insn - The instruction whose opcode field is to be read.
1654 * @return - 0 on success; nonzero otherwise.
1656 static int readMaskRegister(struct InternalInstruction* insn) {
1657 dbgprintf(insn, "readMaskRegister()");
1659 if (insn->vectorExtensionType != TYPE_EVEX)
1662 insn->writemask = aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]);
1667 * readOperands - Consults the specifier for an instruction and consumes all
1668 * operands for that instruction, interpreting them as it goes.
1670 * @param insn - The instruction whose operands are to be read and interpreted.
1671 * @return - 0 if all operands could be read; nonzero otherwise.
1673 static int readOperands(struct InternalInstruction* insn) {
1675 int hasVVVV, needVVVV;
1678 dbgprintf(insn, "readOperands()");
1680 /* If non-zero vvvv specified, need to make sure one of the operands
1682 hasVVVV = !readVVVV(insn);
1683 needVVVV = hasVVVV && (insn->vvvv != 0);
1685 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1686 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1693 if (readModRM(insn))
1695 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1704 dbgprintf(insn, "We currently don't hande code-offset encodings");
1708 /* Saw a register immediate so don't read again and instead split the
1709 previous immediate. FIXME: This is a hack. */
1710 insn->immediates[insn->numImmediatesConsumed] =
1711 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1712 ++insn->numImmediatesConsumed;
1715 if (readImmediate(insn, 1))
1717 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1718 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1720 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1721 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1723 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1724 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1728 if (readImmediate(insn, 2))
1732 if (readImmediate(insn, 4))
1736 if (readImmediate(insn, 8))
1740 if (readImmediate(insn, insn->immediateSize))
1744 if (readImmediate(insn, insn->addressSize))
1748 if (readOpcodeRegister(insn, 1))
1752 if (readOpcodeRegister(insn, 2))
1756 if (readOpcodeRegister(insn, 4))
1760 if (readOpcodeRegister(insn, 8))
1764 if (readOpcodeRegister(insn, 0))
1770 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1773 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1776 case ENCODING_WRITEMASK:
1777 if (readMaskRegister(insn))
1783 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1788 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1789 if (needVVVV) return -1;
1795 * decodeInstruction - Reads and interprets a full instruction provided by the
1798 * @param insn - A pointer to the instruction to be populated. Must be
1800 * @param reader - The function to be used to read the instruction's bytes.
1801 * @param readerArg - A generic argument to be passed to the reader to store
1802 * any internal state.
1803 * @param logger - If non-NULL, the function to be used to write log messages
1805 * @param loggerArg - A generic argument to be passed to the logger to store
1806 * any internal state.
1807 * @param startLoc - The address (in the reader's address space) of the first
1808 * byte in the instruction.
1809 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1810 * decode the instruction in.
1811 * @return - 0 if the instruction's memory could be read; nonzero if
1814 int decodeInstruction(struct InternalInstruction* insn,
1815 byteReader_t reader,
1816 const void* readerArg,
1821 DisassemblerMode mode) {
1822 memset(insn, 0, sizeof(struct InternalInstruction));
1824 insn->reader = reader;
1825 insn->readerArg = readerArg;
1826 insn->dlog = logger;
1827 insn->dlogArg = loggerArg;
1828 insn->startLocation = startLoc;
1829 insn->readerCursor = startLoc;
1831 insn->numImmediatesConsumed = 0;
1833 if (readPrefixes(insn) ||
1835 getID(insn, miiArg) ||
1836 insn->instructionID == 0 ||
1840 insn->operands = &x86OperandSets[insn->spec->operands][0];
1842 insn->length = insn->readerCursor - insn->startLocation;
1844 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1845 startLoc, insn->readerCursor, insn->length);
1847 if (insn->length > 15)
1848 dbgprintf(insn, "Instruction exceeds 15-byte limit");