1 /*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===*
3 * The LLVM Compiler Infrastructure
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
8 *===----------------------------------------------------------------------===*
10 * This file is part of the X86 Disassembler.
11 * It contains the implementation of the instruction decoder.
12 * Documentation for the disassembler can be found in X86Disassembler.h.
14 *===----------------------------------------------------------------------===*/
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 #include "X86GenDisassemblerTables.inc"
29 #define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
31 #define debug(s) do { } while (0)
36 * contextForAttrs - Client for the instruction context table. Takes a set of
37 * attributes and returns the appropriate decode context.
39 * @param attrMask - Attributes, from the enumeration attributeBits.
40 * @return - The InstructionContext to use when looking up an
41 * an instruction with these attributes.
43 static InstructionContext contextForAttrs(uint16_t attrMask) {
44 return CONTEXTS_SYM[attrMask];
48 * modRMRequired - Reads the appropriate instruction table to determine whether
49 * the ModR/M byte is required to decode a particular instruction.
51 * @param type - The opcode type (i.e., how many bytes it has).
52 * @param insnContext - The context for the instruction, as returned by
54 * @param opcode - The last byte of the instruction's opcode, not counting
55 * ModR/M extensions and escapes.
56 * @return - TRUE if the ModR/M byte is required, FALSE otherwise.
58 static int modRMRequired(OpcodeType type,
59 InstructionContext insnContext,
61 const struct ContextDecision* decision = 0;
65 decision = &ONEBYTE_SYM;
68 decision = &TWOBYTE_SYM;
71 decision = &THREEBYTE38_SYM;
74 decision = &THREEBYTE3A_SYM;
77 decision = &XOP8_MAP_SYM;
80 decision = &XOP9_MAP_SYM;
83 decision = &XOPA_MAP_SYM;
87 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
88 modrm_type != MODRM_ONEENTRY;
92 * decode - Reads the appropriate instruction table to obtain the unique ID of
95 * @param type - See modRMRequired().
96 * @param insnContext - See modRMRequired().
97 * @param opcode - See modRMRequired().
98 * @param modRM - The ModR/M byte if required, or any value if not.
99 * @return - The UID of the instruction, or 0 on failure.
101 static InstrUID decode(OpcodeType type,
102 InstructionContext insnContext,
105 const struct ModRMDecision* dec = 0;
109 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
112 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
115 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
118 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
121 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
124 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
127 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
131 switch (dec->modrm_type) {
133 debug("Corrupt table! Unknown modrm_type");
136 return modRMTable[dec->instructionIDs];
138 if (modFromModRM(modRM) == 0x3)
139 return modRMTable[dec->instructionIDs+1];
140 return modRMTable[dec->instructionIDs];
142 if (modFromModRM(modRM) == 0x3)
143 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
144 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
145 case MODRM_SPLITMISC:
146 if (modFromModRM(modRM) == 0x3)
147 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
148 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
150 return modRMTable[dec->instructionIDs+modRM];
155 * specifierForUID - Given a UID, returns the name and operand specification for
158 * @param uid - The unique ID for the instruction. This should be returned by
159 * decode(); specifierForUID will not check bounds.
160 * @return - A pointer to the specification for that instruction.
162 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
163 return &INSTRUCTIONS_SYM[uid];
167 * consumeByte - Uses the reader function provided by the user to consume one
168 * byte from the instruction's memory and advance the cursor.
170 * @param insn - The instruction with the reader function to use. The cursor
171 * for this instruction is advanced.
172 * @param byte - A pointer to a pre-allocated memory buffer to be populated
173 * with the data read.
174 * @return - 0 if the read was successful; nonzero otherwise.
176 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
177 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
180 ++(insn->readerCursor);
186 * lookAtByte - Like consumeByte, but does not advance the cursor.
188 * @param insn - See consumeByte().
189 * @param byte - See consumeByte().
190 * @return - See consumeByte().
192 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
193 return insn->reader(insn->readerArg, byte, insn->readerCursor);
196 static void unconsumeByte(struct InternalInstruction* insn) {
197 insn->readerCursor--;
200 #define CONSUME_FUNC(name, type) \
201 static int name(struct InternalInstruction* insn, type* ptr) { \
204 for (offset = 0; offset < sizeof(type); ++offset) { \
206 int ret = insn->reader(insn->readerArg, \
208 insn->readerCursor + offset); \
211 combined = combined | ((uint64_t)byte << (offset * 8)); \
214 insn->readerCursor += sizeof(type); \
219 * consume* - Use the reader function provided by the user to consume data
220 * values of various sizes from the instruction's memory and advance the
221 * cursor appropriately. These readers perform endian conversion.
223 * @param insn - See consumeByte().
224 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
225 * be populated with the data read.
226 * @return - See consumeByte().
228 CONSUME_FUNC(consumeInt8, int8_t)
229 CONSUME_FUNC(consumeInt16, int16_t)
230 CONSUME_FUNC(consumeInt32, int32_t)
231 CONSUME_FUNC(consumeUInt16, uint16_t)
232 CONSUME_FUNC(consumeUInt32, uint32_t)
233 CONSUME_FUNC(consumeUInt64, uint64_t)
236 * dbgprintf - Uses the logging function provided by the user to log a single
237 * message, typically without a carriage-return.
239 * @param insn - The instruction containing the logging function.
240 * @param format - See printf().
241 * @param ... - See printf().
243 static void dbgprintf(struct InternalInstruction* insn,
252 va_start(ap, format);
253 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
256 insn->dlog(insn->dlogArg, buffer);
262 * setPrefixPresent - Marks that a particular prefix is present at a particular
265 * @param insn - The instruction to be marked as having the prefix.
266 * @param prefix - The prefix that is present.
267 * @param location - The location where the prefix is located (in the address
268 * space of the instruction's reader).
270 static void setPrefixPresent(struct InternalInstruction* insn,
274 insn->prefixPresent[prefix] = 1;
275 insn->prefixLocations[prefix] = location;
279 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
280 * present at a given location.
282 * @param insn - The instruction to be queried.
283 * @param prefix - The prefix.
284 * @param location - The location to query.
285 * @return - Whether the prefix is at that location.
287 static BOOL isPrefixAtLocation(struct InternalInstruction* insn,
291 if (insn->prefixPresent[prefix] == 1 &&
292 insn->prefixLocations[prefix] == location)
299 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
300 * instruction as having them. Also sets the instruction's default operand,
301 * address, and other relevant data sizes to report operands correctly.
303 * @param insn - The instruction whose prefixes are to be read.
304 * @return - 0 if the instruction could be read until the end of the prefix
305 * bytes, and no prefixes conflicted; nonzero otherwise.
307 static int readPrefixes(struct InternalInstruction* insn) {
308 BOOL isPrefix = TRUE;
309 BOOL prefixGroups[4] = { FALSE };
310 uint64_t prefixLocation;
314 BOOL hasAdSize = FALSE;
315 BOOL hasOpSize = FALSE;
317 dbgprintf(insn, "readPrefixes()");
320 prefixLocation = insn->readerCursor;
322 /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
323 if (consumeByte(insn, &byte))
327 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
328 * break and let it be disassembled as a normal "instruction".
330 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0)
333 if (insn->readerCursor - 1 == insn->startLocation
334 && (byte == 0xf2 || byte == 0xf3)
335 && !lookAtByte(insn, &nextByte))
338 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
340 * - it is followed by a LOCK (0xf0) prefix
341 * - it is followed by an xchg instruction
342 * then it should be disassembled as a xacquire/xrelease not repne/rep.
344 if ((byte == 0xf2 || byte == 0xf3) &&
345 ((nextByte == 0xf0) |
346 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90)))
347 insn->xAcquireRelease = TRUE;
349 * Also if the byte is 0xf3, and the following condition is met:
350 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
351 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
352 * then it should be disassembled as an xrelease not rep.
355 (nextByte == 0x88 || nextByte == 0x89 ||
356 nextByte == 0xc6 || nextByte == 0xc7))
357 insn->xAcquireRelease = TRUE;
358 if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) {
359 if (consumeByte(insn, &nextByte))
361 if (lookAtByte(insn, &nextByte))
365 if (nextByte != 0x0f && nextByte != 0x90)
370 case 0xf0: /* LOCK */
371 case 0xf2: /* REPNE/REPNZ */
372 case 0xf3: /* REP or REPE/REPZ */
374 dbgprintf(insn, "Redundant Group 1 prefix");
375 prefixGroups[0] = TRUE;
376 setPrefixPresent(insn, byte, prefixLocation);
378 case 0x2e: /* CS segment override -OR- Branch not taken */
379 case 0x36: /* SS segment override -OR- Branch taken */
380 case 0x3e: /* DS segment override */
381 case 0x26: /* ES segment override */
382 case 0x64: /* FS segment override */
383 case 0x65: /* GS segment override */
386 insn->segmentOverride = SEG_OVERRIDE_CS;
389 insn->segmentOverride = SEG_OVERRIDE_SS;
392 insn->segmentOverride = SEG_OVERRIDE_DS;
395 insn->segmentOverride = SEG_OVERRIDE_ES;
398 insn->segmentOverride = SEG_OVERRIDE_FS;
401 insn->segmentOverride = SEG_OVERRIDE_GS;
404 debug("Unhandled override");
408 dbgprintf(insn, "Redundant Group 2 prefix");
409 prefixGroups[1] = TRUE;
410 setPrefixPresent(insn, byte, prefixLocation);
412 case 0x66: /* Operand-size override */
414 dbgprintf(insn, "Redundant Group 3 prefix");
415 prefixGroups[2] = TRUE;
417 setPrefixPresent(insn, byte, prefixLocation);
419 case 0x67: /* Address-size override */
421 dbgprintf(insn, "Redundant Group 4 prefix");
422 prefixGroups[3] = TRUE;
424 setPrefixPresent(insn, byte, prefixLocation);
426 default: /* Not a prefix byte */
432 dbgprintf(insn, "Found prefix 0x%hhx", byte);
435 insn->vectorExtensionType = TYPE_NO_VEX_XOP;
438 uint8_t byte1, byte2;
440 if (consumeByte(insn, &byte1)) {
441 dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
445 if (lookAtByte(insn, &byte2)) {
446 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
450 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
451 ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
452 insn->vectorExtensionType = TYPE_EVEX;
455 unconsumeByte(insn); /* unconsume byte1 */
456 unconsumeByte(insn); /* unconsume byte */
457 insn->necessaryPrefixLocation = insn->readerCursor - 2;
460 if (insn->vectorExtensionType == TYPE_EVEX) {
461 insn->vectorExtensionPrefix[0] = byte;
462 insn->vectorExtensionPrefix[1] = byte1;
463 if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
464 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
467 if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
468 dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
472 /* We simulate the REX prefix for simplicity's sake */
473 if (insn->mode == MODE_64BIT) {
474 insn->rexPrefix = 0x40
475 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
476 | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
477 | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
478 | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
481 dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
482 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
483 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
486 else if (byte == 0xc4) {
489 if (lookAtByte(insn, &byte1)) {
490 dbgprintf(insn, "Couldn't read second byte of VEX");
494 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
495 insn->vectorExtensionType = TYPE_VEX_3B;
496 insn->necessaryPrefixLocation = insn->readerCursor - 1;
500 insn->necessaryPrefixLocation = insn->readerCursor - 1;
503 if (insn->vectorExtensionType == TYPE_VEX_3B) {
504 insn->vectorExtensionPrefix[0] = byte;
505 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
506 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
508 /* We simulate the REX prefix for simplicity's sake */
510 if (insn->mode == MODE_64BIT) {
511 insn->rexPrefix = 0x40
512 | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
513 | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
514 | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
515 | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
518 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
519 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
520 insn->vectorExtensionPrefix[2]);
523 else if (byte == 0xc5) {
526 if (lookAtByte(insn, &byte1)) {
527 dbgprintf(insn, "Couldn't read second byte of VEX");
531 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
532 insn->vectorExtensionType = TYPE_VEX_2B;
538 if (insn->vectorExtensionType == TYPE_VEX_2B) {
539 insn->vectorExtensionPrefix[0] = byte;
540 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
542 if (insn->mode == MODE_64BIT) {
543 insn->rexPrefix = 0x40
544 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
547 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1]))
556 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
557 insn->vectorExtensionPrefix[0],
558 insn->vectorExtensionPrefix[1]);
561 else if (byte == 0x8f) {
564 if (lookAtByte(insn, &byte1)) {
565 dbgprintf(insn, "Couldn't read second byte of XOP");
569 if ((byte1 & 0x38) != 0x0) { /* 0 in these 3 bits is a POP instruction. */
570 insn->vectorExtensionType = TYPE_XOP;
571 insn->necessaryPrefixLocation = insn->readerCursor - 1;
575 insn->necessaryPrefixLocation = insn->readerCursor - 1;
578 if (insn->vectorExtensionType == TYPE_XOP) {
579 insn->vectorExtensionPrefix[0] = byte;
580 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
581 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
583 /* We simulate the REX prefix for simplicity's sake */
585 if (insn->mode == MODE_64BIT) {
586 insn->rexPrefix = 0x40
587 | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
588 | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
589 | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
590 | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
593 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2]))
602 dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
603 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
604 insn->vectorExtensionPrefix[2]);
608 if (insn->mode == MODE_64BIT) {
609 if ((byte & 0xf0) == 0x40) {
612 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
613 dbgprintf(insn, "Redundant REX prefix");
617 insn->rexPrefix = byte;
618 insn->necessaryPrefixLocation = insn->readerCursor - 2;
620 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
623 insn->necessaryPrefixLocation = insn->readerCursor - 1;
627 insn->necessaryPrefixLocation = insn->readerCursor - 1;
631 if (insn->mode == MODE_16BIT) {
632 insn->registerSize = (hasOpSize ? 4 : 2);
633 insn->addressSize = (hasAdSize ? 4 : 2);
634 insn->displacementSize = (hasAdSize ? 4 : 2);
635 insn->immediateSize = (hasOpSize ? 4 : 2);
636 } else if (insn->mode == MODE_32BIT) {
637 insn->registerSize = (hasOpSize ? 2 : 4);
638 insn->addressSize = (hasAdSize ? 2 : 4);
639 insn->displacementSize = (hasAdSize ? 2 : 4);
640 insn->immediateSize = (hasOpSize ? 2 : 4);
641 } else if (insn->mode == MODE_64BIT) {
642 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
643 insn->registerSize = 8;
644 insn->addressSize = (hasAdSize ? 4 : 8);
645 insn->displacementSize = 4;
646 insn->immediateSize = 4;
647 } else if (insn->rexPrefix) {
648 insn->registerSize = (hasOpSize ? 2 : 4);
649 insn->addressSize = (hasAdSize ? 4 : 8);
650 insn->displacementSize = (hasOpSize ? 2 : 4);
651 insn->immediateSize = (hasOpSize ? 2 : 4);
653 insn->registerSize = (hasOpSize ? 2 : 4);
654 insn->addressSize = (hasAdSize ? 4 : 8);
655 insn->displacementSize = (hasOpSize ? 2 : 4);
656 insn->immediateSize = (hasOpSize ? 2 : 4);
664 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
665 * extended or escape opcodes).
667 * @param insn - The instruction whose opcode is to be read.
668 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
670 static int readOpcode(struct InternalInstruction* insn) {
671 /* Determine the length of the primary opcode */
675 dbgprintf(insn, "readOpcode()");
677 insn->opcodeType = ONEBYTE;
679 if (insn->vectorExtensionType == TYPE_EVEX)
681 switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
683 dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
684 mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
687 insn->opcodeType = TWOBYTE;
688 return consumeByte(insn, &insn->opcode);
690 insn->opcodeType = THREEBYTE_38;
691 return consumeByte(insn, &insn->opcode);
693 insn->opcodeType = THREEBYTE_3A;
694 return consumeByte(insn, &insn->opcode);
697 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
698 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
700 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
701 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
704 insn->opcodeType = TWOBYTE;
705 return consumeByte(insn, &insn->opcode);
707 insn->opcodeType = THREEBYTE_38;
708 return consumeByte(insn, &insn->opcode);
710 insn->opcodeType = THREEBYTE_3A;
711 return consumeByte(insn, &insn->opcode);
714 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
715 insn->opcodeType = TWOBYTE;
716 return consumeByte(insn, &insn->opcode);
718 else if (insn->vectorExtensionType == TYPE_XOP) {
719 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
721 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
722 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
724 case XOP_MAP_SELECT_8:
725 insn->opcodeType = XOP8_MAP;
726 return consumeByte(insn, &insn->opcode);
727 case XOP_MAP_SELECT_9:
728 insn->opcodeType = XOP9_MAP;
729 return consumeByte(insn, &insn->opcode);
730 case XOP_MAP_SELECT_A:
731 insn->opcodeType = XOPA_MAP;
732 return consumeByte(insn, &insn->opcode);
736 if (consumeByte(insn, ¤t))
739 if (current == 0x0f) {
740 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
742 if (consumeByte(insn, ¤t))
745 if (current == 0x38) {
746 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
748 if (consumeByte(insn, ¤t))
751 insn->opcodeType = THREEBYTE_38;
752 } else if (current == 0x3a) {
753 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
755 if (consumeByte(insn, ¤t))
758 insn->opcodeType = THREEBYTE_3A;
760 dbgprintf(insn, "Didn't find a three-byte escape prefix");
762 insn->opcodeType = TWOBYTE;
767 * At this point we have consumed the full opcode.
768 * Anything we consume from here on must be unconsumed.
771 insn->opcode = current;
776 static int readModRM(struct InternalInstruction* insn);
779 * getIDWithAttrMask - Determines the ID of an instruction, consuming
780 * the ModR/M byte as appropriate for extended and escape opcodes,
781 * and using a supplied attribute mask.
783 * @param instructionID - A pointer whose target is filled in with the ID of the
785 * @param insn - The instruction whose ID is to be determined.
786 * @param attrMask - The attribute mask to search.
787 * @return - 0 if the ModR/M could be read when needed or was not
788 * needed; nonzero otherwise.
790 static int getIDWithAttrMask(uint16_t* instructionID,
791 struct InternalInstruction* insn,
793 BOOL hasModRMExtension;
795 uint16_t instructionClass;
797 instructionClass = contextForAttrs(attrMask);
799 hasModRMExtension = modRMRequired(insn->opcodeType,
803 if (hasModRMExtension) {
807 *instructionID = decode(insn->opcodeType,
812 *instructionID = decode(insn->opcodeType,
822 * is16BitEquivalent - Determines whether two instruction names refer to
823 * equivalent instructions but one is 16-bit whereas the other is not.
825 * @param orig - The instruction that is not 16-bit
826 * @param equiv - The instruction that is 16-bit
828 static BOOL is16BitEquivalent(const char* orig, const char* equiv) {
832 if (orig[i] == '\0' && equiv[i] == '\0')
834 if (orig[i] == '\0' || equiv[i] == '\0')
836 if (orig[i] != equiv[i]) {
837 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
839 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
841 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
849 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
850 * appropriate for extended and escape opcodes. Determines the attributes and
851 * context for the instruction before doing so.
853 * @param insn - The instruction whose ID is to be determined.
854 * @return - 0 if the ModR/M could be read when needed or was not needed;
857 static int getID(struct InternalInstruction* insn, const void *miiArg) {
859 uint16_t instructionID;
861 dbgprintf(insn, "getID()");
863 attrMask = ATTR_NONE;
865 if (insn->mode == MODE_64BIT)
866 attrMask |= ATTR_64BIT;
868 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
869 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
871 if (insn->vectorExtensionType == TYPE_EVEX) {
872 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
874 attrMask |= ATTR_OPSIZE;
884 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
885 attrMask |= ATTR_EVEXKZ;
886 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
887 attrMask |= ATTR_EVEXB;
888 if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
889 attrMask |= ATTR_EVEXK;
890 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
891 attrMask |= ATTR_EVEXL;
892 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
893 attrMask |= ATTR_EVEXL2;
895 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
896 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
898 attrMask |= ATTR_OPSIZE;
908 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
909 attrMask |= ATTR_VEXL;
911 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
912 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
914 attrMask |= ATTR_OPSIZE;
924 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
925 attrMask |= ATTR_VEXL;
927 else if (insn->vectorExtensionType == TYPE_XOP) {
928 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
930 attrMask |= ATTR_OPSIZE;
940 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
941 attrMask |= ATTR_VEXL;
948 if (insn->mode != MODE_16BIT && isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
949 attrMask |= ATTR_OPSIZE;
950 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
951 attrMask |= ATTR_ADSIZE;
952 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
954 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
958 if (insn->rexPrefix & 0x08)
959 attrMask |= ATTR_REXW;
961 if (getIDWithAttrMask(&instructionID, insn, attrMask))
965 * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
966 * of the AdSize prefix is inverted w.r.t. 32-bit mode.
968 if (insn->mode == MODE_16BIT && insn->opcode == 0xE3) {
969 const struct InstructionSpecifier *spec;
970 spec = specifierForUID(instructionID);
973 * Check for Ii8PCRel instructions. We could alternatively do a
974 * string-compare on the names, but this is probably cheaper.
976 if (x86OperandSets[spec->operands][0].type == TYPE_REL8) {
977 attrMask ^= ATTR_ADSIZE;
978 if (getIDWithAttrMask(&instructionID, insn, attrMask))
983 /* The following clauses compensate for limitations of the tables. */
985 if ((insn->mode == MODE_16BIT || insn->prefixPresent[0x66]) &&
986 !(attrMask & ATTR_OPSIZE)) {
988 * The instruction tables make no distinction between instructions that
989 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
990 * particular spot (i.e., many MMX operations). In general we're
991 * conservative, but in the specific case where OpSize is present but not
992 * in the right place we check if there's a 16-bit operation.
995 const struct InstructionSpecifier *spec;
996 uint16_t instructionIDWithOpsize;
997 const char *specName, *specWithOpSizeName;
999 spec = specifierForUID(instructionID);
1001 if (getIDWithAttrMask(&instructionIDWithOpsize,
1003 attrMask | ATTR_OPSIZE)) {
1005 * ModRM required with OpSize but not present; give up and return version
1006 * without OpSize set
1009 insn->instructionID = instructionID;
1014 specName = x86DisassemblerGetInstrName(instructionID, miiArg);
1015 specWithOpSizeName =
1016 x86DisassemblerGetInstrName(instructionIDWithOpsize, miiArg);
1018 if (is16BitEquivalent(specName, specWithOpSizeName) &&
1019 (insn->mode == MODE_16BIT) ^ insn->prefixPresent[0x66]) {
1020 insn->instructionID = instructionIDWithOpsize;
1021 insn->spec = specifierForUID(instructionIDWithOpsize);
1023 insn->instructionID = instructionID;
1029 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1030 insn->rexPrefix & 0x01) {
1032 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1033 * it should decode as XCHG %r8, %eax.
1036 const struct InstructionSpecifier *spec;
1037 uint16_t instructionIDWithNewOpcode;
1038 const struct InstructionSpecifier *specWithNewOpcode;
1040 spec = specifierForUID(instructionID);
1042 /* Borrow opcode from one of the other XCHGar opcodes */
1043 insn->opcode = 0x91;
1045 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1048 insn->opcode = 0x90;
1050 insn->instructionID = instructionID;
1055 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1058 insn->opcode = 0x90;
1060 insn->instructionID = instructionIDWithNewOpcode;
1061 insn->spec = specWithNewOpcode;
1066 insn->instructionID = instructionID;
1067 insn->spec = specifierForUID(insn->instructionID);
1073 * readSIB - Consumes the SIB byte to determine addressing information for an
1076 * @param insn - The instruction whose SIB byte is to be read.
1077 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
1079 static int readSIB(struct InternalInstruction* insn) {
1080 SIBIndex sibIndexBase = 0;
1081 SIBBase sibBaseBase = 0;
1082 uint8_t index, base;
1084 dbgprintf(insn, "readSIB()");
1086 if (insn->consumedSIB)
1089 insn->consumedSIB = TRUE;
1091 switch (insn->addressSize) {
1093 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1096 sibIndexBase = SIB_INDEX_EAX;
1097 sibBaseBase = SIB_BASE_EAX;
1100 sibIndexBase = SIB_INDEX_RAX;
1101 sibBaseBase = SIB_BASE_RAX;
1105 if (consumeByte(insn, &insn->sib))
1108 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1109 if (insn->vectorExtensionType == TYPE_EVEX)
1110 index |= v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4;
1114 insn->sibIndex = SIB_INDEX_NONE;
1117 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
1118 if (insn->sibIndex == SIB_INDEX_sib ||
1119 insn->sibIndex == SIB_INDEX_sib64)
1120 insn->sibIndex = SIB_INDEX_NONE;
1124 switch (scaleFromSIB(insn->sib)) {
1139 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1144 switch (modFromModRM(insn->modRM)) {
1146 insn->eaDisplacement = EA_DISP_32;
1147 insn->sibBase = SIB_BASE_NONE;
1150 insn->eaDisplacement = EA_DISP_8;
1151 insn->sibBase = (SIBBase)(sibBaseBase + base);
1154 insn->eaDisplacement = EA_DISP_32;
1155 insn->sibBase = (SIBBase)(sibBaseBase + base);
1158 debug("Cannot have Mod = 0b11 and a SIB byte");
1163 insn->sibBase = (SIBBase)(sibBaseBase + base);
1171 * readDisplacement - Consumes the displacement of an instruction.
1173 * @param insn - The instruction whose displacement is to be read.
1174 * @return - 0 if the displacement byte was successfully read; nonzero
1177 static int readDisplacement(struct InternalInstruction* insn) {
1182 dbgprintf(insn, "readDisplacement()");
1184 if (insn->consumedDisplacement)
1187 insn->consumedDisplacement = TRUE;
1188 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1190 switch (insn->eaDisplacement) {
1192 insn->consumedDisplacement = FALSE;
1195 if (consumeInt8(insn, &d8))
1197 insn->displacement = d8;
1200 if (consumeInt16(insn, &d16))
1202 insn->displacement = d16;
1205 if (consumeInt32(insn, &d32))
1207 insn->displacement = d32;
1211 insn->consumedDisplacement = TRUE;
1216 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1217 * displacement) for an instruction and interprets it.
1219 * @param insn - The instruction whose addressing information is to be read.
1220 * @return - 0 if the information was successfully read; nonzero otherwise.
1222 static int readModRM(struct InternalInstruction* insn) {
1223 uint8_t mod, rm, reg;
1225 dbgprintf(insn, "readModRM()");
1227 if (insn->consumedModRM)
1230 if (consumeByte(insn, &insn->modRM))
1232 insn->consumedModRM = TRUE;
1234 mod = modFromModRM(insn->modRM);
1235 rm = rmFromModRM(insn->modRM);
1236 reg = regFromModRM(insn->modRM);
1239 * This goes by insn->registerSize to pick the correct register, which messes
1240 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1243 switch (insn->registerSize) {
1245 insn->regBase = MODRM_REG_AX;
1246 insn->eaRegBase = EA_REG_AX;
1249 insn->regBase = MODRM_REG_EAX;
1250 insn->eaRegBase = EA_REG_EAX;
1253 insn->regBase = MODRM_REG_RAX;
1254 insn->eaRegBase = EA_REG_RAX;
1258 reg |= rFromREX(insn->rexPrefix) << 3;
1259 rm |= bFromREX(insn->rexPrefix) << 3;
1260 if (insn->vectorExtensionType == TYPE_EVEX) {
1261 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1262 rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1265 insn->reg = (Reg)(insn->regBase + reg);
1267 switch (insn->addressSize) {
1269 insn->eaBaseBase = EA_BASE_BX_SI;
1274 insn->eaBase = EA_BASE_NONE;
1275 insn->eaDisplacement = EA_DISP_16;
1276 if (readDisplacement(insn))
1279 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1280 insn->eaDisplacement = EA_DISP_NONE;
1284 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1285 insn->eaDisplacement = EA_DISP_8;
1286 insn->displacementSize = 1;
1287 if (readDisplacement(insn))
1291 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1292 insn->eaDisplacement = EA_DISP_16;
1293 if (readDisplacement(insn))
1297 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1298 if (readDisplacement(insn))
1305 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1309 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1313 case 0xc: /* in case REXW.b is set */
1314 insn->eaBase = (insn->addressSize == 4 ?
1315 EA_BASE_sib : EA_BASE_sib64);
1316 if (readSIB(insn) || readDisplacement(insn))
1320 insn->eaBase = EA_BASE_NONE;
1321 insn->eaDisplacement = EA_DISP_32;
1322 if (readDisplacement(insn))
1326 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1331 insn->displacementSize = 1;
1334 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1338 case 0xc: /* in case REXW.b is set */
1339 insn->eaBase = EA_BASE_sib;
1340 if (readSIB(insn) || readDisplacement(insn))
1344 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1345 if (readDisplacement(insn))
1351 insn->eaDisplacement = EA_DISP_NONE;
1352 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1356 } /* switch (insn->addressSize) */
1361 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1362 static uint8_t name(struct InternalInstruction *insn, \
1369 debug("Unhandled register type"); \
1373 return base + index; \
1375 if (insn->rexPrefix && \
1376 index >= 4 && index <= 7) { \
1377 return prefix##_SPL + (index - 4); \
1379 return prefix##_AL + index; \
1382 return prefix##_AX + index; \
1384 return prefix##_EAX + index; \
1386 return prefix##_RAX + index; \
1388 return prefix##_ZMM0 + index; \
1390 return prefix##_YMM0 + index; \
1395 return prefix##_XMM0 + index; \
1399 return prefix##_K0 + index; \
1405 return prefix##_MM0 + index; \
1406 case TYPE_SEGMENTREG: \
1409 return prefix##_ES + index; \
1410 case TYPE_DEBUGREG: \
1413 return prefix##_DR0 + index; \
1414 case TYPE_CONTROLREG: \
1417 return prefix##_CR0 + index; \
1422 * fixup*Value - Consults an operand type to determine the meaning of the
1423 * reg or R/M field. If the operand is an XMM operand, for example, an
1424 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1425 * misinterpret it as.
1427 * @param insn - The instruction containing the operand.
1428 * @param type - The operand type.
1429 * @param index - The existing value of the field as reported by readModRM().
1430 * @param valid - The address of a uint8_t. The target is set to 1 if the
1431 * field is valid for the register class; 0 if not.
1432 * @return - The proper value.
1434 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1435 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1438 * fixupReg - Consults an operand specifier to determine which of the
1439 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1441 * @param insn - See fixup*Value().
1442 * @param op - The operand specifier.
1443 * @return - 0 if fixup was successful; -1 if the register returned was
1444 * invalid for its class.
1446 static int fixupReg(struct InternalInstruction *insn,
1447 const struct OperandSpecifier *op) {
1450 dbgprintf(insn, "fixupReg()");
1452 switch ((OperandEncoding)op->encoding) {
1454 debug("Expected a REG or R/M encoding in fixupReg");
1457 insn->vvvv = (Reg)fixupRegValue(insn,
1458 (OperandType)op->type,
1465 insn->reg = (Reg)fixupRegValue(insn,
1466 (OperandType)op->type,
1467 insn->reg - insn->regBase,
1473 if (insn->eaBase >= insn->eaRegBase) {
1474 insn->eaBase = (EABase)fixupRMValue(insn,
1475 (OperandType)op->type,
1476 insn->eaBase - insn->eaRegBase,
1488 * readOpcodeRegister - Reads an operand from the opcode field of an
1489 * instruction and interprets it appropriately given the operand width.
1490 * Handles AddRegFrm instructions.
1492 * @param insn - the instruction whose opcode field is to be read.
1493 * @param size - The width (in bytes) of the register being specified.
1494 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1496 * @return - 0 on success; nonzero otherwise.
1498 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1499 dbgprintf(insn, "readOpcodeRegister()");
1502 size = insn->registerSize;
1506 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1507 | (insn->opcode & 7)));
1508 if (insn->rexPrefix &&
1509 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1510 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1511 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1512 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1517 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1518 + ((bFromREX(insn->rexPrefix) << 3)
1519 | (insn->opcode & 7)));
1522 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1523 + ((bFromREX(insn->rexPrefix) << 3)
1524 | (insn->opcode & 7)));
1527 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1528 + ((bFromREX(insn->rexPrefix) << 3)
1529 | (insn->opcode & 7)));
1537 * readImmediate - Consumes an immediate operand from an instruction, given the
1538 * desired operand size.
1540 * @param insn - The instruction whose operand is to be read.
1541 * @param size - The width (in bytes) of the operand.
1542 * @return - 0 if the immediate was successfully consumed; nonzero
1545 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1551 dbgprintf(insn, "readImmediate()");
1553 if (insn->numImmediatesConsumed == 2) {
1554 debug("Already consumed two immediates");
1559 size = insn->immediateSize;
1561 insn->immediateSize = size;
1562 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1566 if (consumeByte(insn, &imm8))
1568 insn->immediates[insn->numImmediatesConsumed] = imm8;
1571 if (consumeUInt16(insn, &imm16))
1573 insn->immediates[insn->numImmediatesConsumed] = imm16;
1576 if (consumeUInt32(insn, &imm32))
1578 insn->immediates[insn->numImmediatesConsumed] = imm32;
1581 if (consumeUInt64(insn, &imm64))
1583 insn->immediates[insn->numImmediatesConsumed] = imm64;
1587 insn->numImmediatesConsumed++;
1593 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1595 * @param insn - The instruction whose operand is to be read.
1596 * @return - 0 if the vvvv was successfully consumed; nonzero
1599 static int readVVVV(struct InternalInstruction* insn) {
1600 dbgprintf(insn, "readVVVV()");
1602 if (insn->vectorExtensionType == TYPE_EVEX)
1603 insn->vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
1604 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1605 insn->vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1606 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1607 insn->vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1608 else if (insn->vectorExtensionType == TYPE_XOP)
1609 insn->vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1613 if (insn->mode != MODE_64BIT)
1620 * readMaskRegister - Reads an mask register from the opcode field of an
1623 * @param insn - The instruction whose opcode field is to be read.
1624 * @return - 0 on success; nonzero otherwise.
1626 static int readMaskRegister(struct InternalInstruction* insn) {
1627 dbgprintf(insn, "readMaskRegister()");
1629 if (insn->vectorExtensionType != TYPE_EVEX)
1632 insn->writemask = aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]);
1637 * readOperands - Consults the specifier for an instruction and consumes all
1638 * operands for that instruction, interpreting them as it goes.
1640 * @param insn - The instruction whose operands are to be read and interpreted.
1641 * @return - 0 if all operands could be read; nonzero otherwise.
1643 static int readOperands(struct InternalInstruction* insn) {
1645 int hasVVVV, needVVVV;
1648 dbgprintf(insn, "readOperands()");
1650 /* If non-zero vvvv specified, need to make sure one of the operands
1652 hasVVVV = !readVVVV(insn);
1653 needVVVV = hasVVVV && (insn->vvvv != 0);
1655 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1656 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1663 if (readModRM(insn))
1665 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1674 dbgprintf(insn, "We currently don't hande code-offset encodings");
1678 /* Saw a register immediate so don't read again and instead split the
1679 previous immediate. FIXME: This is a hack. */
1680 insn->immediates[insn->numImmediatesConsumed] =
1681 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1682 ++insn->numImmediatesConsumed;
1685 if (readImmediate(insn, 1))
1687 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1688 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1690 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1691 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1693 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1694 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1698 if (readImmediate(insn, 2))
1702 if (readImmediate(insn, 4))
1706 if (readImmediate(insn, 8))
1710 if (readImmediate(insn, insn->immediateSize))
1714 if (readImmediate(insn, insn->addressSize))
1718 if (readOpcodeRegister(insn, 1))
1722 if (readOpcodeRegister(insn, 2))
1726 if (readOpcodeRegister(insn, 4))
1730 if (readOpcodeRegister(insn, 8))
1734 if (readOpcodeRegister(insn, 0))
1740 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1743 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1746 case ENCODING_WRITEMASK:
1747 if (readMaskRegister(insn))
1753 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1758 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1759 if (needVVVV) return -1;
1765 * decodeInstruction - Reads and interprets a full instruction provided by the
1768 * @param insn - A pointer to the instruction to be populated. Must be
1770 * @param reader - The function to be used to read the instruction's bytes.
1771 * @param readerArg - A generic argument to be passed to the reader to store
1772 * any internal state.
1773 * @param logger - If non-NULL, the function to be used to write log messages
1775 * @param loggerArg - A generic argument to be passed to the logger to store
1776 * any internal state.
1777 * @param startLoc - The address (in the reader's address space) of the first
1778 * byte in the instruction.
1779 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1780 * decode the instruction in.
1781 * @return - 0 if the instruction's memory could be read; nonzero if
1784 int decodeInstruction(struct InternalInstruction* insn,
1785 byteReader_t reader,
1786 const void* readerArg,
1791 DisassemblerMode mode) {
1792 memset(insn, 0, sizeof(struct InternalInstruction));
1794 insn->reader = reader;
1795 insn->readerArg = readerArg;
1796 insn->dlog = logger;
1797 insn->dlogArg = loggerArg;
1798 insn->startLocation = startLoc;
1799 insn->readerCursor = startLoc;
1801 insn->numImmediatesConsumed = 0;
1803 if (readPrefixes(insn) ||
1805 getID(insn, miiArg) ||
1806 insn->instructionID == 0 ||
1810 insn->operands = &x86OperandSets[insn->spec->operands][0];
1812 insn->length = insn->readerCursor - insn->startLocation;
1814 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1815 startLoc, insn->readerCursor, insn->length);
1817 if (insn->length > 15)
1818 dbgprintf(insn, "Instruction exceeds 15-byte limit");