1 //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
19 #include "X86Disassembler.h"
20 #include "X86DisassemblerDecoder.h"
21 #include "X86InstrInfo.h"
23 #include "llvm/MC/MCDisassembler.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/Target/TargetRegistry.h"
27 #include "llvm/Support/MemoryObject.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
31 using namespace llvm::X86Disassembler;
35 // Fill-ins to make the compiler happy. These constants are never actually
36 // assigned; they are just filler to make an automatically-generated switch
51 static void translateInstruction(MCInst &target,
52 InternalInstruction &source);
54 X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) :
59 X86GenericDisassembler::~X86GenericDisassembler() {
62 /// regionReader - a callback function that wraps the readByte method from
65 /// @param arg - The generic callback parameter. In this case, this should
66 /// be a pointer to a MemoryObject.
67 /// @param byte - A pointer to the byte to be read.
68 /// @param address - The address to be read.
69 static int regionReader(void* arg, uint8_t* byte, uint64_t address) {
70 MemoryObject* region = static_cast<MemoryObject*>(arg);
71 return region->readByte(address, byte);
74 /// logger - a callback function that wraps the operator<< method from
77 /// @param arg - The generic callback parameter. This should be a pointe
79 /// @param log - A string to be logged. logger() adds a newline.
80 static void logger(void* arg, const char* log) {
84 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
85 vStream << log << "\n";
89 // Public interface for the disassembler
92 bool X86GenericDisassembler::getInstruction(MCInst &instr,
94 const MemoryObject ®ion,
96 raw_ostream &vStream) const {
97 InternalInstruction internalInstr;
99 int ret = decodeInstruction(&internalInstr,
108 size = internalInstr.readerCursor - address;
112 size = internalInstr.length;
113 translateInstruction(instr, internalInstr);
119 // Private code that translates from struct InternalInstructions to MCInsts.
122 /// translateRegister - Translates an internal register to the appropriate LLVM
123 /// register, and appends it as an operand to an MCInst.
125 /// @param mcInst - The MCInst to append to.
126 /// @param reg - The Reg to append.
127 static void translateRegister(MCInst &mcInst, Reg reg) {
128 #define ENTRY(x) X86::x,
129 uint8_t llvmRegnums[] = {
135 uint8_t llvmRegnum = llvmRegnums[reg];
136 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
139 /// translateImmediate - Appends an immediate operand to an MCInst.
141 /// @param mcInst - The MCInst to append to.
142 /// @param immediate - The immediate value to append.
143 static void translateImmediate(MCInst &mcInst, uint64_t immediate) {
144 mcInst.addOperand(MCOperand::CreateImm(immediate));
147 /// translateRMRegister - Translates a register stored in the R/M field of the
148 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
149 /// @param mcInst - The MCInst to append to.
150 /// @param insn - The internal instruction to extract the R/M field
152 static void translateRMRegister(MCInst &mcInst,
153 InternalInstruction &insn) {
154 assert(insn.eaBase != EA_BASE_sib && insn.eaBase != EA_BASE_sib64 &&
155 "A R/M register operand may not have a SIB byte");
157 switch (insn.eaBase) {
159 llvm_unreachable("EA_BASE_NONE for ModR/M base");
161 #define ENTRY(x) case EA_BASE_##x:
164 llvm_unreachable("A R/M register operand may not have a base; "
165 "the operand must be a register.");
169 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
173 llvm_unreachable("Unexpected EA base register");
177 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
178 /// fields of an internal instruction (and possibly its SIB byte) to a memory
179 /// operand in LLVM's format, and appends it to an MCInst.
181 /// @param mcInst - The MCInst to append to.
182 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
184 static void translateRMMemory(MCInst &mcInst,
185 InternalInstruction &insn) {
186 // Addresses in an MCInst are represented as five operands:
187 // 1. basereg (register) The R/M base, or (if there is a SIB) the
189 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
191 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
192 // the index (which is multiplied by the
194 // 4. displacement (immediate) 0, or the displacement if there is one
195 // 5. segmentreg (register) x86_registerNONE for now, but could be set
196 // if we have segment overrides
199 MCOperand scaleAmount;
201 MCOperand displacement;
202 MCOperand segmentReg;
204 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
205 if (insn.sibBase != SIB_BASE_NONE) {
206 switch (insn.sibBase) {
208 llvm_unreachable("Unexpected sibBase");
211 baseReg = MCOperand::CreateReg(X86::x); break;
216 baseReg = MCOperand::CreateReg(0);
219 if (insn.sibIndex != SIB_INDEX_NONE) {
220 switch (insn.sibIndex) {
222 llvm_unreachable("Unexpected sibIndex");
224 case SIB_INDEX_##x: \
225 indexReg = MCOperand::CreateReg(X86::x); break;
231 indexReg = MCOperand::CreateReg(0);
234 scaleAmount = MCOperand::CreateImm(insn.sibScale);
236 switch (insn.eaBase) {
238 assert(insn.eaDisplacement != EA_DISP_NONE &&
239 "EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
241 if (insn.mode == MODE_64BIT)
242 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
244 baseReg = MCOperand::CreateReg(0);
246 indexReg = MCOperand::CreateReg(0);
249 baseReg = MCOperand::CreateReg(X86::BX);
250 indexReg = MCOperand::CreateReg(X86::SI);
253 baseReg = MCOperand::CreateReg(X86::BX);
254 indexReg = MCOperand::CreateReg(X86::DI);
257 baseReg = MCOperand::CreateReg(X86::BP);
258 indexReg = MCOperand::CreateReg(X86::SI);
261 baseReg = MCOperand::CreateReg(X86::BP);
262 indexReg = MCOperand::CreateReg(X86::DI);
265 indexReg = MCOperand::CreateReg(0);
266 switch (insn.eaBase) {
268 llvm_unreachable("Unexpected eaBase");
270 // Here, we will use the fill-ins defined above. However,
271 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
272 // sib and sib64 were handled in the top-level if, so they're only
273 // placeholders to keep the compiler happy.
276 baseReg = MCOperand::CreateReg(X86::x); break;
279 #define ENTRY(x) case EA_REG_##x:
282 llvm_unreachable("A R/M memory operand may not be a register; "
283 "the base field must be a base.");
289 displacement = MCOperand::CreateImm(insn.displacement);
291 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
292 0, // SEG_OVERRIDE_NONE
301 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
303 mcInst.addOperand(baseReg);
304 mcInst.addOperand(scaleAmount);
305 mcInst.addOperand(indexReg);
306 mcInst.addOperand(displacement);
307 mcInst.addOperand(segmentReg);
310 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
311 /// byte of an instruction to LLVM form, and appends it to an MCInst.
313 /// @param mcInst - The MCInst to append to.
314 /// @param operand - The operand, as stored in the descriptor table.
315 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
317 static void translateRM(MCInst &mcInst,
318 OperandSpecifier &operand,
319 InternalInstruction &insn) {
320 switch (operand.type) {
322 llvm_unreachable("Unexpected type for a R/M operand");
338 translateRMRegister(mcInst, insn);
357 translateRMMemory(mcInst, insn);
362 /// translateFPRegister - Translates a stack position on the FPU stack to its
363 /// LLVM form, and appends it to an MCInst.
365 /// @param mcInst - The MCInst to append to.
366 /// @param stackPos - The stack position to translate.
367 static void translateFPRegister(MCInst &mcInst,
369 assert(stackPos < 8 && "Invalid FP stack position");
371 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
374 /// translateOperand - Translates an operand stored in an internal instruction
375 /// to LLVM's format and appends it to an MCInst.
377 /// @param mcInst - The MCInst to append to.
378 /// @param operand - The operand, as stored in the descriptor table.
379 /// @param insn - The internal instruction.
380 static void translateOperand(MCInst &mcInst,
381 OperandSpecifier &operand,
382 InternalInstruction &insn) {
383 switch (operand.encoding) {
385 llvm_unreachable("Unhandled operand encoding during translation");
387 translateRegister(mcInst, insn.reg);
390 translateRM(mcInst, operand, insn);
398 llvm_unreachable("Translation of code offsets isn't supported.");
405 translateImmediate(mcInst,
406 insn.immediates[insn.numImmediatesTranslated++]);
412 translateRegister(mcInst, insn.opcodeRegister);
415 translateFPRegister(mcInst, insn.opcodeModifier);
418 translateRegister(mcInst, insn.opcodeRegister);
421 translateOperand(mcInst,
422 insn.spec->operands[operand.type - TYPE_DUP0],
428 /// translateInstruction - Translates an internal instruction and all its
429 /// operands to an MCInst.
431 /// @param mcInst - The MCInst to populate with the instruction's data.
432 /// @param insn - The internal instruction.
433 static void translateInstruction(MCInst &mcInst,
434 InternalInstruction &insn) {
437 mcInst.setOpcode(insn.instructionID);
441 insn.numImmediatesTranslated = 0;
443 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
444 if (insn.spec->operands[index].encoding != ENCODING_NONE)
445 translateOperand(mcInst, insn.spec->operands[index], insn);
449 static const MCDisassembler *createX86_32Disassembler(const Target &T) {
450 return new X86Disassembler::X86_32Disassembler;
453 static const MCDisassembler *createX86_64Disassembler(const Target &T) {
454 return new X86Disassembler::X86_64Disassembler;
457 extern "C" void LLVMInitializeX86Disassembler() {
458 // Register the disassembler.
459 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
460 createX86_32Disassembler);
461 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
462 createX86_64Disassembler);
467 extern "C" void LLVMInitializeX86Disassembler() {