1 //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
20 #include "llvm/MC/EDInstInfo.h"
21 #include "llvm/MC/MCDisassembler.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MemoryObject.h"
27 #include "llvm/Support/raw_ostream.h"
29 #include "X86GenRegisterNames.inc"
30 #include "X86GenEDInfo.inc"
33 using namespace llvm::X86Disassembler;
35 void x86DisassemblerDebug(const char *file,
38 dbgs() << file << ":" << line << ": " << s;
41 #define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
45 // Fill-ins to make the compiler happy. These constants are never actually
46 // assigned; they are just filler to make an automatically-generated switch
59 extern Target TheX86_32Target, TheX86_64Target;
63 static bool translateInstruction(MCInst &target,
64 InternalInstruction &source);
66 X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) :
71 X86GenericDisassembler::~X86GenericDisassembler() {
74 EDInstInfo *X86GenericDisassembler::getEDInfo() const {
78 /// regionReader - a callback function that wraps the readByte method from
81 /// @param arg - The generic callback parameter. In this case, this should
82 /// be a pointer to a MemoryObject.
83 /// @param byte - A pointer to the byte to be read.
84 /// @param address - The address to be read.
85 static int regionReader(void* arg, uint8_t* byte, uint64_t address) {
86 MemoryObject* region = static_cast<MemoryObject*>(arg);
87 return region->readByte(address, byte);
90 /// logger - a callback function that wraps the operator<< method from
93 /// @param arg - The generic callback parameter. This should be a pointe
95 /// @param log - A string to be logged. logger() adds a newline.
96 static void logger(void* arg, const char* log) {
100 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
101 vStream << log << "\n";
105 // Public interface for the disassembler
108 bool X86GenericDisassembler::getInstruction(MCInst &instr,
110 const MemoryObject ®ion,
112 raw_ostream &vStream) const {
113 InternalInstruction internalInstr;
115 int ret = decodeInstruction(&internalInstr,
124 size = internalInstr.readerCursor - address;
128 size = internalInstr.length;
129 return !translateInstruction(instr, internalInstr);
134 // Private code that translates from struct InternalInstructions to MCInsts.
137 /// translateRegister - Translates an internal register to the appropriate LLVM
138 /// register, and appends it as an operand to an MCInst.
140 /// @param mcInst - The MCInst to append to.
141 /// @param reg - The Reg to append.
142 static void translateRegister(MCInst &mcInst, Reg reg) {
143 #define ENTRY(x) X86::x,
144 uint8_t llvmRegnums[] = {
150 uint8_t llvmRegnum = llvmRegnums[reg];
151 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
154 /// translateImmediate - Appends an immediate operand to an MCInst.
156 /// @param mcInst - The MCInst to append to.
157 /// @param immediate - The immediate value to append.
158 /// @param operand - The operand, as stored in the descriptor table.
159 /// @param insn - The internal instruction.
160 static void translateImmediate(MCInst &mcInst,
162 OperandSpecifier &operand,
163 InternalInstruction &insn) {
164 // Sign-extend the immediate if necessary.
166 OperandType type = operand.type;
168 if (type == TYPE_RELv) {
169 switch (insn.displacementSize) {
191 immediate |= ~(0xffull);
194 if(immediate & 0x8000)
195 immediate |= ~(0xffffull);
200 if(immediate & 0x80000000)
201 immediate |= ~(0xffffffffull);
205 // operand is 64 bits wide. Do nothing.
209 mcInst.addOperand(MCOperand::CreateImm(immediate));
212 /// translateRMRegister - Translates a register stored in the R/M field of the
213 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
214 /// @param mcInst - The MCInst to append to.
215 /// @param insn - The internal instruction to extract the R/M field
217 /// @return - 0 on success; -1 otherwise
218 static bool translateRMRegister(MCInst &mcInst,
219 InternalInstruction &insn) {
220 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
221 debug("A R/M register operand may not have a SIB byte");
225 switch (insn.eaBase) {
227 debug("Unexpected EA base register");
230 debug("EA_BASE_NONE for ModR/M base");
232 #define ENTRY(x) case EA_BASE_##x:
235 debug("A R/M register operand may not have a base; "
236 "the operand must be a register.");
240 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
248 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
249 /// fields of an internal instruction (and possibly its SIB byte) to a memory
250 /// operand in LLVM's format, and appends it to an MCInst.
252 /// @param mcInst - The MCInst to append to.
253 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
255 /// @return - 0 on success; nonzero otherwise
256 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) {
257 // Addresses in an MCInst are represented as five operands:
258 // 1. basereg (register) The R/M base, or (if there is a SIB) the
260 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
262 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
263 // the index (which is multiplied by the
265 // 4. displacement (immediate) 0, or the displacement if there is one
266 // 5. segmentreg (register) x86_registerNONE for now, but could be set
267 // if we have segment overrides
270 MCOperand scaleAmount;
272 MCOperand displacement;
273 MCOperand segmentReg;
275 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
276 if (insn.sibBase != SIB_BASE_NONE) {
277 switch (insn.sibBase) {
279 debug("Unexpected sibBase");
283 baseReg = MCOperand::CreateReg(X86::x); break;
288 baseReg = MCOperand::CreateReg(0);
291 if (insn.sibIndex != SIB_INDEX_NONE) {
292 switch (insn.sibIndex) {
294 debug("Unexpected sibIndex");
297 case SIB_INDEX_##x: \
298 indexReg = MCOperand::CreateReg(X86::x); break;
304 indexReg = MCOperand::CreateReg(0);
307 scaleAmount = MCOperand::CreateImm(insn.sibScale);
309 switch (insn.eaBase) {
311 if (insn.eaDisplacement == EA_DISP_NONE) {
312 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
315 if (insn.mode == MODE_64BIT)
316 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
318 baseReg = MCOperand::CreateReg(0);
320 indexReg = MCOperand::CreateReg(0);
323 baseReg = MCOperand::CreateReg(X86::BX);
324 indexReg = MCOperand::CreateReg(X86::SI);
327 baseReg = MCOperand::CreateReg(X86::BX);
328 indexReg = MCOperand::CreateReg(X86::DI);
331 baseReg = MCOperand::CreateReg(X86::BP);
332 indexReg = MCOperand::CreateReg(X86::SI);
335 baseReg = MCOperand::CreateReg(X86::BP);
336 indexReg = MCOperand::CreateReg(X86::DI);
339 indexReg = MCOperand::CreateReg(0);
340 switch (insn.eaBase) {
342 debug("Unexpected eaBase");
344 // Here, we will use the fill-ins defined above. However,
345 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
346 // sib and sib64 were handled in the top-level if, so they're only
347 // placeholders to keep the compiler happy.
350 baseReg = MCOperand::CreateReg(X86::x); break;
353 #define ENTRY(x) case EA_REG_##x:
356 debug("A R/M memory operand may not be a register; "
357 "the base field must be a base.");
362 scaleAmount = MCOperand::CreateImm(1);
365 displacement = MCOperand::CreateImm(insn.displacement);
367 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
368 0, // SEG_OVERRIDE_NONE
377 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
379 mcInst.addOperand(baseReg);
380 mcInst.addOperand(scaleAmount);
381 mcInst.addOperand(indexReg);
382 mcInst.addOperand(displacement);
383 mcInst.addOperand(segmentReg);
387 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
388 /// byte of an instruction to LLVM form, and appends it to an MCInst.
390 /// @param mcInst - The MCInst to append to.
391 /// @param operand - The operand, as stored in the descriptor table.
392 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
394 /// @return - 0 on success; nonzero otherwise
395 static bool translateRM(MCInst &mcInst,
396 OperandSpecifier &operand,
397 InternalInstruction &insn) {
398 switch (operand.type) {
400 debug("Unexpected type for a R/M operand");
415 case TYPE_CONTROLREG:
416 return translateRMRegister(mcInst, insn);
435 return translateRMMemory(mcInst, insn);
439 /// translateFPRegister - Translates a stack position on the FPU stack to its
440 /// LLVM form, and appends it to an MCInst.
442 /// @param mcInst - The MCInst to append to.
443 /// @param stackPos - The stack position to translate.
444 /// @return - 0 on success; nonzero otherwise.
445 static bool translateFPRegister(MCInst &mcInst,
448 debug("Invalid FP stack position");
452 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
457 /// translateOperand - Translates an operand stored in an internal instruction
458 /// to LLVM's format and appends it to an MCInst.
460 /// @param mcInst - The MCInst to append to.
461 /// @param operand - The operand, as stored in the descriptor table.
462 /// @param insn - The internal instruction.
463 /// @return - false on success; true otherwise.
464 static bool translateOperand(MCInst &mcInst,
465 OperandSpecifier &operand,
466 InternalInstruction &insn) {
467 switch (operand.encoding) {
469 debug("Unhandled operand encoding during translation");
472 translateRegister(mcInst, insn.reg);
475 return translateRM(mcInst, operand, insn);
482 debug("Translation of code offsets isn't supported.");
490 translateImmediate(mcInst,
491 insn.immediates[insn.numImmediatesTranslated++],
499 translateRegister(mcInst, insn.opcodeRegister);
502 return translateFPRegister(mcInst, insn.opcodeModifier);
504 translateRegister(mcInst, insn.opcodeRegister);
507 return translateOperand(mcInst,
508 insn.spec->operands[operand.type - TYPE_DUP0],
513 /// translateInstruction - Translates an internal instruction and all its
514 /// operands to an MCInst.
516 /// @param mcInst - The MCInst to populate with the instruction's data.
517 /// @param insn - The internal instruction.
518 /// @return - false on success; true otherwise.
519 static bool translateInstruction(MCInst &mcInst,
520 InternalInstruction &insn) {
522 debug("Instruction has no specification");
526 mcInst.setOpcode(insn.instructionID);
530 insn.numImmediatesTranslated = 0;
532 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
533 if (insn.spec->operands[index].encoding != ENCODING_NONE) {
534 if (translateOperand(mcInst, insn.spec->operands[index], insn)) {
543 static MCDisassembler *createX86_32Disassembler(const Target &T) {
544 return new X86Disassembler::X86_32Disassembler;
547 static MCDisassembler *createX86_64Disassembler(const Target &T) {
548 return new X86Disassembler::X86_64Disassembler;
551 extern "C" void LLVMInitializeX86Disassembler() {
552 // Register the disassembler.
553 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
554 createX86_32Disassembler);
555 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
556 createX86_64Disassembler);