1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
30 using namespace llvm::X86Disassembler;
32 #define DEBUG_TYPE "x86-disassembler"
34 #define GET_REGINFO_ENUM
35 #include "X86GenRegisterInfo.inc"
36 #define GET_INSTRINFO_ENUM
37 #include "X86GenInstrInfo.inc"
38 #define GET_SUBTARGETINFO_ENUM
39 #include "X86GenSubtargetInfo.inc"
41 void llvm::X86Disassembler::Debug(const char *file, unsigned line,
43 dbgs() << file << ":" << line << ": " << s;
46 const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode,
48 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
49 return MII->getName(Opcode);
52 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s));
56 // Fill-ins to make the compiler happy. These constants are never actually
57 // assigned; they are just filler to make an automatically-generated switch
70 extern Target TheX86_32Target, TheX86_64Target;
74 static bool translateInstruction(MCInst &target,
75 InternalInstruction &source,
76 const MCDisassembler *Dis);
78 X86GenericDisassembler::X86GenericDisassembler(
79 const MCSubtargetInfo &STI,
81 std::unique_ptr<const MCInstrInfo> MII)
82 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
83 const FeatureBitset &FB = STI.getFeatureBits();
84 if (FB[X86::Mode16Bit]) {
87 } else if (FB[X86::Mode32Bit]) {
90 } else if (FB[X86::Mode64Bit]) {
95 llvm_unreachable("Invalid CPU mode");
99 ArrayRef<uint8_t> Bytes;
101 Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {}
104 /// A callback function that wraps the readByte method from Region.
106 /// @param Arg - The generic callback parameter. In this case, this should
107 /// be a pointer to a Region.
108 /// @param Byte - A pointer to the byte to be read.
109 /// @param Address - The address to be read.
110 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) {
111 auto *R = static_cast<const Region *>(Arg);
112 ArrayRef<uint8_t> Bytes = R->Bytes;
113 unsigned Index = Address - R->Base;
114 if (Bytes.size() <= Index)
116 *Byte = Bytes[Index];
120 /// logger - a callback function that wraps the operator<< method from
123 /// @param arg - The generic callback parameter. This should be a pointe
124 /// to a raw_ostream.
125 /// @param log - A string to be logged. logger() adds a newline.
126 static void logger(void* arg, const char* log) {
130 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
131 vStream << log << "\n";
135 // Public interface for the disassembler
138 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction(
139 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
140 raw_ostream &VStream, raw_ostream &CStream) const {
141 CommentStream = &CStream;
143 InternalInstruction InternalInstr;
145 dlog_t LoggerFn = logger;
146 if (&VStream == &nulls())
147 LoggerFn = nullptr; // Disable logging completely if it's going to nulls().
149 Region R(Bytes, Address);
151 int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R,
152 LoggerFn, (void *)&VStream,
153 (const void *)MII.get(), Address, fMode);
156 Size = InternalInstr.readerCursor - Address;
159 Size = InternalInstr.length;
160 return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail;
165 // Private code that translates from struct InternalInstructions to MCInsts.
168 /// translateRegister - Translates an internal register to the appropriate LLVM
169 /// register, and appends it as an operand to an MCInst.
171 /// @param mcInst - The MCInst to append to.
172 /// @param reg - The Reg to append.
173 static void translateRegister(MCInst &mcInst, Reg reg) {
174 #define ENTRY(x) X86::x,
175 uint8_t llvmRegnums[] = {
181 uint8_t llvmRegnum = llvmRegnums[reg];
182 mcInst.addOperand(MCOperand::createReg(llvmRegnum));
185 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
186 /// immediate Value in the MCInst.
188 /// @param Value - The immediate Value, has had any PC adjustment made by
190 /// @param isBranch - If the instruction is a branch instruction
191 /// @param Address - The starting address of the instruction
192 /// @param Offset - The byte offset to this immediate in the instruction
193 /// @param Width - The byte width of this immediate in the instruction
195 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
196 /// called then that function is called to get any symbolic information for the
197 /// immediate in the instruction using the Address, Offset and Width. If that
198 /// returns non-zero then the symbolic information it returns is used to create
199 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
200 /// returns zero and isBranch is true then a symbol look up for immediate Value
201 /// is done and if a symbol is found an MCExpr is created with that, else
202 /// an MCExpr with the immediate Value is created. This function returns true
203 /// if it adds an operand to the MCInst and false otherwise.
204 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
205 uint64_t Address, uint64_t Offset,
206 uint64_t Width, MCInst &MI,
207 const MCDisassembler *Dis) {
208 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
212 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
213 /// referenced by a load instruction with the base register that is the rip.
214 /// These can often be addresses in a literal pool. The Address of the
215 /// instruction and its immediate Value are used to determine the address
216 /// being referenced in the literal pool entry. The SymbolLookUp call back will
217 /// return a pointer to a literal 'C' string if the referenced address is an
218 /// address into a section with 'C' string literals.
219 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value,
220 const void *Decoder) {
221 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
222 Dis->tryAddingPcLoadReferenceComment(Value, Address);
225 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
226 0, // SEG_OVERRIDE_NONE
235 /// translateSrcIndex - Appends a source index operand to an MCInst.
237 /// @param mcInst - The MCInst to append to.
238 /// @param insn - The internal instruction.
239 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
242 if (insn.mode == MODE_64BIT)
243 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;
244 else if (insn.mode == MODE_32BIT)
245 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;
247 assert(insn.mode == MODE_16BIT);
248 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
250 MCOperand baseReg = MCOperand::createReg(baseRegNo);
251 mcInst.addOperand(baseReg);
253 MCOperand segmentReg;
254 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
255 mcInst.addOperand(segmentReg);
259 /// translateDstIndex - Appends a destination index operand to an MCInst.
261 /// @param mcInst - The MCInst to append to.
262 /// @param insn - The internal instruction.
264 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
267 if (insn.mode == MODE_64BIT)
268 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI;
269 else if (insn.mode == MODE_32BIT)
270 baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI;
272 assert(insn.mode == MODE_16BIT);
273 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
275 MCOperand baseReg = MCOperand::createReg(baseRegNo);
276 mcInst.addOperand(baseReg);
280 /// translateImmediate - Appends an immediate operand to an MCInst.
282 /// @param mcInst - The MCInst to append to.
283 /// @param immediate - The immediate value to append.
284 /// @param operand - The operand, as stored in the descriptor table.
285 /// @param insn - The internal instruction.
286 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
287 const OperandSpecifier &operand,
288 InternalInstruction &insn,
289 const MCDisassembler *Dis) {
290 // Sign-extend the immediate if necessary.
292 OperandType type = (OperandType)operand.type;
294 bool isBranch = false;
296 if (type == TYPE_RELv) {
298 pcrel = insn.startLocation +
299 insn.immediateOffset + insn.immediateSize;
300 switch (insn.displacementSize) {
305 immediate |= ~(0xffull);
308 if(immediate & 0x8000)
309 immediate |= ~(0xffffull);
312 if(immediate & 0x80000000)
313 immediate |= ~(0xffffffffull);
319 // By default sign-extend all X86 immediates based on their encoding.
320 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
321 type == TYPE_IMM64 || type == TYPE_IMMv) {
322 switch (operand.encoding) {
327 immediate |= ~(0xffull);
330 if(immediate & 0x8000)
331 immediate |= ~(0xffffull);
334 if(immediate & 0x80000000)
335 immediate |= ~(0xffffffffull);
340 } else if (type == TYPE_IMM3) {
341 // Check for immediates that printSSECC can't handle.
342 if (immediate >= 8) {
344 switch (mcInst.getOpcode()) {
345 default: llvm_unreachable("unexpected opcode");
346 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break;
347 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break;
348 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break;
349 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break;
350 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break;
351 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break;
352 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break;
353 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break;
354 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break;
355 case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break;
356 case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break;
357 case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break;
358 case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break;
359 case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break;
360 case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break;
361 case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break;
362 case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break;
363 case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break;
364 case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break;
365 case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break;
366 case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break;
367 case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break;
368 case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break;
369 case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break;
371 // Switch opcode to the one that doesn't get special printing.
372 mcInst.setOpcode(NewOpc);
374 } else if (type == TYPE_IMM5) {
375 // Check for immediates that printAVXCC can't handle.
376 if (immediate >= 32) {
378 switch (mcInst.getOpcode()) {
379 default: llvm_unreachable("unexpected opcode");
380 case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break;
381 case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break;
382 case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break;
383 case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break;
384 case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break;
385 case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break;
386 case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break;
387 case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break;
388 case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break;
389 case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break;
390 case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break;
391 case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break;
392 case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break;
393 case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break;
394 case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break;
395 case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break;
396 case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break;
397 case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break;
398 case X86::VCMPSDZrm: NewOpc = X86::VCMPSDZrmi_alt; break;
399 case X86::VCMPSDZrr: NewOpc = X86::VCMPSDZrri_alt; break;
400 case X86::VCMPSSZrm: NewOpc = X86::VCMPSSZrmi_alt; break;
401 case X86::VCMPSSZrr: NewOpc = X86::VCMPSSZrri_alt; break;
403 // Switch opcode to the one that doesn't get special printing.
404 mcInst.setOpcode(NewOpc);
406 } else if (type == TYPE_AVX512ICC) {
407 if (immediate >= 8 || ((immediate & 0x3) == 3)) {
409 switch (mcInst.getOpcode()) {
410 default: llvm_unreachable("unexpected opcode");
411 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break;
412 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break;
413 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break;
414 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break;
415 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break;
416 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break;
417 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break;
418 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break;
419 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break;
420 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break;
421 case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break;
422 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break;
423 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break;
424 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break;
425 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break;
426 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break;
427 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break;
428 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break;
429 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break;
430 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break;
431 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break;
432 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break;
433 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break;
434 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break;
435 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break;
436 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break;
437 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break;
438 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break;
439 case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break;
440 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break;
441 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break;
442 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break;
443 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break;
444 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break;
445 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break;
446 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break;
447 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break;
448 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break;
449 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break;
450 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break;
451 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break;
452 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break;
453 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break;
454 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break;
455 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break;
456 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break;
457 case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break;
458 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break;
459 case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break;
460 case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break;
461 case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break;
462 case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break;
463 case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break;
464 case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break;
465 case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break;
466 case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break;
467 case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break;
468 case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break;
469 case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break;
470 case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break;
471 case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break;
472 case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break;
473 case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break;
474 case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break;
475 case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break;
476 case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break;
477 case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break;
478 case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break;
479 case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break;
480 case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break;
481 case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break;
482 case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break;
483 case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break;
484 case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break;
485 case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break;
486 case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break;
487 case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break;
488 case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break;
489 case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break;
490 case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break;
491 case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break;
492 case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break;
493 case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break;
494 case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break;
495 case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break;
496 case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break;
497 case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break;
498 case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break;
499 case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break;
500 case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break;
501 case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break;
502 case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break;
503 case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break;
504 case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break;
505 case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break;
506 case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break;
507 case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break;
508 case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break;
509 case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break;
510 case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break;
511 case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break;
512 case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break;
513 case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break;
514 case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break;
515 case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break;
516 case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break;
517 case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break;
518 case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break;
519 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break;
520 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break;
521 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break;
522 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break;
523 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break;
524 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break;
525 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break;
526 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break;
527 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break;
528 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break;
529 case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break;
530 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break;
532 // Switch opcode to the one that doesn't get special printing.
533 mcInst.setOpcode(NewOpc);
541 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
544 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
547 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
550 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4)));
553 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
555 immediate |= ~(0xffull);
560 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
561 if(immediate & 0x80000000)
562 immediate |= ~(0xffffffffull);
565 // operand is 64 bits wide. Do nothing.
569 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
570 insn.immediateOffset, insn.immediateSize,
572 mcInst.addOperand(MCOperand::createImm(immediate));
574 if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
575 type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
576 MCOperand segmentReg;
577 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
578 mcInst.addOperand(segmentReg);
582 /// translateRMRegister - Translates a register stored in the R/M field of the
583 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
584 /// @param mcInst - The MCInst to append to.
585 /// @param insn - The internal instruction to extract the R/M field
587 /// @return - 0 on success; -1 otherwise
588 static bool translateRMRegister(MCInst &mcInst,
589 InternalInstruction &insn) {
590 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
591 debug("A R/M register operand may not have a SIB byte");
595 switch (insn.eaBase) {
597 debug("Unexpected EA base register");
600 debug("EA_BASE_NONE for ModR/M base");
602 #define ENTRY(x) case EA_BASE_##x:
605 debug("A R/M register operand may not have a base; "
606 "the operand must be a register.");
610 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
618 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
619 /// fields of an internal instruction (and possibly its SIB byte) to a memory
620 /// operand in LLVM's format, and appends it to an MCInst.
622 /// @param mcInst - The MCInst to append to.
623 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
625 /// @return - 0 on success; nonzero otherwise
626 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
627 const MCDisassembler *Dis) {
628 // Addresses in an MCInst are represented as five operands:
629 // 1. basereg (register) The R/M base, or (if there is a SIB) the
631 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
633 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
634 // the index (which is multiplied by the
636 // 4. displacement (immediate) 0, or the displacement if there is one
637 // 5. segmentreg (register) x86_registerNONE for now, but could be set
638 // if we have segment overrides
641 MCOperand scaleAmount;
643 MCOperand displacement;
644 MCOperand segmentReg;
647 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
648 if (insn.sibBase != SIB_BASE_NONE) {
649 switch (insn.sibBase) {
651 debug("Unexpected sibBase");
655 baseReg = MCOperand::createReg(X86::x); break;
660 baseReg = MCOperand::createReg(0);
663 // Check whether we are handling VSIB addressing mode for GATHER.
664 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and
665 // we should use SIB_INDEX_XMM4|YMM4 for VSIB.
666 // I don't see a way to get the correct IndexReg in readSIB:
667 // We can tell whether it is VSIB or SIB after instruction ID is decoded,
668 // but instruction ID may not be decoded yet when calling readSIB.
669 uint32_t Opcode = mcInst.getOpcode();
670 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
671 Opcode == X86::VGATHERDPDYrm ||
672 Opcode == X86::VGATHERQPDrm ||
673 Opcode == X86::VGATHERDPSrm ||
674 Opcode == X86::VGATHERQPSrm ||
675 Opcode == X86::VPGATHERDQrm ||
676 Opcode == X86::VPGATHERDQYrm ||
677 Opcode == X86::VPGATHERQQrm ||
678 Opcode == X86::VPGATHERDDrm ||
679 Opcode == X86::VPGATHERQDrm);
680 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
681 Opcode == X86::VGATHERDPSYrm ||
682 Opcode == X86::VGATHERQPSYrm ||
683 Opcode == X86::VGATHERDPDZrm ||
684 Opcode == X86::VPGATHERDQZrm ||
685 Opcode == X86::VPGATHERQQYrm ||
686 Opcode == X86::VPGATHERDDYrm ||
687 Opcode == X86::VPGATHERQDYrm);
688 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
689 Opcode == X86::VGATHERDPSZrm ||
690 Opcode == X86::VGATHERQPSZrm ||
691 Opcode == X86::VPGATHERQQZrm ||
692 Opcode == X86::VPGATHERDDZrm ||
693 Opcode == X86::VPGATHERQDZrm);
694 if (IndexIs128 || IndexIs256 || IndexIs512) {
695 unsigned IndexOffset = insn.sibIndex -
696 (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
697 SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
698 IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
699 insn.sibIndex = (SIBIndex)(IndexBase +
700 (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset));
703 if (insn.sibIndex != SIB_INDEX_NONE) {
704 switch (insn.sibIndex) {
706 debug("Unexpected sibIndex");
709 case SIB_INDEX_##x: \
710 indexReg = MCOperand::createReg(X86::x); break;
719 indexReg = MCOperand::createReg(0);
722 scaleAmount = MCOperand::createImm(insn.sibScale);
724 switch (insn.eaBase) {
726 if (insn.eaDisplacement == EA_DISP_NONE) {
727 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
730 if (insn.mode == MODE_64BIT){
731 pcrel = insn.startLocation +
732 insn.displacementOffset + insn.displacementSize;
733 tryAddingPcLoadReferenceComment(insn.startLocation +
734 insn.displacementOffset,
735 insn.displacement + pcrel, Dis);
736 baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6
739 baseReg = MCOperand::createReg(0);
741 indexReg = MCOperand::createReg(0);
744 baseReg = MCOperand::createReg(X86::BX);
745 indexReg = MCOperand::createReg(X86::SI);
748 baseReg = MCOperand::createReg(X86::BX);
749 indexReg = MCOperand::createReg(X86::DI);
752 baseReg = MCOperand::createReg(X86::BP);
753 indexReg = MCOperand::createReg(X86::SI);
756 baseReg = MCOperand::createReg(X86::BP);
757 indexReg = MCOperand::createReg(X86::DI);
760 indexReg = MCOperand::createReg(0);
761 switch (insn.eaBase) {
763 debug("Unexpected eaBase");
765 // Here, we will use the fill-ins defined above. However,
766 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
767 // sib and sib64 were handled in the top-level if, so they're only
768 // placeholders to keep the compiler happy.
771 baseReg = MCOperand::createReg(X86::x); break;
774 #define ENTRY(x) case EA_REG_##x:
777 debug("A R/M memory operand may not be a register; "
778 "the base field must be a base.");
783 scaleAmount = MCOperand::createImm(1);
786 displacement = MCOperand::createImm(insn.displacement);
788 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
790 mcInst.addOperand(baseReg);
791 mcInst.addOperand(scaleAmount);
792 mcInst.addOperand(indexReg);
793 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false,
794 insn.startLocation, insn.displacementOffset,
795 insn.displacementSize, mcInst, Dis))
796 mcInst.addOperand(displacement);
797 mcInst.addOperand(segmentReg);
801 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
802 /// byte of an instruction to LLVM form, and appends it to an MCInst.
804 /// @param mcInst - The MCInst to append to.
805 /// @param operand - The operand, as stored in the descriptor table.
806 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
808 /// @return - 0 on success; nonzero otherwise
809 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
810 InternalInstruction &insn, const MCDisassembler *Dis) {
811 switch (operand.type) {
813 debug("Unexpected type for a R/M operand");
831 case TYPE_CONTROLREG:
833 return translateRMRegister(mcInst, insn);
850 return translateRMMemory(mcInst, insn, Dis);
854 /// translateFPRegister - Translates a stack position on the FPU stack to its
855 /// LLVM form, and appends it to an MCInst.
857 /// @param mcInst - The MCInst to append to.
858 /// @param stackPos - The stack position to translate.
859 static void translateFPRegister(MCInst &mcInst,
861 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
864 /// translateMaskRegister - Translates a 3-bit mask register number to
865 /// LLVM form, and appends it to an MCInst.
867 /// @param mcInst - The MCInst to append to.
868 /// @param maskRegNum - Number of mask register from 0 to 7.
869 /// @return - false on success; true otherwise.
870 static bool translateMaskRegister(MCInst &mcInst,
871 uint8_t maskRegNum) {
872 if (maskRegNum >= 8) {
873 debug("Invalid mask register number");
877 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
881 /// translateOperand - Translates an operand stored in an internal instruction
882 /// to LLVM's format and appends it to an MCInst.
884 /// @param mcInst - The MCInst to append to.
885 /// @param operand - The operand, as stored in the descriptor table.
886 /// @param insn - The internal instruction.
887 /// @return - false on success; true otherwise.
888 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
889 InternalInstruction &insn,
890 const MCDisassembler *Dis) {
891 switch (operand.encoding) {
893 debug("Unhandled operand encoding during translation");
896 translateRegister(mcInst, insn.reg);
898 case ENCODING_WRITEMASK:
899 return translateMaskRegister(mcInst, insn.writemask);
901 return translateRM(mcInst, operand, insn, Dis);
908 debug("Translation of code offsets isn't supported.");
916 translateImmediate(mcInst,
917 insn.immediates[insn.numImmediatesTranslated++],
923 return translateSrcIndex(mcInst, insn);
925 return translateDstIndex(mcInst, insn);
931 translateRegister(mcInst, insn.opcodeRegister);
934 translateFPRegister(mcInst, insn.modRM & 7);
937 translateRegister(mcInst, insn.vvvv);
940 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
945 /// translateInstruction - Translates an internal instruction and all its
946 /// operands to an MCInst.
948 /// @param mcInst - The MCInst to populate with the instruction's data.
949 /// @param insn - The internal instruction.
950 /// @return - false on success; true otherwise.
951 static bool translateInstruction(MCInst &mcInst,
952 InternalInstruction &insn,
953 const MCDisassembler *Dis) {
955 debug("Instruction has no specification");
959 mcInst.setOpcode(insn.instructionID);
960 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
961 // prefix bytes should be disassembled as xrelease and xacquire then set the
962 // opcode to those instead of the rep and repne opcodes.
963 if (insn.xAcquireRelease) {
964 if(mcInst.getOpcode() == X86::REP_PREFIX)
965 mcInst.setOpcode(X86::XRELEASE_PREFIX);
966 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
967 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
970 insn.numImmediatesTranslated = 0;
972 for (const auto &Op : insn.operands) {
973 if (Op.encoding != ENCODING_NONE) {
974 if (translateOperand(mcInst, Op, insn, Dis)) {
983 static MCDisassembler *createX86Disassembler(const Target &T,
984 const MCSubtargetInfo &STI,
986 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
987 return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII));
990 extern "C" void LLVMInitializeX86Disassembler() {
991 // Register the disassembler.
992 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
993 createX86Disassembler);
994 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
995 createX86Disassembler);