1 //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
20 #include "llvm/MC/EDInstInfo.h"
21 #include "llvm/MC/MCDisassembler.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MemoryObject.h"
27 #include "llvm/Support/raw_ostream.h"
29 #include "X86GenRegisterNames.inc"
30 #include "X86GenEDInfo.inc"
33 using namespace llvm::X86Disassembler;
35 void x86DisassemblerDebug(const char *file,
38 dbgs() << file << ":" << line << ": " << s;
41 #define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
45 // Fill-ins to make the compiler happy. These constants are never actually
46 // assigned; they are just filler to make an automatically-generated switch
59 extern Target TheX86_32Target, TheX86_64Target;
63 static bool translateInstruction(MCInst &target,
64 InternalInstruction &source);
66 X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) :
71 X86GenericDisassembler::~X86GenericDisassembler() {
74 EDInstInfo *X86GenericDisassembler::getEDInfo() const {
78 /// regionReader - a callback function that wraps the readByte method from
81 /// @param arg - The generic callback parameter. In this case, this should
82 /// be a pointer to a MemoryObject.
83 /// @param byte - A pointer to the byte to be read.
84 /// @param address - The address to be read.
85 static int regionReader(void* arg, uint8_t* byte, uint64_t address) {
86 MemoryObject* region = static_cast<MemoryObject*>(arg);
87 return region->readByte(address, byte);
90 /// logger - a callback function that wraps the operator<< method from
93 /// @param arg - The generic callback parameter. This should be a pointe
95 /// @param log - A string to be logged. logger() adds a newline.
96 static void logger(void* arg, const char* log) {
100 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
101 vStream << log << "\n";
105 // Public interface for the disassembler
108 bool X86GenericDisassembler::getInstruction(MCInst &instr,
110 const MemoryObject ®ion,
112 raw_ostream &vStream) const {
113 InternalInstruction internalInstr;
115 int ret = decodeInstruction(&internalInstr,
124 size = internalInstr.readerCursor - address;
128 size = internalInstr.length;
129 return !translateInstruction(instr, internalInstr);
134 // Private code that translates from struct InternalInstructions to MCInsts.
137 /// translateRegister - Translates an internal register to the appropriate LLVM
138 /// register, and appends it as an operand to an MCInst.
140 /// @param mcInst - The MCInst to append to.
141 /// @param reg - The Reg to append.
142 static void translateRegister(MCInst &mcInst, Reg reg) {
143 #define ENTRY(x) X86::x,
144 uint8_t llvmRegnums[] = {
150 uint8_t llvmRegnum = llvmRegnums[reg];
151 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
154 /// translateImmediate - Appends an immediate operand to an MCInst.
156 /// @param mcInst - The MCInst to append to.
157 /// @param immediate - The immediate value to append.
158 static void translateImmediate(MCInst &mcInst, uint64_t immediate) {
159 mcInst.addOperand(MCOperand::CreateImm(immediate));
162 /// translateRMRegister - Translates a register stored in the R/M field of the
163 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
164 /// @param mcInst - The MCInst to append to.
165 /// @param insn - The internal instruction to extract the R/M field
167 /// @return - 0 on success; -1 otherwise
168 static bool translateRMRegister(MCInst &mcInst,
169 InternalInstruction &insn) {
170 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
171 debug("A R/M register operand may not have a SIB byte");
175 switch (insn.eaBase) {
177 debug("Unexpected EA base register");
180 debug("EA_BASE_NONE for ModR/M base");
182 #define ENTRY(x) case EA_BASE_##x:
185 debug("A R/M register operand may not have a base; "
186 "the operand must be a register.");
190 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
198 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
199 /// fields of an internal instruction (and possibly its SIB byte) to a memory
200 /// operand in LLVM's format, and appends it to an MCInst.
202 /// @param mcInst - The MCInst to append to.
203 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
205 /// @param sr - Whether or not to emit the segment register. The
206 /// LEA instruction does not expect a segment-register
208 /// @return - 0 on success; nonzero otherwise
209 static bool translateRMMemory(MCInst &mcInst,
210 InternalInstruction &insn,
212 // Addresses in an MCInst are represented as five operands:
213 // 1. basereg (register) The R/M base, or (if there is a SIB) the
215 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
217 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
218 // the index (which is multiplied by the
220 // 4. displacement (immediate) 0, or the displacement if there is one
221 // 5. segmentreg (register) x86_registerNONE for now, but could be set
222 // if we have segment overrides
225 MCOperand scaleAmount;
227 MCOperand displacement;
228 MCOperand segmentReg;
230 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
231 if (insn.sibBase != SIB_BASE_NONE) {
232 switch (insn.sibBase) {
234 debug("Unexpected sibBase");
238 baseReg = MCOperand::CreateReg(X86::x); break;
243 baseReg = MCOperand::CreateReg(0);
246 if (insn.sibIndex != SIB_INDEX_NONE) {
247 switch (insn.sibIndex) {
249 debug("Unexpected sibIndex");
252 case SIB_INDEX_##x: \
253 indexReg = MCOperand::CreateReg(X86::x); break;
259 indexReg = MCOperand::CreateReg(0);
262 scaleAmount = MCOperand::CreateImm(insn.sibScale);
264 switch (insn.eaBase) {
266 if (insn.eaDisplacement == EA_DISP_NONE) {
267 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
270 if (insn.mode == MODE_64BIT)
271 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
273 baseReg = MCOperand::CreateReg(0);
275 indexReg = MCOperand::CreateReg(0);
278 baseReg = MCOperand::CreateReg(X86::BX);
279 indexReg = MCOperand::CreateReg(X86::SI);
282 baseReg = MCOperand::CreateReg(X86::BX);
283 indexReg = MCOperand::CreateReg(X86::DI);
286 baseReg = MCOperand::CreateReg(X86::BP);
287 indexReg = MCOperand::CreateReg(X86::SI);
290 baseReg = MCOperand::CreateReg(X86::BP);
291 indexReg = MCOperand::CreateReg(X86::DI);
294 indexReg = MCOperand::CreateReg(0);
295 switch (insn.eaBase) {
297 debug("Unexpected eaBase");
299 // Here, we will use the fill-ins defined above. However,
300 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
301 // sib and sib64 were handled in the top-level if, so they're only
302 // placeholders to keep the compiler happy.
305 baseReg = MCOperand::CreateReg(X86::x); break;
308 #define ENTRY(x) case EA_REG_##x:
311 debug("A R/M memory operand may not be a register; "
312 "the base field must be a base.");
317 scaleAmount = MCOperand::CreateImm(1);
320 displacement = MCOperand::CreateImm(insn.displacement);
322 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
323 0, // SEG_OVERRIDE_NONE
332 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
334 mcInst.addOperand(baseReg);
335 mcInst.addOperand(scaleAmount);
336 mcInst.addOperand(indexReg);
337 mcInst.addOperand(displacement);
340 mcInst.addOperand(segmentReg);
345 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
346 /// byte of an instruction to LLVM form, and appends it to an MCInst.
348 /// @param mcInst - The MCInst to append to.
349 /// @param operand - The operand, as stored in the descriptor table.
350 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
352 /// @return - 0 on success; nonzero otherwise
353 static bool translateRM(MCInst &mcInst,
354 OperandSpecifier &operand,
355 InternalInstruction &insn) {
356 switch (operand.type) {
358 debug("Unexpected type for a R/M operand");
375 return translateRMRegister(mcInst, insn);
393 return translateRMMemory(mcInst, insn, true);
395 return translateRMMemory(mcInst, insn, false);
399 /// translateFPRegister - Translates a stack position on the FPU stack to its
400 /// LLVM form, and appends it to an MCInst.
402 /// @param mcInst - The MCInst to append to.
403 /// @param stackPos - The stack position to translate.
404 /// @return - 0 on success; nonzero otherwise.
405 static bool translateFPRegister(MCInst &mcInst,
408 debug("Invalid FP stack position");
412 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
417 /// translateOperand - Translates an operand stored in an internal instruction
418 /// to LLVM's format and appends it to an MCInst.
420 /// @param mcInst - The MCInst to append to.
421 /// @param operand - The operand, as stored in the descriptor table.
422 /// @param insn - The internal instruction.
423 /// @return - false on success; true otherwise.
424 static bool translateOperand(MCInst &mcInst,
425 OperandSpecifier &operand,
426 InternalInstruction &insn) {
427 switch (operand.encoding) {
429 debug("Unhandled operand encoding during translation");
432 translateRegister(mcInst, insn.reg);
435 return translateRM(mcInst, operand, insn);
442 debug("Translation of code offsets isn't supported.");
450 translateImmediate(mcInst,
451 insn.immediates[insn.numImmediatesTranslated++]);
457 translateRegister(mcInst, insn.opcodeRegister);
460 return translateFPRegister(mcInst, insn.opcodeModifier);
462 translateRegister(mcInst, insn.opcodeRegister);
465 return translateOperand(mcInst,
466 insn.spec->operands[operand.type - TYPE_DUP0],
471 /// translateInstruction - Translates an internal instruction and all its
472 /// operands to an MCInst.
474 /// @param mcInst - The MCInst to populate with the instruction's data.
475 /// @param insn - The internal instruction.
476 /// @return - false on success; true otherwise.
477 static bool translateInstruction(MCInst &mcInst,
478 InternalInstruction &insn) {
480 debug("Instruction has no specification");
484 mcInst.setOpcode(insn.instructionID);
488 insn.numImmediatesTranslated = 0;
490 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
491 if (insn.spec->operands[index].encoding != ENCODING_NONE) {
492 if (translateOperand(mcInst, insn.spec->operands[index], insn)) {
501 static MCDisassembler *createX86_32Disassembler(const Target &T) {
502 return new X86Disassembler::X86_32Disassembler;
505 static MCDisassembler *createX86_64Disassembler(const Target &T) {
506 return new X86Disassembler::X86_64Disassembler;
509 extern "C" void LLVMInitializeX86Disassembler() {
510 // Register the disassembler.
511 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
512 createX86_32Disassembler);
513 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
514 createX86_64Disassembler);