1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MemoryObject.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
30 #define GET_REGINFO_ENUM
31 #include "X86GenRegisterInfo.inc"
32 #define GET_INSTRINFO_ENUM
33 #include "X86GenInstrInfo.inc"
34 #define GET_SUBTARGETINFO_ENUM
35 #include "X86GenSubtargetInfo.inc"
38 using namespace llvm::X86Disassembler;
40 void llvm::X86Disassembler::Debug(const char *file, unsigned line,
42 dbgs() << file << ":" << line << ": " << s;
45 const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode,
47 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
48 return MII->getName(Opcode);
51 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s));
55 // Fill-ins to make the compiler happy. These constants are never actually
56 // assigned; they are just filler to make an automatically-generated switch
69 extern Target TheX86_32Target, TheX86_64Target;
73 static bool translateInstruction(MCInst &target,
74 InternalInstruction &source,
75 const MCDisassembler *Dis);
77 X86GenericDisassembler::X86GenericDisassembler(
78 const MCSubtargetInfo &STI,
80 std::unique_ptr<const MCInstrInfo> MII)
81 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
82 switch (STI.getFeatureBits() &
83 (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
94 llvm_unreachable("Invalid CPU mode");
98 /// regionReader - a callback function that wraps the readByte method from
101 /// @param arg - The generic callback parameter. In this case, this should
102 /// be a pointer to a MemoryObject.
103 /// @param byte - A pointer to the byte to be read.
104 /// @param address - The address to be read.
105 static int regionReader(const void* arg, uint8_t* byte, uint64_t address) {
106 const MemoryObject* region = static_cast<const MemoryObject*>(arg);
107 return region->readByte(address, byte);
110 /// logger - a callback function that wraps the operator<< method from
113 /// @param arg - The generic callback parameter. This should be a pointe
114 /// to a raw_ostream.
115 /// @param log - A string to be logged. logger() adds a newline.
116 static void logger(void* arg, const char* log) {
120 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
121 vStream << log << "\n";
125 // Public interface for the disassembler
128 MCDisassembler::DecodeStatus
129 X86GenericDisassembler::getInstruction(MCInst &instr,
131 const MemoryObject ®ion,
133 raw_ostream &vStream,
134 raw_ostream &cStream) const {
135 CommentStream = &cStream;
137 InternalInstruction internalInstr;
139 dlog_t loggerFn = logger;
140 if (&vStream == &nulls())
141 loggerFn = 0; // Disable logging completely if it's going to nulls().
143 int ret = decodeInstruction(&internalInstr,
145 (const void*)®ion,
148 (const void*)MII.get(),
153 size = internalInstr.readerCursor - address;
157 size = internalInstr.length;
158 return (!translateInstruction(instr, internalInstr, this)) ?
164 // Private code that translates from struct InternalInstructions to MCInsts.
167 /// translateRegister - Translates an internal register to the appropriate LLVM
168 /// register, and appends it as an operand to an MCInst.
170 /// @param mcInst - The MCInst to append to.
171 /// @param reg - The Reg to append.
172 static void translateRegister(MCInst &mcInst, Reg reg) {
173 #define ENTRY(x) X86::x,
174 uint8_t llvmRegnums[] = {
180 uint8_t llvmRegnum = llvmRegnums[reg];
181 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
184 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
185 /// immediate Value in the MCInst.
187 /// @param Value - The immediate Value, has had any PC adjustment made by
189 /// @param isBranch - If the instruction is a branch instruction
190 /// @param Address - The starting address of the instruction
191 /// @param Offset - The byte offset to this immediate in the instruction
192 /// @param Width - The byte width of this immediate in the instruction
194 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
195 /// called then that function is called to get any symbolic information for the
196 /// immediate in the instruction using the Address, Offset and Width. If that
197 /// returns non-zero then the symbolic information it returns is used to create
198 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
199 /// returns zero and isBranch is true then a symbol look up for immediate Value
200 /// is done and if a symbol is found an MCExpr is created with that, else
201 /// an MCExpr with the immediate Value is created. This function returns true
202 /// if it adds an operand to the MCInst and false otherwise.
203 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
204 uint64_t Address, uint64_t Offset,
205 uint64_t Width, MCInst &MI,
206 const MCDisassembler *Dis) {
207 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
211 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
212 /// referenced by a load instruction with the base register that is the rip.
213 /// These can often be addresses in a literal pool. The Address of the
214 /// instruction and its immediate Value are used to determine the address
215 /// being referenced in the literal pool entry. The SymbolLookUp call back will
216 /// return a pointer to a literal 'C' string if the referenced address is an
217 /// address into a section with 'C' string literals.
218 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value,
219 const void *Decoder) {
220 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
221 Dis->tryAddingPcLoadReferenceComment(Value, Address);
224 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
225 0, // SEG_OVERRIDE_NONE
234 /// translateSrcIndex - Appends a source index operand to an MCInst.
236 /// @param mcInst - The MCInst to append to.
237 /// @param insn - The internal instruction.
238 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
241 if (insn.mode == MODE_64BIT)
242 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;
243 else if (insn.mode == MODE_32BIT)
244 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;
246 assert(insn.mode == MODE_16BIT);
247 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
249 MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
250 mcInst.addOperand(baseReg);
252 MCOperand segmentReg;
253 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
254 mcInst.addOperand(segmentReg);
258 /// translateDstIndex - Appends a destination index operand to an MCInst.
260 /// @param mcInst - The MCInst to append to.
261 /// @param insn - The internal instruction.
263 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
266 if (insn.mode == MODE_64BIT)
267 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI;
268 else if (insn.mode == MODE_32BIT)
269 baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI;
271 assert(insn.mode == MODE_16BIT);
272 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
274 MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
275 mcInst.addOperand(baseReg);
279 /// translateImmediate - Appends an immediate operand to an MCInst.
281 /// @param mcInst - The MCInst to append to.
282 /// @param immediate - The immediate value to append.
283 /// @param operand - The operand, as stored in the descriptor table.
284 /// @param insn - The internal instruction.
285 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
286 const OperandSpecifier &operand,
287 InternalInstruction &insn,
288 const MCDisassembler *Dis) {
289 // Sign-extend the immediate if necessary.
291 OperandType type = (OperandType)operand.type;
293 bool isBranch = false;
295 if (type == TYPE_RELv) {
297 pcrel = insn.startLocation +
298 insn.immediateOffset + insn.immediateSize;
299 switch (insn.displacementSize) {
304 immediate |= ~(0xffull);
307 if(immediate & 0x8000)
308 immediate |= ~(0xffffull);
311 if(immediate & 0x80000000)
312 immediate |= ~(0xffffffffull);
318 // By default sign-extend all X86 immediates based on their encoding.
319 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
320 type == TYPE_IMM64) {
321 uint32_t Opcode = mcInst.getOpcode();
322 switch (operand.encoding) {
326 // Special case those X86 instructions that use the imm8 as a set of
327 // bits, bit count, etc. and are not sign-extend.
328 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
329 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
330 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
331 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
332 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
333 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
334 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
335 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
336 Opcode != X86::VINSERTPSrr)
338 immediate |= ~(0xffull);
341 if(immediate & 0x8000)
342 immediate |= ~(0xffffull);
345 if(immediate & 0x80000000)
346 immediate |= ~(0xffffffffull);
357 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
360 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
363 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
367 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
369 immediate |= ~(0xffull);
374 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
375 if(immediate & 0x80000000)
376 immediate |= ~(0xffffffffull);
379 // operand is 64 bits wide. Do nothing.
383 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
384 insn.immediateOffset, insn.immediateSize,
386 mcInst.addOperand(MCOperand::CreateImm(immediate));
388 if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
389 type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
390 MCOperand segmentReg;
391 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
392 mcInst.addOperand(segmentReg);
396 /// translateRMRegister - Translates a register stored in the R/M field of the
397 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
398 /// @param mcInst - The MCInst to append to.
399 /// @param insn - The internal instruction to extract the R/M field
401 /// @return - 0 on success; -1 otherwise
402 static bool translateRMRegister(MCInst &mcInst,
403 InternalInstruction &insn) {
404 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
405 debug("A R/M register operand may not have a SIB byte");
409 switch (insn.eaBase) {
411 debug("Unexpected EA base register");
414 debug("EA_BASE_NONE for ModR/M base");
416 #define ENTRY(x) case EA_BASE_##x:
419 debug("A R/M register operand may not have a base; "
420 "the operand must be a register.");
424 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
432 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
433 /// fields of an internal instruction (and possibly its SIB byte) to a memory
434 /// operand in LLVM's format, and appends it to an MCInst.
436 /// @param mcInst - The MCInst to append to.
437 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
439 /// @return - 0 on success; nonzero otherwise
440 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
441 const MCDisassembler *Dis) {
442 // Addresses in an MCInst are represented as five operands:
443 // 1. basereg (register) The R/M base, or (if there is a SIB) the
445 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
447 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
448 // the index (which is multiplied by the
450 // 4. displacement (immediate) 0, or the displacement if there is one
451 // 5. segmentreg (register) x86_registerNONE for now, but could be set
452 // if we have segment overrides
455 MCOperand scaleAmount;
457 MCOperand displacement;
458 MCOperand segmentReg;
461 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
462 if (insn.sibBase != SIB_BASE_NONE) {
463 switch (insn.sibBase) {
465 debug("Unexpected sibBase");
469 baseReg = MCOperand::CreateReg(X86::x); break;
474 baseReg = MCOperand::CreateReg(0);
477 // Check whether we are handling VSIB addressing mode for GATHER.
478 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and
479 // we should use SIB_INDEX_XMM4|YMM4 for VSIB.
480 // I don't see a way to get the correct IndexReg in readSIB:
481 // We can tell whether it is VSIB or SIB after instruction ID is decoded,
482 // but instruction ID may not be decoded yet when calling readSIB.
483 uint32_t Opcode = mcInst.getOpcode();
484 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
485 Opcode == X86::VGATHERDPDYrm ||
486 Opcode == X86::VGATHERQPDrm ||
487 Opcode == X86::VGATHERDPSrm ||
488 Opcode == X86::VGATHERQPSrm ||
489 Opcode == X86::VPGATHERDQrm ||
490 Opcode == X86::VPGATHERDQYrm ||
491 Opcode == X86::VPGATHERQQrm ||
492 Opcode == X86::VPGATHERDDrm ||
493 Opcode == X86::VPGATHERQDrm);
494 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
495 Opcode == X86::VGATHERDPSYrm ||
496 Opcode == X86::VGATHERQPSYrm ||
497 Opcode == X86::VGATHERDPDZrm ||
498 Opcode == X86::VPGATHERDQZrm ||
499 Opcode == X86::VPGATHERQQYrm ||
500 Opcode == X86::VPGATHERDDYrm ||
501 Opcode == X86::VPGATHERQDYrm);
502 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
503 Opcode == X86::VGATHERDPSZrm ||
504 Opcode == X86::VGATHERQPSZrm ||
505 Opcode == X86::VPGATHERQQZrm ||
506 Opcode == X86::VPGATHERDDZrm ||
507 Opcode == X86::VPGATHERQDZrm);
508 if (IndexIs128 || IndexIs256 || IndexIs512) {
509 unsigned IndexOffset = insn.sibIndex -
510 (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
511 SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
512 IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
513 insn.sibIndex = (SIBIndex)(IndexBase +
514 (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset));
517 if (insn.sibIndex != SIB_INDEX_NONE) {
518 switch (insn.sibIndex) {
520 debug("Unexpected sibIndex");
523 case SIB_INDEX_##x: \
524 indexReg = MCOperand::CreateReg(X86::x); break;
533 indexReg = MCOperand::CreateReg(0);
536 scaleAmount = MCOperand::CreateImm(insn.sibScale);
538 switch (insn.eaBase) {
540 if (insn.eaDisplacement == EA_DISP_NONE) {
541 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
544 if (insn.mode == MODE_64BIT){
545 pcrel = insn.startLocation +
546 insn.displacementOffset + insn.displacementSize;
547 tryAddingPcLoadReferenceComment(insn.startLocation +
548 insn.displacementOffset,
549 insn.displacement + pcrel, Dis);
550 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
553 baseReg = MCOperand::CreateReg(0);
555 indexReg = MCOperand::CreateReg(0);
558 baseReg = MCOperand::CreateReg(X86::BX);
559 indexReg = MCOperand::CreateReg(X86::SI);
562 baseReg = MCOperand::CreateReg(X86::BX);
563 indexReg = MCOperand::CreateReg(X86::DI);
566 baseReg = MCOperand::CreateReg(X86::BP);
567 indexReg = MCOperand::CreateReg(X86::SI);
570 baseReg = MCOperand::CreateReg(X86::BP);
571 indexReg = MCOperand::CreateReg(X86::DI);
574 indexReg = MCOperand::CreateReg(0);
575 switch (insn.eaBase) {
577 debug("Unexpected eaBase");
579 // Here, we will use the fill-ins defined above. However,
580 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
581 // sib and sib64 were handled in the top-level if, so they're only
582 // placeholders to keep the compiler happy.
585 baseReg = MCOperand::CreateReg(X86::x); break;
588 #define ENTRY(x) case EA_REG_##x:
591 debug("A R/M memory operand may not be a register; "
592 "the base field must be a base.");
597 scaleAmount = MCOperand::CreateImm(1);
600 displacement = MCOperand::CreateImm(insn.displacement);
602 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
604 mcInst.addOperand(baseReg);
605 mcInst.addOperand(scaleAmount);
606 mcInst.addOperand(indexReg);
607 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false,
608 insn.startLocation, insn.displacementOffset,
609 insn.displacementSize, mcInst, Dis))
610 mcInst.addOperand(displacement);
611 mcInst.addOperand(segmentReg);
615 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
616 /// byte of an instruction to LLVM form, and appends it to an MCInst.
618 /// @param mcInst - The MCInst to append to.
619 /// @param operand - The operand, as stored in the descriptor table.
620 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
622 /// @return - 0 on success; nonzero otherwise
623 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
624 InternalInstruction &insn, const MCDisassembler *Dis) {
625 switch (operand.type) {
627 debug("Unexpected type for a R/M operand");
647 case TYPE_CONTROLREG:
648 return translateRMRegister(mcInst, insn);
668 return translateRMMemory(mcInst, insn, Dis);
672 /// translateFPRegister - Translates a stack position on the FPU stack to its
673 /// LLVM form, and appends it to an MCInst.
675 /// @param mcInst - The MCInst to append to.
676 /// @param stackPos - The stack position to translate.
677 static void translateFPRegister(MCInst &mcInst,
679 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
682 /// translateMaskRegister - Translates a 3-bit mask register number to
683 /// LLVM form, and appends it to an MCInst.
685 /// @param mcInst - The MCInst to append to.
686 /// @param maskRegNum - Number of mask register from 0 to 7.
687 /// @return - false on success; true otherwise.
688 static bool translateMaskRegister(MCInst &mcInst,
689 uint8_t maskRegNum) {
690 if (maskRegNum >= 8) {
691 debug("Invalid mask register number");
695 mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));
699 /// translateOperand - Translates an operand stored in an internal instruction
700 /// to LLVM's format and appends it to an MCInst.
702 /// @param mcInst - The MCInst to append to.
703 /// @param operand - The operand, as stored in the descriptor table.
704 /// @param insn - The internal instruction.
705 /// @return - false on success; true otherwise.
706 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
707 InternalInstruction &insn,
708 const MCDisassembler *Dis) {
709 switch (operand.encoding) {
711 debug("Unhandled operand encoding during translation");
714 translateRegister(mcInst, insn.reg);
716 case ENCODING_WRITEMASK:
717 return translateMaskRegister(mcInst, insn.writemask);
719 return translateRM(mcInst, operand, insn, Dis);
726 debug("Translation of code offsets isn't supported.");
734 translateImmediate(mcInst,
735 insn.immediates[insn.numImmediatesTranslated++],
741 return translateSrcIndex(mcInst, insn);
743 return translateDstIndex(mcInst, insn);
749 translateRegister(mcInst, insn.opcodeRegister);
752 translateFPRegister(mcInst, insn.modRM & 7);
755 translateRegister(mcInst, insn.vvvv);
758 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
763 /// translateInstruction - Translates an internal instruction and all its
764 /// operands to an MCInst.
766 /// @param mcInst - The MCInst to populate with the instruction's data.
767 /// @param insn - The internal instruction.
768 /// @return - false on success; true otherwise.
769 static bool translateInstruction(MCInst &mcInst,
770 InternalInstruction &insn,
771 const MCDisassembler *Dis) {
773 debug("Instruction has no specification");
777 mcInst.setOpcode(insn.instructionID);
778 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
779 // prefix bytes should be disassembled as xrelease and xacquire then set the
780 // opcode to those instead of the rep and repne opcodes.
781 if (insn.xAcquireRelease) {
782 if(mcInst.getOpcode() == X86::REP_PREFIX)
783 mcInst.setOpcode(X86::XRELEASE_PREFIX);
784 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
785 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
790 insn.numImmediatesTranslated = 0;
792 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
793 if (insn.operands[index].encoding != ENCODING_NONE) {
794 if (translateOperand(mcInst, insn.operands[index], insn, Dis)) {
803 static MCDisassembler *createX86Disassembler(const Target &T,
804 const MCSubtargetInfo &STI,
806 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
807 return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII));
810 extern "C" void LLVMInitializeX86Disassembler() {
811 // Register the disassembler.
812 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
813 createX86Disassembler);
814 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
815 createX86Disassembler);