1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
13 //===----------------------------------------------------------------------===//
15 #include "X86InstComments.h"
16 #include "X86GenInstrNames.inc"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Support/raw_ostream.h"
21 //===----------------------------------------------------------------------===//
22 // Vector Mask Decoding
23 //===----------------------------------------------------------------------===//
29 static void DecodeINSERTPSMask(unsigned Imm,
30 SmallVectorImpl<unsigned> &ShuffleMask) {
31 // Defaults the copying the dest value.
32 ShuffleMask.push_back(0);
33 ShuffleMask.push_back(1);
34 ShuffleMask.push_back(2);
35 ShuffleMask.push_back(3);
37 // Decode the immediate.
38 unsigned ZMask = Imm & 15;
39 unsigned CountD = (Imm >> 4) & 3;
40 unsigned CountS = (Imm >> 6) & 3;
42 // CountS selects which input element to use.
43 unsigned InVal = 4+CountS;
44 // CountD specifies which element of destination to update.
45 ShuffleMask[CountD] = InVal;
46 // ZMask zaps values, potentially overriding the CountD elt.
47 if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero;
48 if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero;
49 if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero;
50 if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero;
53 static void DecodeSHUFPSMask(unsigned NElts, unsigned Imm,
54 SmallVectorImpl<unsigned> &ShuffleMask) {
55 // Part that reads from dest.
56 for (unsigned i = 0; i != NElts/2; ++i) {
57 ShuffleMask.push_back(Imm % NElts);
60 // Part that reads from src.
61 for (unsigned i = 0; i != NElts/2; ++i) {
62 ShuffleMask.push_back(Imm % NElts + NElts);
67 static void DecodePSHUFMask(unsigned NElts, unsigned Imm,
68 SmallVectorImpl<unsigned> &ShuffleMask) {
69 for (unsigned i = 0; i != NElts; ++i) {
70 ShuffleMask.push_back(Imm % NElts);
75 /// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd
76 /// etc. NElts indicates the number of elements in the vector allowing it to
77 /// handle different datatypes and vector widths.
78 static void DecodeUNPCKLPMask(unsigned NElts,
79 SmallVectorImpl<unsigned> &ShuffleMask) {
80 for (unsigned i = 0; i != NElts/2; ++i) {
81 ShuffleMask.push_back(i); // Reads from dest
82 ShuffleMask.push_back(i+NElts); // Reads from src
86 //===----------------------------------------------------------------------===//
87 // Top Level Entrypoint
88 //===----------------------------------------------------------------------===//
91 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
92 /// newline terminated strings to the specified string if desired. This
93 /// information is shown in disassembly dumps when verbose assembly is enabled.
94 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
95 const char *(*getRegName)(unsigned)) {
96 // If this is a shuffle operation, the switch should fill in this state.
97 SmallVector<unsigned, 8> ShuffleMask;
98 const char *DestName = 0, *Src1Name = 0, *Src2Name = 0;
100 switch (MI->getOpcode()) {
101 case X86::INSERTPSrr:
102 Src1Name = getRegName(MI->getOperand(1).getReg());
103 Src2Name = getRegName(MI->getOperand(2).getReg());
104 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
107 Src1Name = getRegName(MI->getOperand(1).getReg());
110 DestName = getRegName(MI->getOperand(0).getReg());
111 DecodePSHUFMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(),
116 DecodeSHUFPSMask(2, MI->getOperand(3).getImm(), ShuffleMask);
117 Src1Name = getRegName(MI->getOperand(0).getReg());
118 Src2Name = getRegName(MI->getOperand(2).getReg());
121 DecodeSHUFPSMask(4, MI->getOperand(3).getImm(), ShuffleMask);
122 Src1Name = getRegName(MI->getOperand(0).getReg());
123 Src2Name = getRegName(MI->getOperand(2).getReg());
125 case X86::UNPCKLPSrr:
126 Src2Name = getRegName(MI->getOperand(2).getReg());
128 case X86::UNPCKLPSrm:
129 DecodeUNPCKLPMask(4, ShuffleMask);
130 Src1Name = getRegName(MI->getOperand(0).getReg());
135 // If this was a shuffle operation, print the shuffle mask.
136 if (!ShuffleMask.empty()) {
137 if (DestName == 0) DestName = Src1Name;
138 OS << (DestName ? DestName : "mem") << " = ";
140 // If the two sources are the same, canonicalize the input elements to be
141 // from the first src so that we get larger element spans.
142 if (Src1Name == Src2Name) {
143 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
144 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
145 ShuffleMask[i] >= e) // From second mask.
150 // The shuffle mask specifies which elements of the src1/src2 fill in the
151 // destination, with a few sentinel values. Loop through and print them
153 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
156 if (ShuffleMask[i] == SM_SentinelZero) {
161 // Otherwise, it must come from src1 or src2. Print the span of elements
162 // that comes from this src.
163 bool isSrc1 = ShuffleMask[i] < ShuffleMask.size();
164 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
165 OS << (SrcName ? SrcName : "mem") << '[';
168 (int)ShuffleMask[i] >= 0 &&
169 (ShuffleMask[i] < ShuffleMask.size()) == isSrc1) {
174 OS << ShuffleMask[i] % ShuffleMask.size();
178 --i; // For loop increments element #.