1 //===-- X86Operand.h - Parsed X86 machine instruction --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
11 #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
13 #include "X86AsmParserCommon.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/ADT/STLExtras.h"
20 /// X86Operand - Instances of this class represent a parsed X86 machine
22 struct X86Operand : public MCParsedAsmOperand {
30 SMLoc StartLoc, EndLoc;
66 X86Operand(KindTy K, SMLoc Start, SMLoc End)
67 : Kind(K), StartLoc(Start), EndLoc(End) {}
69 StringRef getSymName() override { return SymName; }
70 void *getOpDecl() override { return OpDecl; }
72 /// getStartLoc - Get the location of the first token of this operand.
73 SMLoc getStartLoc() const override { return StartLoc; }
74 /// getEndLoc - Get the location of the last token of this operand.
75 SMLoc getEndLoc() const override { return EndLoc; }
76 /// getLocRange - Get the range between the first and last token of this
78 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
79 /// getOffsetOfLoc - Get the location of the offset operator.
80 SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
82 void print(raw_ostream &OS) const override {}
84 StringRef getToken() const {
85 assert(Kind == Token && "Invalid access!");
86 return StringRef(Tok.Data, Tok.Length);
88 void setTokenValue(StringRef Value) {
89 assert(Kind == Token && "Invalid access!");
90 Tok.Data = Value.data();
91 Tok.Length = Value.size();
94 unsigned getReg() const override {
95 assert(Kind == Register && "Invalid access!");
99 const MCExpr *getImm() const {
100 assert(Kind == Immediate && "Invalid access!");
104 const MCExpr *getMemDisp() const {
105 assert(Kind == Memory && "Invalid access!");
108 unsigned getMemSegReg() const {
109 assert(Kind == Memory && "Invalid access!");
112 unsigned getMemBaseReg() const {
113 assert(Kind == Memory && "Invalid access!");
116 unsigned getMemIndexReg() const {
117 assert(Kind == Memory && "Invalid access!");
120 unsigned getMemScale() const {
121 assert(Kind == Memory && "Invalid access!");
124 unsigned getMemModeSize() const {
125 assert(Kind == Memory && "Invalid access!");
129 bool isToken() const override {return Kind == Token; }
131 bool isImm() const override { return Kind == Immediate; }
133 bool isImmSExti16i8() const {
137 // If this isn't a constant expr, just assume it fits and let relaxation
139 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
143 // Otherwise, check the value is in a range that makes sense for this
145 return isImmSExti16i8Value(CE->getValue());
147 bool isImmSExti32i8() const {
151 // If this isn't a constant expr, just assume it fits and let relaxation
153 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
157 // Otherwise, check the value is in a range that makes sense for this
159 return isImmSExti32i8Value(CE->getValue());
161 bool isImmSExti64i8() const {
165 // If this isn't a constant expr, just assume it fits and let relaxation
167 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
171 // Otherwise, check the value is in a range that makes sense for this
173 return isImmSExti64i8Value(CE->getValue());
175 bool isImmSExti64i32() const {
179 // If this isn't a constant expr, just assume it fits and let relaxation
181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
185 // Otherwise, check the value is in a range that makes sense for this
187 return isImmSExti64i32Value(CE->getValue());
190 bool isImmUnsignedi8() const {
191 if (!isImm()) return false;
192 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
193 if (!CE) return false;
194 return isImmUnsignedi8Value(CE->getValue());
197 bool isOffsetOf() const override {
198 return OffsetOfLoc.getPointer();
201 bool needAddressOf() const override {
205 bool isMem() const override { return Kind == Memory; }
206 bool isMemUnsized() const {
207 return Kind == Memory && Mem.Size == 0;
209 bool isMem8() const {
210 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
212 bool isMem16() const {
213 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
215 bool isMem32() const {
216 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
218 bool isMem64() const {
219 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
221 bool isMem80() const {
222 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
224 bool isMem128() const {
225 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
227 bool isMem256() const {
228 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
230 bool isMem512() const {
231 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
234 bool isMemVX32() const {
235 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
236 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
238 bool isMemVY32() const {
239 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
240 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
242 bool isMemVX64() const {
243 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
244 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
246 bool isMemVY64() const {
247 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
248 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
250 bool isMemVZ32() const {
251 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
252 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
254 bool isMemVZ64() const {
255 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
256 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
259 bool isAbsMem() const {
260 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
261 !getMemIndexReg() && getMemScale() == 1;
263 bool isAVX512RC() const{
267 bool isAbsMem16() const {
268 return isAbsMem() && Mem.ModeSize == 16;
271 bool isSrcIdx() const {
272 return !getMemIndexReg() && getMemScale() == 1 &&
273 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
274 getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
275 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
277 bool isSrcIdx8() const {
278 return isMem8() && isSrcIdx();
280 bool isSrcIdx16() const {
281 return isMem16() && isSrcIdx();
283 bool isSrcIdx32() const {
284 return isMem32() && isSrcIdx();
286 bool isSrcIdx64() const {
287 return isMem64() && isSrcIdx();
290 bool isDstIdx() const {
291 return !getMemIndexReg() && getMemScale() == 1 &&
292 (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
293 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
294 getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
295 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
297 bool isDstIdx8() const {
298 return isMem8() && isDstIdx();
300 bool isDstIdx16() const {
301 return isMem16() && isDstIdx();
303 bool isDstIdx32() const {
304 return isMem32() && isDstIdx();
306 bool isDstIdx64() const {
307 return isMem64() && isDstIdx();
310 bool isMemOffs() const {
311 return Kind == Memory && !getMemBaseReg() && !getMemIndexReg() &&
315 bool isMemOffs16_8() const {
316 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 8);
318 bool isMemOffs16_16() const {
319 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 16);
321 bool isMemOffs16_32() const {
322 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 32);
324 bool isMemOffs32_8() const {
325 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 8);
327 bool isMemOffs32_16() const {
328 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 16);
330 bool isMemOffs32_32() const {
331 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 32);
333 bool isMemOffs32_64() const {
334 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 64);
336 bool isMemOffs64_8() const {
337 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 8);
339 bool isMemOffs64_16() const {
340 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 16);
342 bool isMemOffs64_32() const {
343 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 32);
345 bool isMemOffs64_64() const {
346 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 64);
349 bool isReg() const override { return Kind == Register; }
351 bool isGR32orGR64() const {
352 return Kind == Register &&
353 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
354 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
357 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
358 // Add as immediates when possible.
359 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
360 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
362 Inst.addOperand(MCOperand::CreateExpr(Expr));
365 void addRegOperands(MCInst &Inst, unsigned N) const {
366 assert(N == 1 && "Invalid number of operands!");
367 Inst.addOperand(MCOperand::CreateReg(getReg()));
370 static unsigned getGR32FromGR64(unsigned RegNo) {
372 default: llvm_unreachable("Unexpected register");
373 case X86::RAX: return X86::EAX;
374 case X86::RCX: return X86::ECX;
375 case X86::RDX: return X86::EDX;
376 case X86::RBX: return X86::EBX;
377 case X86::RBP: return X86::EBP;
378 case X86::RSP: return X86::ESP;
379 case X86::RSI: return X86::ESI;
380 case X86::RDI: return X86::EDI;
381 case X86::R8: return X86::R8D;
382 case X86::R9: return X86::R9D;
383 case X86::R10: return X86::R10D;
384 case X86::R11: return X86::R11D;
385 case X86::R12: return X86::R12D;
386 case X86::R13: return X86::R13D;
387 case X86::R14: return X86::R14D;
388 case X86::R15: return X86::R15D;
389 case X86::RIP: return X86::EIP;
393 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
394 assert(N == 1 && "Invalid number of operands!");
395 unsigned RegNo = getReg();
396 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
397 RegNo = getGR32FromGR64(RegNo);
398 Inst.addOperand(MCOperand::CreateReg(RegNo));
400 void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
401 assert(N == 1 && "Invalid number of operands!");
402 addExpr(Inst, getImm());
404 void addImmOperands(MCInst &Inst, unsigned N) const {
405 assert(N == 1 && "Invalid number of operands!");
406 addExpr(Inst, getImm());
409 void addMemOperands(MCInst &Inst, unsigned N) const {
410 assert((N == 5) && "Invalid number of operands!");
411 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
412 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
413 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
414 addExpr(Inst, getMemDisp());
415 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
418 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
419 assert((N == 1) && "Invalid number of operands!");
420 // Add as immediates when possible.
421 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
422 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
424 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
427 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
428 assert((N == 2) && "Invalid number of operands!");
429 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
430 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
432 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
433 assert((N == 1) && "Invalid number of operands!");
434 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
437 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
438 assert((N == 2) && "Invalid number of operands!");
439 // Add as immediates when possible.
440 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
441 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
443 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
444 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
447 static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
448 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
449 auto Res = llvm::make_unique<X86Operand>(Token, Loc, EndLoc);
450 Res->Tok.Data = Str.data();
451 Res->Tok.Length = Str.size();
455 static std::unique_ptr<X86Operand>
456 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
457 bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
458 StringRef SymName = StringRef(), void *OpDecl = nullptr) {
459 auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc);
460 Res->Reg.RegNo = RegNo;
461 Res->AddressOf = AddressOf;
462 Res->OffsetOfLoc = OffsetOfLoc;
463 Res->SymName = SymName;
464 Res->OpDecl = OpDecl;
468 static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
469 SMLoc StartLoc, SMLoc EndLoc) {
470 auto Res = llvm::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
475 /// Create an absolute memory operand.
476 static std::unique_ptr<X86Operand>
477 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
478 unsigned Size = 0, StringRef SymName = StringRef(),
479 void *OpDecl = nullptr) {
480 auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
482 Res->Mem.Disp = Disp;
483 Res->Mem.BaseReg = 0;
484 Res->Mem.IndexReg = 0;
486 Res->Mem.Size = Size;
487 Res->Mem.ModeSize = ModeSize;
488 Res->SymName = SymName;
489 Res->OpDecl = OpDecl;
490 Res->AddressOf = false;
494 /// Create a generalized memory operand.
495 static std::unique_ptr<X86Operand>
496 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
497 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
498 SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(),
499 void *OpDecl = nullptr) {
500 // We should never just have a displacement, that should be parsed as an
501 // absolute memory operand.
502 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
504 // The scale should always be one of {1,2,4,8}.
505 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
507 auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
508 Res->Mem.SegReg = SegReg;
509 Res->Mem.Disp = Disp;
510 Res->Mem.BaseReg = BaseReg;
511 Res->Mem.IndexReg = IndexReg;
512 Res->Mem.Scale = Scale;
513 Res->Mem.Size = Size;
514 Res->Mem.ModeSize = ModeSize;
515 Res->SymName = SymName;
516 Res->OpDecl = OpDecl;
517 Res->AddressOf = false;
522 } // End of namespace llvm