1 //===-- X86Operand.h - Parsed X86 machine instruction --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
11 #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
13 #include "X86AsmParserCommon.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/ADT/STLExtras.h"
20 /// X86Operand - Instances of this class represent a parsed X86 machine
22 struct X86Operand : public MCParsedAsmOperand {
30 SMLoc StartLoc, EndLoc;
66 X86Operand(KindTy K, SMLoc Start, SMLoc End)
67 : Kind(K), StartLoc(Start), EndLoc(End) {}
69 StringRef getSymName() override { return SymName; }
70 void *getOpDecl() override { return OpDecl; }
72 /// getStartLoc - Get the location of the first token of this operand.
73 SMLoc getStartLoc() const override { return StartLoc; }
74 /// getEndLoc - Get the location of the last token of this operand.
75 SMLoc getEndLoc() const override { return EndLoc; }
76 /// getLocRange - Get the range between the first and last token of this
78 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
79 /// getOffsetOfLoc - Get the location of the offset operator.
80 SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
82 void print(raw_ostream &OS) const override {}
84 StringRef getToken() const {
85 assert(Kind == Token && "Invalid access!");
86 return StringRef(Tok.Data, Tok.Length);
88 void setTokenValue(StringRef Value) {
89 assert(Kind == Token && "Invalid access!");
90 Tok.Data = Value.data();
91 Tok.Length = Value.size();
94 unsigned getReg() const override {
95 assert(Kind == Register && "Invalid access!");
99 const MCExpr *getImm() const {
100 assert(Kind == Immediate && "Invalid access!");
104 const MCExpr *getMemDisp() const {
105 assert(Kind == Memory && "Invalid access!");
108 unsigned getMemSegReg() const {
109 assert(Kind == Memory && "Invalid access!");
112 unsigned getMemBaseReg() const {
113 assert(Kind == Memory && "Invalid access!");
116 unsigned getMemIndexReg() const {
117 assert(Kind == Memory && "Invalid access!");
120 unsigned getMemScale() const {
121 assert(Kind == Memory && "Invalid access!");
124 unsigned getMemModeSize() const {
125 assert(Kind == Memory && "Invalid access!");
129 bool isToken() const override {return Kind == Token; }
131 bool isImm() const override { return Kind == Immediate; }
133 bool isImmSExti16i8() const {
137 // If this isn't a constant expr, just assume it fits and let relaxation
139 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
143 // Otherwise, check the value is in a range that makes sense for this
145 return isImmSExti16i8Value(CE->getValue());
147 bool isImmSExti32i8() const {
151 // If this isn't a constant expr, just assume it fits and let relaxation
153 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
157 // Otherwise, check the value is in a range that makes sense for this
159 return isImmSExti32i8Value(CE->getValue());
161 bool isImmSExti64i8() const {
165 // If this isn't a constant expr, just assume it fits and let relaxation
167 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
171 // Otherwise, check the value is in a range that makes sense for this
173 return isImmSExti64i8Value(CE->getValue());
175 bool isImmSExti64i32() const {
179 // If this isn't a constant expr, just assume it fits and let relaxation
181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
185 // Otherwise, check the value is in a range that makes sense for this
187 return isImmSExti64i32Value(CE->getValue());
190 bool isOffsetOf() const override {
191 return OffsetOfLoc.getPointer();
194 bool needAddressOf() const override {
198 bool isMem() const override { return Kind == Memory; }
199 bool isMemUnsized() const {
200 return Kind == Memory && Mem.Size == 0;
202 bool isMem8() const {
203 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
205 bool isMem16() const {
206 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
208 bool isMem32() const {
209 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
211 bool isMem64() const {
212 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
214 bool isMem80() const {
215 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
217 bool isMem128() const {
218 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
220 bool isMem256() const {
221 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
223 bool isMem512() const {
224 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
227 bool isMemVX32() const {
228 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
229 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
231 bool isMemVY32() const {
232 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
233 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
235 bool isMemVX64() const {
236 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
237 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
239 bool isMemVY64() const {
240 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
241 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
243 bool isMemVZ32() const {
244 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
245 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
247 bool isMemVZ64() const {
248 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
249 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
252 bool isAbsMem() const {
253 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
254 !getMemIndexReg() && getMemScale() == 1;
257 bool isAbsMem16() const {
258 return isAbsMem() && Mem.ModeSize == 16;
261 bool isAbsMem32() const {
262 return isAbsMem() && Mem.ModeSize != 16;
265 bool isSrcIdx() const {
266 return !getMemIndexReg() && getMemScale() == 1 &&
267 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
268 getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
269 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
271 bool isSrcIdx8() const {
272 return isMem8() && isSrcIdx();
274 bool isSrcIdx16() const {
275 return isMem16() && isSrcIdx();
277 bool isSrcIdx32() const {
278 return isMem32() && isSrcIdx();
280 bool isSrcIdx64() const {
281 return isMem64() && isSrcIdx();
284 bool isDstIdx() const {
285 return !getMemIndexReg() && getMemScale() == 1 &&
286 (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
287 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
288 getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
289 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
291 bool isDstIdx8() const {
292 return isMem8() && isDstIdx();
294 bool isDstIdx16() const {
295 return isMem16() && isDstIdx();
297 bool isDstIdx32() const {
298 return isMem32() && isDstIdx();
300 bool isDstIdx64() const {
301 return isMem64() && isDstIdx();
304 bool isMemOffs() const {
305 return Kind == Memory && !getMemBaseReg() && !getMemIndexReg() &&
309 bool isMemOffs16_8() const {
310 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 8);
312 bool isMemOffs16_16() const {
313 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 16);
315 bool isMemOffs16_32() const {
316 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 32);
318 bool isMemOffs32_8() const {
319 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 8);
321 bool isMemOffs32_16() const {
322 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 16);
324 bool isMemOffs32_32() const {
325 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 32);
327 bool isMemOffs32_64() const {
328 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 64);
330 bool isMemOffs64_8() const {
331 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 8);
333 bool isMemOffs64_16() const {
334 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 16);
336 bool isMemOffs64_32() const {
337 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 32);
339 bool isMemOffs64_64() const {
340 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 64);
343 bool isReg() const override { return Kind == Register; }
345 bool isGR32orGR64() const {
346 return Kind == Register &&
347 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
348 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
351 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
352 // Add as immediates when possible.
353 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
354 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
356 Inst.addOperand(MCOperand::CreateExpr(Expr));
359 void addRegOperands(MCInst &Inst, unsigned N) const {
360 assert(N == 1 && "Invalid number of operands!");
361 Inst.addOperand(MCOperand::CreateReg(getReg()));
364 static unsigned getGR32FromGR64(unsigned RegNo) {
366 default: llvm_unreachable("Unexpected register");
367 case X86::RAX: return X86::EAX;
368 case X86::RCX: return X86::ECX;
369 case X86::RDX: return X86::EDX;
370 case X86::RBX: return X86::EBX;
371 case X86::RBP: return X86::EBP;
372 case X86::RSP: return X86::ESP;
373 case X86::RSI: return X86::ESI;
374 case X86::RDI: return X86::EDI;
375 case X86::R8: return X86::R8D;
376 case X86::R9: return X86::R9D;
377 case X86::R10: return X86::R10D;
378 case X86::R11: return X86::R11D;
379 case X86::R12: return X86::R12D;
380 case X86::R13: return X86::R13D;
381 case X86::R14: return X86::R14D;
382 case X86::R15: return X86::R15D;
383 case X86::RIP: return X86::EIP;
387 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
388 assert(N == 1 && "Invalid number of operands!");
389 unsigned RegNo = getReg();
390 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
391 RegNo = getGR32FromGR64(RegNo);
392 Inst.addOperand(MCOperand::CreateReg(RegNo));
395 void addImmOperands(MCInst &Inst, unsigned N) const {
396 assert(N == 1 && "Invalid number of operands!");
397 addExpr(Inst, getImm());
400 void addMemOperands(MCInst &Inst, unsigned N) const {
401 assert((N == 5) && "Invalid number of operands!");
402 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
403 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
404 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
405 addExpr(Inst, getMemDisp());
406 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
409 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
410 assert((N == 1) && "Invalid number of operands!");
411 // Add as immediates when possible.
412 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
413 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
415 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
418 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
419 assert((N == 2) && "Invalid number of operands!");
420 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
421 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
423 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
424 assert((N == 1) && "Invalid number of operands!");
425 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
428 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
429 assert((N == 2) && "Invalid number of operands!");
430 // Add as immediates when possible.
431 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
432 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
434 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
435 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
438 static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
439 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
440 auto Res = llvm::make_unique<X86Operand>(Token, Loc, EndLoc);
441 Res->Tok.Data = Str.data();
442 Res->Tok.Length = Str.size();
446 static std::unique_ptr<X86Operand>
447 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
448 bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
449 StringRef SymName = StringRef(), void *OpDecl = nullptr) {
450 auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc);
451 Res->Reg.RegNo = RegNo;
452 Res->AddressOf = AddressOf;
453 Res->OffsetOfLoc = OffsetOfLoc;
454 Res->SymName = SymName;
455 Res->OpDecl = OpDecl;
459 static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
460 SMLoc StartLoc, SMLoc EndLoc) {
461 auto Res = llvm::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
466 /// Create an absolute memory operand.
467 static std::unique_ptr<X86Operand>
468 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
469 unsigned Size = 0, StringRef SymName = StringRef(),
470 void *OpDecl = nullptr) {
471 auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
473 Res->Mem.Disp = Disp;
474 Res->Mem.BaseReg = 0;
475 Res->Mem.IndexReg = 0;
477 Res->Mem.Size = Size;
478 Res->Mem.ModeSize = ModeSize;
479 Res->SymName = SymName;
480 Res->OpDecl = OpDecl;
481 Res->AddressOf = false;
485 /// Create a generalized memory operand.
486 static std::unique_ptr<X86Operand>
487 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
488 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
489 SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(),
490 void *OpDecl = nullptr) {
491 // We should never just have a displacement, that should be parsed as an
492 // absolute memory operand.
493 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
495 // The scale should always be one of {1,2,4,8}.
496 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
498 auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
499 Res->Mem.SegReg = SegReg;
500 Res->Mem.Disp = Disp;
501 Res->Mem.BaseReg = BaseReg;
502 Res->Mem.IndexReg = IndexReg;
503 Res->Mem.Scale = Scale;
504 Res->Mem.Size = Size;
505 Res->Mem.ModeSize = ModeSize;
506 Res->SymName = SymName;
507 Res->OpDecl = OpDecl;
508 Res->AddressOf = false;
513 } // End of namespace llvm