1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/ADT/APFloat.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/ADT/Twine.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
37 static const char OpPrecedence[] = {
50 class X86AsmParser : public MCTargetAsmParser {
53 ParseInstructionInfo *InstInfo;
55 SMLoc consumeToken() {
56 SMLoc Result = Parser.getTok().getLoc();
61 enum InfixCalculatorTok {
74 class InfixCalculator {
75 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
76 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
77 SmallVector<ICToken, 4> PostfixStack;
80 int64_t popOperand() {
81 assert (!PostfixStack.empty() && "Poped an empty stack!");
82 ICToken Op = PostfixStack.pop_back_val();
83 assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
84 && "Expected and immediate or register!");
87 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
88 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
89 "Unexpected operand!");
90 PostfixStack.push_back(std::make_pair(Op, Val));
93 void popOperator() { InfixOperatorStack.pop_back(); }
94 void pushOperator(InfixCalculatorTok Op) {
95 // Push the new operator if the stack is empty.
96 if (InfixOperatorStack.empty()) {
97 InfixOperatorStack.push_back(Op);
101 // Push the new operator if it has a higher precedence than the operator
102 // on the top of the stack or the operator on the top of the stack is a
104 unsigned Idx = InfixOperatorStack.size() - 1;
105 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
106 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
107 InfixOperatorStack.push_back(Op);
111 // The operator on the top of the stack has higher precedence than the
113 unsigned ParenCount = 0;
115 // Nothing to process.
116 if (InfixOperatorStack.empty())
119 Idx = InfixOperatorStack.size() - 1;
120 StackOp = InfixOperatorStack[Idx];
121 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
124 // If we have an even parentheses count and we see a left parentheses,
125 // then stop processing.
126 if (!ParenCount && StackOp == IC_LPAREN)
129 if (StackOp == IC_RPAREN) {
131 InfixOperatorStack.pop_back();
132 } else if (StackOp == IC_LPAREN) {
134 InfixOperatorStack.pop_back();
136 InfixOperatorStack.pop_back();
137 PostfixStack.push_back(std::make_pair(StackOp, 0));
140 // Push the new operator.
141 InfixOperatorStack.push_back(Op);
144 // Push any remaining operators onto the postfix stack.
145 while (!InfixOperatorStack.empty()) {
146 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
147 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
148 PostfixStack.push_back(std::make_pair(StackOp, 0));
151 if (PostfixStack.empty())
154 SmallVector<ICToken, 16> OperandStack;
155 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
156 ICToken Op = PostfixStack[i];
157 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
158 OperandStack.push_back(Op);
160 assert (OperandStack.size() > 1 && "Too few operands.");
162 ICToken Op2 = OperandStack.pop_back_val();
163 ICToken Op1 = OperandStack.pop_back_val();
166 report_fatal_error("Unexpected operator!");
169 Val = Op1.second + Op2.second;
170 OperandStack.push_back(std::make_pair(IC_IMM, Val));
173 Val = Op1.second - Op2.second;
174 OperandStack.push_back(std::make_pair(IC_IMM, Val));
177 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
178 "Multiply operation with an immediate and a register!");
179 Val = Op1.second * Op2.second;
180 OperandStack.push_back(std::make_pair(IC_IMM, Val));
183 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
184 "Divide operation with an immediate and a register!");
185 assert (Op2.second != 0 && "Division by zero!");
186 Val = Op1.second / Op2.second;
187 OperandStack.push_back(std::make_pair(IC_IMM, Val));
190 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
191 "Or operation with an immediate and a register!");
192 Val = Op1.second | Op2.second;
193 OperandStack.push_back(std::make_pair(IC_IMM, Val));
196 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
197 "And operation with an immediate and a register!");
198 Val = Op1.second & Op2.second;
199 OperandStack.push_back(std::make_pair(IC_IMM, Val));
204 assert (OperandStack.size() == 1 && "Expected a single result.");
205 return OperandStack.pop_back_val().second;
209 enum IntelExprState {
226 class IntelExprStateMachine {
227 IntelExprState State, PrevState;
228 unsigned BaseReg, IndexReg, TmpReg, Scale;
232 bool StopOnLBrac, AddImmPrefix;
234 InlineAsmIdentifierInfo Info;
236 IntelExprStateMachine(int64_t imm, bool stoponlbrac, bool addimmprefix) :
237 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
238 Scale(1), Imm(imm), Sym(0), StopOnLBrac(stoponlbrac),
239 AddImmPrefix(addimmprefix) { Info.clear(); }
241 unsigned getBaseReg() { return BaseReg; }
242 unsigned getIndexReg() { return IndexReg; }
243 unsigned getScale() { return Scale; }
244 const MCExpr *getSym() { return Sym; }
245 StringRef getSymName() { return SymName; }
246 int64_t getImm() { return Imm + IC.execute(); }
247 bool isValidEndState() {
248 return State == IES_RBRAC || State == IES_INTEGER;
250 bool getStopOnLBrac() { return StopOnLBrac; }
251 bool getAddImmPrefix() { return AddImmPrefix; }
252 bool hadError() { return State == IES_ERROR; }
254 InlineAsmIdentifierInfo &getIdentifierInfo() {
259 IntelExprState CurrState = State;
268 IC.pushOperator(IC_OR);
271 PrevState = CurrState;
274 IntelExprState CurrState = State;
283 IC.pushOperator(IC_AND);
286 PrevState = CurrState;
289 IntelExprState CurrState = State;
298 IC.pushOperator(IC_PLUS);
299 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
300 // If we already have a BaseReg, then assume this is the IndexReg with
305 assert (!IndexReg && "BaseReg/IndexReg already set!");
312 PrevState = CurrState;
315 IntelExprState CurrState = State;
330 // Only push the minus operator if it is not a unary operator.
331 if (!(CurrState == IES_PLUS || CurrState == IES_MINUS ||
332 CurrState == IES_MULTIPLY || CurrState == IES_DIVIDE ||
333 CurrState == IES_LPAREN || CurrState == IES_LBRAC))
334 IC.pushOperator(IC_MINUS);
335 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
336 // If we already have a BaseReg, then assume this is the IndexReg with
341 assert (!IndexReg && "BaseReg/IndexReg already set!");
348 PrevState = CurrState;
350 void onRegister(unsigned Reg) {
351 IntelExprState CurrState = State;
358 State = IES_REGISTER;
360 IC.pushOperand(IC_REGISTER);
363 // Index Register - Scale * Register
364 if (PrevState == IES_INTEGER) {
365 assert (!IndexReg && "IndexReg already set!");
366 State = IES_REGISTER;
368 // Get the scale and replace the 'Scale * Register' with '0'.
369 Scale = IC.popOperand();
370 IC.pushOperand(IC_IMM);
377 PrevState = CurrState;
379 void onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName) {
389 SymName = SymRefName;
390 IC.pushOperand(IC_IMM);
394 void onInteger(int64_t TmpInt) {
395 IntelExprState CurrState = State;
408 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
409 // Index Register - Register * Scale
410 assert (!IndexReg && "IndexReg already set!");
413 // Get the scale and replace the 'Register * Scale' with '0'.
415 } else if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
416 PrevState == IES_OR || PrevState == IES_AND ||
417 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
418 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
419 CurrState == IES_MINUS) {
420 // Unary minus. No need to pop the minus operand because it was never
422 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm.
424 IC.pushOperand(IC_IMM, TmpInt);
428 PrevState = CurrState;
439 State = IES_MULTIPLY;
440 IC.pushOperator(IC_MULTIPLY);
453 IC.pushOperator(IC_DIVIDE);
465 IC.pushOperator(IC_PLUS);
470 IntelExprState CurrState = State;
479 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
480 // If we already have a BaseReg, then assume this is the IndexReg with
485 assert (!IndexReg && "BaseReg/IndexReg already set!");
492 PrevState = CurrState;
495 IntelExprState CurrState = State;
507 // FIXME: We don't handle this type of unary minus, yet.
508 if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
509 PrevState == IES_OR || PrevState == IES_AND ||
510 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
511 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
512 CurrState == IES_MINUS) {
517 IC.pushOperator(IC_LPAREN);
520 PrevState = CurrState;
532 IC.pushOperator(IC_RPAREN);
538 MCAsmParser &getParser() const { return Parser; }
540 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
542 bool Error(SMLoc L, const Twine &Msg,
543 ArrayRef<SMRange> Ranges = None,
544 bool MatchingInlineAsm = false) {
545 if (MatchingInlineAsm) return true;
546 return Parser.Error(L, Msg, Ranges);
549 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
554 X86Operand *DefaultMemSIOperand(SMLoc Loc);
555 X86Operand *DefaultMemDIOperand(SMLoc Loc);
556 X86Operand *ParseOperand();
557 X86Operand *ParseATTOperand();
558 X86Operand *ParseIntelOperand();
559 X86Operand *ParseIntelOffsetOfOperator();
560 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
561 X86Operand *ParseIntelOperator(unsigned OpKind);
562 X86Operand *ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
563 X86Operand *ParseIntelMemOperand(int64_t ImmDisp, SMLoc StartLoc,
565 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
566 X86Operand *ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
567 int64_t ImmDisp, unsigned Size);
568 bool ParseIntelIdentifier(const MCExpr *&Val, StringRef &Identifier,
569 InlineAsmIdentifierInfo &Info,
570 bool IsUnevaluatedOperand, SMLoc &End);
572 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
574 X86Operand *CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
575 unsigned BaseReg, unsigned IndexReg,
576 unsigned Scale, SMLoc Start, SMLoc End,
577 unsigned Size, StringRef Identifier,
578 InlineAsmIdentifierInfo &Info);
580 bool ParseDirectiveWord(unsigned Size, SMLoc L);
581 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
583 bool processInstruction(MCInst &Inst,
584 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
586 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
587 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
588 MCStreamer &Out, unsigned &ErrorInfo,
589 bool MatchingInlineAsm);
591 /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
592 /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
593 bool isSrcOp(X86Operand &Op);
595 /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
596 /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
597 bool isDstOp(X86Operand &Op);
599 bool is64BitMode() const {
600 // FIXME: Can tablegen auto-generate this?
601 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
603 bool is32BitMode() const {
604 // FIXME: Can tablegen auto-generate this?
605 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
607 bool is16BitMode() const {
608 // FIXME: Can tablegen auto-generate this?
609 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
611 void SwitchMode(uint64_t mode) {
612 uint64_t oldMode = STI.getFeatureBits() &
613 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
614 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
615 setAvailableFeatures(FB);
616 assert(mode == (STI.getFeatureBits() &
617 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
620 bool isParsingIntelSyntax() {
621 return getParser().getAssemblerDialect();
624 /// @name Auto-generated Matcher Functions
627 #define GET_ASSEMBLER_HEADER
628 #include "X86GenAsmMatcher.inc"
633 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
634 const MCInstrInfo &MII)
635 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
637 // Initialize the set of available features.
638 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
640 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
642 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
644 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
646 virtual bool ParseDirective(AsmToken DirectiveID);
648 } // end anonymous namespace
650 /// @name Auto-generated Match Functions
653 static unsigned MatchRegisterName(StringRef Name);
657 static bool isImmSExti16i8Value(uint64_t Value) {
658 return (( Value <= 0x000000000000007FULL)||
659 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
660 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
663 static bool isImmSExti32i8Value(uint64_t Value) {
664 return (( Value <= 0x000000000000007FULL)||
665 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
666 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
669 static bool isImmZExtu32u8Value(uint64_t Value) {
670 return (Value <= 0x00000000000000FFULL);
673 static bool isImmSExti64i8Value(uint64_t Value) {
674 return (( Value <= 0x000000000000007FULL)||
675 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
678 static bool isImmSExti64i32Value(uint64_t Value) {
679 return (( Value <= 0x000000007FFFFFFFULL)||
680 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
684 /// X86Operand - Instances of this class represent a parsed X86 machine
686 struct X86Operand : public MCParsedAsmOperand {
694 SMLoc StartLoc, EndLoc;
729 X86Operand(KindTy K, SMLoc Start, SMLoc End)
730 : Kind(K), StartLoc(Start), EndLoc(End) {}
732 StringRef getSymName() { return SymName; }
733 void *getOpDecl() { return OpDecl; }
735 /// getStartLoc - Get the location of the first token of this operand.
736 SMLoc getStartLoc() const { return StartLoc; }
737 /// getEndLoc - Get the location of the last token of this operand.
738 SMLoc getEndLoc() const { return EndLoc; }
739 /// getLocRange - Get the range between the first and last token of this
741 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
742 /// getOffsetOfLoc - Get the location of the offset operator.
743 SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
745 virtual void print(raw_ostream &OS) const {}
747 StringRef getToken() const {
748 assert(Kind == Token && "Invalid access!");
749 return StringRef(Tok.Data, Tok.Length);
751 void setTokenValue(StringRef Value) {
752 assert(Kind == Token && "Invalid access!");
753 Tok.Data = Value.data();
754 Tok.Length = Value.size();
757 unsigned getReg() const {
758 assert(Kind == Register && "Invalid access!");
762 const MCExpr *getImm() const {
763 assert(Kind == Immediate && "Invalid access!");
767 const MCExpr *getMemDisp() const {
768 assert(Kind == Memory && "Invalid access!");
771 unsigned getMemSegReg() const {
772 assert(Kind == Memory && "Invalid access!");
775 unsigned getMemBaseReg() const {
776 assert(Kind == Memory && "Invalid access!");
779 unsigned getMemIndexReg() const {
780 assert(Kind == Memory && "Invalid access!");
783 unsigned getMemScale() const {
784 assert(Kind == Memory && "Invalid access!");
788 bool isToken() const {return Kind == Token; }
790 bool isImm() const { return Kind == Immediate; }
792 bool isImmSExti16i8() const {
796 // If this isn't a constant expr, just assume it fits and let relaxation
798 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
802 // Otherwise, check the value is in a range that makes sense for this
804 return isImmSExti16i8Value(CE->getValue());
806 bool isImmSExti32i8() const {
810 // If this isn't a constant expr, just assume it fits and let relaxation
812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816 // Otherwise, check the value is in a range that makes sense for this
818 return isImmSExti32i8Value(CE->getValue());
820 bool isImmZExtu32u8() const {
824 // If this isn't a constant expr, just assume it fits and let relaxation
826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
830 // Otherwise, check the value is in a range that makes sense for this
832 return isImmZExtu32u8Value(CE->getValue());
834 bool isImmSExti64i8() const {
838 // If this isn't a constant expr, just assume it fits and let relaxation
840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
844 // Otherwise, check the value is in a range that makes sense for this
846 return isImmSExti64i8Value(CE->getValue());
848 bool isImmSExti64i32() const {
852 // If this isn't a constant expr, just assume it fits and let relaxation
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
858 // Otherwise, check the value is in a range that makes sense for this
860 return isImmSExti64i32Value(CE->getValue());
863 bool isOffsetOf() const {
864 return OffsetOfLoc.getPointer();
867 bool needAddressOf() const {
871 bool isMem() const { return Kind == Memory; }
872 bool isMem8() const {
873 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
875 bool isMem16() const {
876 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
878 bool isMem32() const {
879 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
881 bool isMem64() const {
882 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
884 bool isMem80() const {
885 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
887 bool isMem128() const {
888 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
890 bool isMem256() const {
891 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
893 bool isMem512() const {
894 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
897 bool isMemVX32() const {
898 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
899 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
901 bool isMemVY32() const {
902 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
903 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
905 bool isMemVX64() const {
906 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
907 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
909 bool isMemVY64() const {
910 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
911 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
913 bool isMemVZ32() const {
914 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
915 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
917 bool isMemVZ64() const {
918 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
919 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
922 bool isAbsMem() const {
923 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
924 !getMemIndexReg() && getMemScale() == 1;
927 bool isSrcIdx() const {
928 return !getMemIndexReg() && getMemScale() == 1 &&
929 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
930 getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
931 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
933 bool isSrcIdx8() const {
934 return isMem8() && isSrcIdx();
936 bool isSrcIdx16() const {
937 return isMem16() && isSrcIdx();
939 bool isSrcIdx32() const {
940 return isMem32() && isSrcIdx();
942 bool isSrcIdx64() const {
943 return isMem64() && isSrcIdx();
946 bool isDstIdx() const {
947 return !getMemIndexReg() && getMemScale() == 1 &&
948 (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
949 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
950 getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
951 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
953 bool isDstIdx8() const {
954 return isMem8() && isDstIdx();
956 bool isDstIdx16() const {
957 return isMem16() && isDstIdx();
959 bool isDstIdx32() const {
960 return isMem32() && isDstIdx();
962 bool isDstIdx64() const {
963 return isMem64() && isDstIdx();
966 bool isMemOffs8() const {
967 return Kind == Memory && !getMemBaseReg() &&
968 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 8);
970 bool isMemOffs16() const {
971 return Kind == Memory && !getMemBaseReg() &&
972 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 16);
974 bool isMemOffs32() const {
975 return Kind == Memory && !getMemBaseReg() &&
976 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 32);
978 bool isMemOffs64() const {
979 return Kind == Memory && !getMemBaseReg() &&
980 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 64);
983 bool isReg() const { return Kind == Register; }
985 bool isGR32orGR64() const {
986 return Kind == Register &&
987 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
988 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
991 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
992 // Add as immediates when possible.
993 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
994 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
996 Inst.addOperand(MCOperand::CreateExpr(Expr));
999 void addRegOperands(MCInst &Inst, unsigned N) const {
1000 assert(N == 1 && "Invalid number of operands!");
1001 Inst.addOperand(MCOperand::CreateReg(getReg()));
1004 static unsigned getGR32FromGR64(unsigned RegNo) {
1006 default: llvm_unreachable("Unexpected register");
1007 case X86::RAX: return X86::EAX;
1008 case X86::RCX: return X86::ECX;
1009 case X86::RDX: return X86::EDX;
1010 case X86::RBX: return X86::EBX;
1011 case X86::RBP: return X86::EBP;
1012 case X86::RSP: return X86::ESP;
1013 case X86::RSI: return X86::ESI;
1014 case X86::RDI: return X86::EDI;
1015 case X86::R8: return X86::R8D;
1016 case X86::R9: return X86::R9D;
1017 case X86::R10: return X86::R10D;
1018 case X86::R11: return X86::R11D;
1019 case X86::R12: return X86::R12D;
1020 case X86::R13: return X86::R13D;
1021 case X86::R14: return X86::R14D;
1022 case X86::R15: return X86::R15D;
1023 case X86::RIP: return X86::EIP;
1027 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
1028 assert(N == 1 && "Invalid number of operands!");
1029 unsigned RegNo = getReg();
1030 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
1031 RegNo = getGR32FromGR64(RegNo);
1032 Inst.addOperand(MCOperand::CreateReg(RegNo));
1035 void addImmOperands(MCInst &Inst, unsigned N) const {
1036 assert(N == 1 && "Invalid number of operands!");
1037 addExpr(Inst, getImm());
1040 void addMemOperands(MCInst &Inst, unsigned N) const {
1041 assert((N == 5) && "Invalid number of operands!");
1042 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1043 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
1044 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
1045 addExpr(Inst, getMemDisp());
1046 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1049 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
1050 assert((N == 1) && "Invalid number of operands!");
1051 // Add as immediates when possible.
1052 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
1053 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1055 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
1058 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
1059 assert((N == 2) && "Invalid number of operands!");
1060 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1061 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1063 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
1064 assert((N == 1) && "Invalid number of operands!");
1065 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1068 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
1069 assert((N == 2) && "Invalid number of operands!");
1070 // Add as immediates when possible.
1071 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
1072 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1074 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
1075 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1078 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
1079 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
1080 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
1081 Res->Tok.Data = Str.data();
1082 Res->Tok.Length = Str.size();
1086 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
1087 bool AddressOf = false,
1088 SMLoc OffsetOfLoc = SMLoc(),
1089 StringRef SymName = StringRef(),
1091 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
1092 Res->Reg.RegNo = RegNo;
1093 Res->AddressOf = AddressOf;
1094 Res->OffsetOfLoc = OffsetOfLoc;
1095 Res->SymName = SymName;
1096 Res->OpDecl = OpDecl;
1100 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
1101 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
1106 /// Create an absolute memory operand.
1107 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
1108 unsigned Size = 0, StringRef SymName = StringRef(),
1110 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
1111 Res->Mem.SegReg = 0;
1112 Res->Mem.Disp = Disp;
1113 Res->Mem.BaseReg = 0;
1114 Res->Mem.IndexReg = 0;
1116 Res->Mem.Size = Size;
1117 Res->SymName = SymName;
1118 Res->OpDecl = OpDecl;
1119 Res->AddressOf = false;
1123 /// Create a generalized memory operand.
1124 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
1125 unsigned BaseReg, unsigned IndexReg,
1126 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
1128 StringRef SymName = StringRef(),
1130 // We should never just have a displacement, that should be parsed as an
1131 // absolute memory operand.
1132 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
1134 // The scale should always be one of {1,2,4,8}.
1135 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
1137 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
1138 Res->Mem.SegReg = SegReg;
1139 Res->Mem.Disp = Disp;
1140 Res->Mem.BaseReg = BaseReg;
1141 Res->Mem.IndexReg = IndexReg;
1142 Res->Mem.Scale = Scale;
1143 Res->Mem.Size = Size;
1144 Res->SymName = SymName;
1145 Res->OpDecl = OpDecl;
1146 Res->AddressOf = false;
1151 } // end anonymous namespace.
1153 bool X86AsmParser::isSrcOp(X86Operand &Op) {
1155 is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
1157 return (Op.isMem() &&
1158 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
1159 isa<MCConstantExpr>(Op.Mem.Disp) &&
1160 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1161 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
1164 bool X86AsmParser::isDstOp(X86Operand &Op) {
1166 is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
1168 return Op.isMem() &&
1169 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
1170 isa<MCConstantExpr>(Op.Mem.Disp) &&
1171 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1172 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
1175 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1176 SMLoc &StartLoc, SMLoc &EndLoc) {
1178 const AsmToken &PercentTok = Parser.getTok();
1179 StartLoc = PercentTok.getLoc();
1181 // If we encounter a %, ignore it. This code handles registers with and
1182 // without the prefix, unprefixed registers can occur in cfi directives.
1183 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1184 Parser.Lex(); // Eat percent token.
1186 const AsmToken &Tok = Parser.getTok();
1187 EndLoc = Tok.getEndLoc();
1189 if (Tok.isNot(AsmToken::Identifier)) {
1190 if (isParsingIntelSyntax()) return true;
1191 return Error(StartLoc, "invalid register name",
1192 SMRange(StartLoc, EndLoc));
1195 RegNo = MatchRegisterName(Tok.getString());
1197 // If the match failed, try the register name as lowercase.
1199 RegNo = MatchRegisterName(Tok.getString().lower());
1201 if (!is64BitMode()) {
1202 // FIXME: This should be done using Requires<Not64BitMode> and
1203 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1205 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1207 if (RegNo == X86::RIZ ||
1208 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1209 X86II::isX86_64NonExtLowByteReg(RegNo) ||
1210 X86II::isX86_64ExtendedReg(RegNo))
1211 return Error(StartLoc, "register %"
1212 + Tok.getString() + " is only available in 64-bit mode",
1213 SMRange(StartLoc, EndLoc));
1216 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1217 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
1219 Parser.Lex(); // Eat 'st'
1221 // Check to see if we have '(4)' after %st.
1222 if (getLexer().isNot(AsmToken::LParen))
1227 const AsmToken &IntTok = Parser.getTok();
1228 if (IntTok.isNot(AsmToken::Integer))
1229 return Error(IntTok.getLoc(), "expected stack index");
1230 switch (IntTok.getIntVal()) {
1231 case 0: RegNo = X86::ST0; break;
1232 case 1: RegNo = X86::ST1; break;
1233 case 2: RegNo = X86::ST2; break;
1234 case 3: RegNo = X86::ST3; break;
1235 case 4: RegNo = X86::ST4; break;
1236 case 5: RegNo = X86::ST5; break;
1237 case 6: RegNo = X86::ST6; break;
1238 case 7: RegNo = X86::ST7; break;
1239 default: return Error(IntTok.getLoc(), "invalid stack index");
1242 if (getParser().Lex().isNot(AsmToken::RParen))
1243 return Error(Parser.getTok().getLoc(), "expected ')'");
1245 EndLoc = Parser.getTok().getEndLoc();
1246 Parser.Lex(); // Eat ')'
1250 EndLoc = Parser.getTok().getEndLoc();
1252 // If this is "db[0-7]", match it as an alias
1254 if (RegNo == 0 && Tok.getString().size() == 3 &&
1255 Tok.getString().startswith("db")) {
1256 switch (Tok.getString()[2]) {
1257 case '0': RegNo = X86::DR0; break;
1258 case '1': RegNo = X86::DR1; break;
1259 case '2': RegNo = X86::DR2; break;
1260 case '3': RegNo = X86::DR3; break;
1261 case '4': RegNo = X86::DR4; break;
1262 case '5': RegNo = X86::DR5; break;
1263 case '6': RegNo = X86::DR6; break;
1264 case '7': RegNo = X86::DR7; break;
1268 EndLoc = Parser.getTok().getEndLoc();
1269 Parser.Lex(); // Eat it.
1275 if (isParsingIntelSyntax()) return true;
1276 return Error(StartLoc, "invalid register name",
1277 SMRange(StartLoc, EndLoc));
1280 Parser.Lex(); // Eat identifier token.
1284 X86Operand *X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1286 is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
1287 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
1288 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
1289 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
1292 X86Operand *X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1294 is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
1295 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
1296 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
1297 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
1300 X86Operand *X86AsmParser::ParseOperand() {
1301 if (isParsingIntelSyntax())
1302 return ParseIntelOperand();
1303 return ParseATTOperand();
1306 /// getIntelMemOperandSize - Return intel memory operand size.
1307 static unsigned getIntelMemOperandSize(StringRef OpStr) {
1308 unsigned Size = StringSwitch<unsigned>(OpStr)
1309 .Cases("BYTE", "byte", 8)
1310 .Cases("WORD", "word", 16)
1311 .Cases("DWORD", "dword", 32)
1312 .Cases("QWORD", "qword", 64)
1313 .Cases("XWORD", "xword", 80)
1314 .Cases("XMMWORD", "xmmword", 128)
1315 .Cases("YMMWORD", "ymmword", 256)
1316 .Cases("ZMMWORD", "zmmword", 512)
1317 .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter
1323 X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
1324 unsigned BaseReg, unsigned IndexReg,
1325 unsigned Scale, SMLoc Start, SMLoc End,
1326 unsigned Size, StringRef Identifier,
1327 InlineAsmIdentifierInfo &Info){
1328 if (isa<MCSymbolRefExpr>(Disp)) {
1329 // If this is not a VarDecl then assume it is a FuncDecl or some other label
1330 // reference. We need an 'r' constraint here, so we need to create register
1331 // operand to ensure proper matching. Just pick a GPR based on the size of
1333 if (!Info.IsVarDecl) {
1335 is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1336 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,
1337 SMLoc(), Identifier, Info.OpDecl);
1340 Size = Info.Type * 8; // Size is in terms of bits in this context.
1342 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_SizeDirective, Start,
1347 // When parsing inline assembly we set the base register to a non-zero value
1348 // if we don't know the actual value at this time. This is necessary to
1349 // get the matching correct in some cases.
1350 BaseReg = BaseReg ? BaseReg : 1;
1351 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1352 End, Size, Identifier, Info.OpDecl);
1356 RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> *AsmRewrites,
1357 StringRef SymName, int64_t ImmDisp,
1358 int64_t FinalImmDisp, SMLoc &BracLoc,
1359 SMLoc &StartInBrac, SMLoc &End) {
1360 // Remove the '[' and ']' from the IR string.
1361 AsmRewrites->push_back(AsmRewrite(AOK_Skip, BracLoc, 1));
1362 AsmRewrites->push_back(AsmRewrite(AOK_Skip, End, 1));
1364 // If ImmDisp is non-zero, then we parsed a displacement before the
1365 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1366 // If ImmDisp doesn't match the displacement computed by the state machine
1367 // then we have an additional displacement in the bracketed expression.
1368 if (ImmDisp != FinalImmDisp) {
1370 // We have an immediate displacement before the bracketed expression.
1371 // Adjust this to match the final immediate displacement.
1373 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1374 E = AsmRewrites->end(); I != E; ++I) {
1375 if ((*I).Loc.getPointer() > BracLoc.getPointer())
1377 if ((*I).Kind == AOK_ImmPrefix || (*I).Kind == AOK_Imm) {
1378 assert (!Found && "ImmDisp already rewritten.");
1379 (*I).Kind = AOK_Imm;
1380 (*I).Len = BracLoc.getPointer() - (*I).Loc.getPointer();
1381 (*I).Val = FinalImmDisp;
1386 assert (Found && "Unable to rewrite ImmDisp.");
1389 // We have a symbolic and an immediate displacement, but no displacement
1390 // before the bracketed expression. Put the immediate displacement
1391 // before the bracketed expression.
1392 AsmRewrites->push_back(AsmRewrite(AOK_Imm, BracLoc, 0, FinalImmDisp));
1395 // Remove all the ImmPrefix rewrites within the brackets.
1396 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1397 E = AsmRewrites->end(); I != E; ++I) {
1398 if ((*I).Loc.getPointer() < StartInBrac.getPointer())
1400 if ((*I).Kind == AOK_ImmPrefix)
1401 (*I).Kind = AOK_Delete;
1403 const char *SymLocPtr = SymName.data();
1404 // Skip everything before the symbol.
1405 if (unsigned Len = SymLocPtr - StartInBrac.getPointer()) {
1406 assert(Len > 0 && "Expected a non-negative length.");
1407 AsmRewrites->push_back(AsmRewrite(AOK_Skip, StartInBrac, Len));
1409 // Skip everything after the symbol.
1410 if (unsigned Len = End.getPointer() - (SymLocPtr + SymName.size())) {
1411 SMLoc Loc = SMLoc::getFromPointer(SymLocPtr + SymName.size());
1412 assert(Len > 0 && "Expected a non-negative length.");
1413 AsmRewrites->push_back(AsmRewrite(AOK_Skip, Loc, Len));
1417 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1418 const AsmToken &Tok = Parser.getTok();
1422 bool UpdateLocLex = true;
1424 // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1425 // identifier. Don't try an parse it as a register.
1426 if (Tok.getString().startswith("."))
1429 // If we're parsing an immediate expression, we don't expect a '['.
1430 if (SM.getStopOnLBrac() && getLexer().getKind() == AsmToken::LBrac)
1433 switch (getLexer().getKind()) {
1435 if (SM.isValidEndState()) {
1439 return Error(Tok.getLoc(), "unknown token in expression");
1441 case AsmToken::EndOfStatement: {
1445 case AsmToken::Identifier: {
1446 // This could be a register or a symbolic displacement.
1449 SMLoc IdentLoc = Tok.getLoc();
1450 StringRef Identifier = Tok.getString();
1451 if(!ParseRegister(TmpReg, IdentLoc, End)) {
1452 SM.onRegister(TmpReg);
1453 UpdateLocLex = false;
1456 if (!isParsingInlineAsm()) {
1457 if (getParser().parsePrimaryExpr(Val, End))
1458 return Error(Tok.getLoc(), "Unexpected identifier!");
1460 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1461 if (ParseIntelIdentifier(Val, Identifier, Info,
1462 /*Unevaluated=*/false, End))
1465 SM.onIdentifierExpr(Val, Identifier);
1466 UpdateLocLex = false;
1469 return Error(Tok.getLoc(), "Unexpected identifier!");
1471 case AsmToken::Integer: {
1472 if (isParsingInlineAsm() && SM.getAddImmPrefix())
1473 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1475 // Look for 'b' or 'f' following an Integer as a directional label
1476 SMLoc Loc = getTok().getLoc();
1477 int64_t IntVal = getTok().getIntVal();
1478 End = consumeToken();
1479 UpdateLocLex = false;
1480 if (getLexer().getKind() == AsmToken::Identifier) {
1481 StringRef IDVal = getTok().getString();
1482 if (IDVal == "f" || IDVal == "b") {
1484 getContext().GetDirectionalLocalSymbol(IntVal,
1485 IDVal == "f" ? 1 : 0);
1486 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1488 MCSymbolRefExpr::Create(Sym, Variant, getContext());
1489 if (IDVal == "b" && Sym->isUndefined())
1490 return Error(Loc, "invalid reference to undefined symbol");
1491 StringRef Identifier = Sym->getName();
1492 SM.onIdentifierExpr(Val, Identifier);
1493 End = consumeToken();
1495 SM.onInteger(IntVal);
1498 SM.onInteger(IntVal);
1502 case AsmToken::Plus: SM.onPlus(); break;
1503 case AsmToken::Minus: SM.onMinus(); break;
1504 case AsmToken::Star: SM.onStar(); break;
1505 case AsmToken::Slash: SM.onDivide(); break;
1506 case AsmToken::Pipe: SM.onOr(); break;
1507 case AsmToken::Amp: SM.onAnd(); break;
1508 case AsmToken::LBrac: SM.onLBrac(); break;
1509 case AsmToken::RBrac: SM.onRBrac(); break;
1510 case AsmToken::LParen: SM.onLParen(); break;
1511 case AsmToken::RParen: SM.onRParen(); break;
1514 return Error(Tok.getLoc(), "unknown token in expression");
1516 if (!Done && UpdateLocLex)
1517 End = consumeToken();
1522 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
1525 const AsmToken &Tok = Parser.getTok();
1526 SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
1527 if (getLexer().isNot(AsmToken::LBrac))
1528 return ErrorOperand(BracLoc, "Expected '[' token!");
1529 Parser.Lex(); // Eat '['
1531 SMLoc StartInBrac = Tok.getLoc();
1532 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1533 // may have already parsed an immediate displacement before the bracketed
1535 IntelExprStateMachine SM(ImmDisp, /*StopOnLBrac=*/false, /*AddImmPrefix=*/true);
1536 if (ParseIntelExpression(SM, End))
1540 if (const MCExpr *Sym = SM.getSym()) {
1541 // A symbolic displacement.
1543 if (isParsingInlineAsm())
1544 RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),
1545 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
1548 // An immediate displacement only.
1549 Disp = MCConstantExpr::Create(SM.getImm(), getContext());
1552 // Parse the dot operator (e.g., [ebx].foo.bar).
1553 if (Tok.getString().startswith(".")) {
1554 const MCExpr *NewDisp;
1555 if (ParseIntelDotOperator(Disp, NewDisp))
1558 End = Tok.getEndLoc();
1559 Parser.Lex(); // Eat the field.
1563 int BaseReg = SM.getBaseReg();
1564 int IndexReg = SM.getIndexReg();
1565 int Scale = SM.getScale();
1566 if (!isParsingInlineAsm()) {
1568 if (!BaseReg && !IndexReg) {
1570 return X86Operand::CreateMem(Disp, Start, End, Size);
1572 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
1574 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1578 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1579 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1580 End, Size, SM.getSymName(), Info);
1583 // Inline assembly may use variable names with namespace alias qualifiers.
1584 bool X86AsmParser::ParseIntelIdentifier(const MCExpr *&Val,
1585 StringRef &Identifier,
1586 InlineAsmIdentifierInfo &Info,
1587 bool IsUnevaluatedOperand, SMLoc &End) {
1588 assert (isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1591 StringRef LineBuf(Identifier.data());
1592 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1594 const AsmToken &Tok = Parser.getTok();
1596 // Advance the token stream until the end of the current token is
1597 // after the end of what the frontend claimed.
1598 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1600 End = Tok.getEndLoc();
1603 assert(End.getPointer() <= EndPtr && "frontend claimed part of a token?");
1604 if (End.getPointer() == EndPtr) break;
1607 // Create the symbol reference.
1608 Identifier = LineBuf;
1609 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1610 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1611 Val = MCSymbolRefExpr::Create(Sym, Variant, getParser().getContext());
1615 /// \brief Parse intel style segment override.
1616 X86Operand *X86AsmParser::ParseIntelSegmentOverride(unsigned SegReg,
1619 assert(SegReg != 0 && "Tried to parse a segment override without a segment!");
1620 const AsmToken &Tok = Parser.getTok(); // Eat colon.
1621 if (Tok.isNot(AsmToken::Colon))
1622 return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1623 Parser.Lex(); // Eat ':'
1625 int64_t ImmDisp = 0;
1626 if (getLexer().is(AsmToken::Integer)) {
1627 ImmDisp = Tok.getIntVal();
1628 AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
1630 if (isParsingInlineAsm())
1631 InstInfo->AsmRewrites->push_back(
1632 AsmRewrite(AOK_ImmPrefix, ImmDispToken.getLoc()));
1634 if (getLexer().isNot(AsmToken::LBrac)) {
1635 // An immediate following a 'segment register', 'colon' token sequence can
1636 // be followed by a bracketed expression. If it isn't we know we have our
1637 // final segment override.
1638 const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext());
1639 return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0, /*IndexReg=*/0,
1640 /*Scale=*/1, Start, ImmDispToken.getEndLoc(),
1645 if (getLexer().is(AsmToken::LBrac))
1646 return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1650 if (!isParsingInlineAsm()) {
1651 if (getParser().parsePrimaryExpr(Val, End))
1652 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1654 return X86Operand::CreateMem(Val, Start, End, Size);
1657 InlineAsmIdentifierInfo Info;
1658 StringRef Identifier = Tok.getString();
1659 if (ParseIntelIdentifier(Val, Identifier, Info,
1660 /*Unevaluated=*/false, End))
1662 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1663 /*Scale=*/1, Start, End, Size, Identifier, Info);
1666 /// ParseIntelMemOperand - Parse intel style memory operand.
1667 X86Operand *X86AsmParser::ParseIntelMemOperand(int64_t ImmDisp, SMLoc Start,
1669 const AsmToken &Tok = Parser.getTok();
1672 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1673 if (getLexer().is(AsmToken::LBrac))
1674 return ParseIntelBracExpression(/*SegReg=*/0, Start, ImmDisp, Size);
1677 if (!isParsingInlineAsm()) {
1678 if (getParser().parsePrimaryExpr(Val, End))
1679 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1681 return X86Operand::CreateMem(Val, Start, End, Size);
1684 InlineAsmIdentifierInfo Info;
1685 StringRef Identifier = Tok.getString();
1686 if (ParseIntelIdentifier(Val, Identifier, Info,
1687 /*Unevaluated=*/false, End))
1689 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1690 /*Scale=*/1, Start, End, Size, Identifier, Info);
1693 /// Parse the '.' operator.
1694 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
1695 const MCExpr *&NewDisp) {
1696 const AsmToken &Tok = Parser.getTok();
1697 int64_t OrigDispVal, DotDispVal;
1699 // FIXME: Handle non-constant expressions.
1700 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp))
1701 OrigDispVal = OrigDisp->getValue();
1703 return Error(Tok.getLoc(), "Non-constant offsets are not supported!");
1706 StringRef DotDispStr = Tok.getString().drop_front(1);
1708 // .Imm gets lexed as a real.
1709 if (Tok.is(AsmToken::Real)) {
1711 DotDispStr.getAsInteger(10, DotDisp);
1712 DotDispVal = DotDisp.getZExtValue();
1713 } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1715 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1716 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1718 return Error(Tok.getLoc(), "Unable to lookup field reference!");
1719 DotDispVal = DotDisp;
1721 return Error(Tok.getLoc(), "Unexpected token type!");
1723 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1724 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1725 unsigned Len = DotDispStr.size();
1726 unsigned Val = OrigDispVal + DotDispVal;
1727 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
1731 NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
1735 /// Parse the 'offset' operator. This operator is used to specify the
1736 /// location rather then the content of a variable.
1737 X86Operand *X86AsmParser::ParseIntelOffsetOfOperator() {
1738 const AsmToken &Tok = Parser.getTok();
1739 SMLoc OffsetOfLoc = Tok.getLoc();
1740 Parser.Lex(); // Eat offset.
1743 InlineAsmIdentifierInfo Info;
1744 SMLoc Start = Tok.getLoc(), End;
1745 StringRef Identifier = Tok.getString();
1746 if (ParseIntelIdentifier(Val, Identifier, Info,
1747 /*Unevaluated=*/false, End))
1750 // Don't emit the offset operator.
1751 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
1753 // The offset operator will have an 'r' constraint, thus we need to create
1754 // register operand to ensure proper matching. Just pick a GPR based on
1755 // the size of a pointer.
1757 is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1758 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1759 OffsetOfLoc, Identifier, Info.OpDecl);
1762 enum IntelOperatorKind {
1768 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1769 /// returns the number of elements in an array. It returns the value 1 for
1770 /// non-array variables. The SIZE operator returns the size of a C or C++
1771 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1772 /// TYPE operator returns the size of a C or C++ type or variable. If the
1773 /// variable is an array, TYPE returns the size of a single element.
1774 X86Operand *X86AsmParser::ParseIntelOperator(unsigned OpKind) {
1775 const AsmToken &Tok = Parser.getTok();
1776 SMLoc TypeLoc = Tok.getLoc();
1777 Parser.Lex(); // Eat operator.
1779 const MCExpr *Val = 0;
1780 InlineAsmIdentifierInfo Info;
1781 SMLoc Start = Tok.getLoc(), End;
1782 StringRef Identifier = Tok.getString();
1783 if (ParseIntelIdentifier(Val, Identifier, Info,
1784 /*Unevaluated=*/true, End))
1788 return ErrorOperand(Start, "unable to lookup expression");
1792 default: llvm_unreachable("Unexpected operand kind!");
1793 case IOK_LENGTH: CVal = Info.Length; break;
1794 case IOK_SIZE: CVal = Info.Size; break;
1795 case IOK_TYPE: CVal = Info.Type; break;
1798 // Rewrite the type operator and the C or C++ type or variable in terms of an
1799 // immediate. E.g. TYPE foo -> $$4
1800 unsigned Len = End.getPointer() - TypeLoc.getPointer();
1801 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, CVal));
1803 const MCExpr *Imm = MCConstantExpr::Create(CVal, getContext());
1804 return X86Operand::CreateImm(Imm, Start, End);
1807 X86Operand *X86AsmParser::ParseIntelOperand() {
1808 const AsmToken &Tok = Parser.getTok();
1811 // Offset, length, type and size operators.
1812 if (isParsingInlineAsm()) {
1813 StringRef AsmTokStr = Tok.getString();
1814 if (AsmTokStr == "offset" || AsmTokStr == "OFFSET")
1815 return ParseIntelOffsetOfOperator();
1816 if (AsmTokStr == "length" || AsmTokStr == "LENGTH")
1817 return ParseIntelOperator(IOK_LENGTH);
1818 if (AsmTokStr == "size" || AsmTokStr == "SIZE")
1819 return ParseIntelOperator(IOK_SIZE);
1820 if (AsmTokStr == "type" || AsmTokStr == "TYPE")
1821 return ParseIntelOperator(IOK_TYPE);
1824 unsigned Size = getIntelMemOperandSize(Tok.getString());
1826 Parser.Lex(); // Eat operand size (e.g., byte, word).
1827 if (Tok.getString() != "PTR" && Tok.getString() != "ptr")
1828 return ErrorOperand(Start, "Expected 'PTR' or 'ptr' token!");
1829 Parser.Lex(); // Eat ptr.
1831 Start = Tok.getLoc();
1834 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Minus) ||
1835 getLexer().is(AsmToken::LParen)) {
1836 AsmToken StartTok = Tok;
1837 IntelExprStateMachine SM(/*Imm=*/0, /*StopOnLBrac=*/true,
1838 /*AddImmPrefix=*/false);
1839 if (ParseIntelExpression(SM, End))
1842 int64_t Imm = SM.getImm();
1843 if (isParsingInlineAsm()) {
1844 unsigned Len = Tok.getLoc().getPointer() - Start.getPointer();
1845 if (StartTok.getString().size() == Len)
1846 // Just add a prefix if this wasn't a complex immediate expression.
1847 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix, Start));
1849 // Otherwise, rewrite the complex expression as a single immediate.
1850 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, Start, Len, Imm));
1853 if (getLexer().isNot(AsmToken::LBrac)) {
1854 // If a directional label (ie. 1f or 2b) was parsed above from
1855 // ParseIntelExpression() then SM.getSym() was set to a pointer to
1856 // to the MCExpr with the directional local symbol and this is a
1857 // memory operand not an immediate operand.
1859 return X86Operand::CreateMem(SM.getSym(), Start, End, Size);
1861 const MCExpr *ImmExpr = MCConstantExpr::Create(Imm, getContext());
1862 return X86Operand::CreateImm(ImmExpr, Start, End);
1865 // Only positive immediates are valid.
1867 return ErrorOperand(Start, "expected a positive immediate displacement "
1868 "before bracketed expr.");
1870 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1871 return ParseIntelMemOperand(Imm, Start, Size);
1876 if (!ParseRegister(RegNo, Start, End)) {
1877 // If this is a segment register followed by a ':', then this is the start
1878 // of a segment override, otherwise this is a normal register reference.
1879 if (getLexer().isNot(AsmToken::Colon))
1880 return X86Operand::CreateReg(RegNo, Start, End);
1882 return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
1886 return ParseIntelMemOperand(/*Disp=*/0, Start, Size);
1889 X86Operand *X86AsmParser::ParseATTOperand() {
1890 switch (getLexer().getKind()) {
1892 // Parse a memory operand with no segment register.
1893 return ParseMemOperand(0, Parser.getTok().getLoc());
1894 case AsmToken::Percent: {
1895 // Read the register.
1898 if (ParseRegister(RegNo, Start, End)) return 0;
1899 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1900 Error(Start, "%eiz and %riz can only be used as index registers",
1901 SMRange(Start, End));
1905 // If this is a segment register followed by a ':', then this is the start
1906 // of a memory reference, otherwise this is a normal register reference.
1907 if (getLexer().isNot(AsmToken::Colon))
1908 return X86Operand::CreateReg(RegNo, Start, End);
1910 getParser().Lex(); // Eat the colon.
1911 return ParseMemOperand(RegNo, Start);
1913 case AsmToken::Dollar: {
1914 // $42 -> immediate.
1915 SMLoc Start = Parser.getTok().getLoc(), End;
1918 if (getParser().parseExpression(Val, End))
1920 return X86Operand::CreateImm(Val, Start, End);
1925 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1926 /// has already been parsed if present.
1927 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
1929 // We have to disambiguate a parenthesized expression "(4+5)" from the start
1930 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
1931 // only way to do this without lookahead is to eat the '(' and see what is
1933 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1934 if (getLexer().isNot(AsmToken::LParen)) {
1936 if (getParser().parseExpression(Disp, ExprEnd)) return 0;
1938 // After parsing the base expression we could either have a parenthesized
1939 // memory address or not. If not, return now. If so, eat the (.
1940 if (getLexer().isNot(AsmToken::LParen)) {
1941 // Unless we have a segment register, treat this as an immediate.
1943 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
1944 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1950 // Okay, we have a '('. We don't know if this is an expression or not, but
1951 // so we have to eat the ( to see beyond it.
1952 SMLoc LParenLoc = Parser.getTok().getLoc();
1953 Parser.Lex(); // Eat the '('.
1955 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
1956 // Nothing to do here, fall into the code below with the '(' part of the
1957 // memory operand consumed.
1961 // It must be an parenthesized expression, parse it now.
1962 if (getParser().parseParenExpression(Disp, ExprEnd))
1965 // After parsing the base expression we could either have a parenthesized
1966 // memory address or not. If not, return now. If so, eat the (.
1967 if (getLexer().isNot(AsmToken::LParen)) {
1968 // Unless we have a segment register, treat this as an immediate.
1970 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
1971 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1979 // If we reached here, then we just ate the ( of the memory operand. Process
1980 // the rest of the memory operand.
1981 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1982 SMLoc IndexLoc, BaseLoc;
1984 if (getLexer().is(AsmToken::Percent)) {
1985 SMLoc StartLoc, EndLoc;
1986 BaseLoc = Parser.getTok().getLoc();
1987 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
1988 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1989 Error(StartLoc, "eiz and riz can only be used as index registers",
1990 SMRange(StartLoc, EndLoc));
1995 if (getLexer().is(AsmToken::Comma)) {
1996 Parser.Lex(); // Eat the comma.
1997 IndexLoc = Parser.getTok().getLoc();
1999 // Following the comma we should have either an index register, or a scale
2000 // value. We don't support the later form, but we want to parse it
2003 // Not that even though it would be completely consistent to support syntax
2004 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2005 if (getLexer().is(AsmToken::Percent)) {
2007 if (ParseRegister(IndexReg, L, L)) return 0;
2009 if (getLexer().isNot(AsmToken::RParen)) {
2010 // Parse the scale amount:
2011 // ::= ',' [scale-expression]
2012 if (getLexer().isNot(AsmToken::Comma)) {
2013 Error(Parser.getTok().getLoc(),
2014 "expected comma in scale expression");
2017 Parser.Lex(); // Eat the comma.
2019 if (getLexer().isNot(AsmToken::RParen)) {
2020 SMLoc Loc = Parser.getTok().getLoc();
2023 if (getParser().parseAbsoluteExpression(ScaleVal)){
2024 Error(Loc, "expected scale expression");
2028 // Validate the scale amount.
2029 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2031 Error(Loc, "scale factor in 16-bit address must be 1");
2034 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
2035 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
2038 Scale = (unsigned)ScaleVal;
2041 } else if (getLexer().isNot(AsmToken::RParen)) {
2042 // A scale amount without an index is ignored.
2044 SMLoc Loc = Parser.getTok().getLoc();
2047 if (getParser().parseAbsoluteExpression(Value))
2051 Warning(Loc, "scale factor without index register is ignored");
2056 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2057 if (getLexer().isNot(AsmToken::RParen)) {
2058 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
2061 SMLoc MemEnd = Parser.getTok().getEndLoc();
2062 Parser.Lex(); // Eat the ')'.
2064 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
2065 // and then only in non-64-bit modes. Except for DX, which is a special case
2066 // because an unofficial form of in/out instructions uses it.
2067 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2068 (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
2069 BaseReg != X86::SI && BaseReg != X86::DI)) &&
2070 BaseReg != X86::DX) {
2071 Error(BaseLoc, "invalid 16-bit base register");
2075 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2076 Error(IndexLoc, "16-bit memory operand may not include only index register");
2079 // If we have both a base register and an index register make sure they are
2080 // both 64-bit or 32-bit registers.
2081 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
2082 if (BaseReg != 0 && IndexReg != 0) {
2083 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
2084 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
2085 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
2086 IndexReg != X86::RIZ) {
2087 Error(BaseLoc, "base register is 64-bit, but index register is not");
2090 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
2091 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
2092 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
2093 IndexReg != X86::EIZ){
2094 Error(BaseLoc, "base register is 32-bit, but index register is not");
2097 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
2098 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
2099 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
2100 Error(BaseLoc, "base register is 16-bit, but index register is not");
2103 if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
2104 IndexReg != X86::SI && IndexReg != X86::DI) ||
2105 ((BaseReg == X86::SI || BaseReg == X86::DI) &&
2106 IndexReg != X86::BX && IndexReg != X86::BP)) {
2107 Error(BaseLoc, "invalid 16-bit base/index register combination");
2113 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
2118 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2119 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2121 StringRef PatchedName = Name;
2123 // FIXME: Hack to recognize setneb as setne.
2124 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2125 PatchedName != "setb" && PatchedName != "setnb")
2126 PatchedName = PatchedName.substr(0, Name.size()-1);
2128 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
2129 const MCExpr *ExtraImmOp = 0;
2130 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
2131 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2132 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
2133 bool IsVCMP = PatchedName[0] == 'v';
2134 unsigned SSECCIdx = IsVCMP ? 4 : 3;
2135 unsigned SSEComparisonCode = StringSwitch<unsigned>(
2136 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
2140 .Case("unord", 0x03)
2145 /* AVX only from here */
2146 .Case("eq_uq", 0x08)
2149 .Case("false", 0x0B)
2150 .Case("neq_oq", 0x0C)
2154 .Case("eq_os", 0x10)
2155 .Case("lt_oq", 0x11)
2156 .Case("le_oq", 0x12)
2157 .Case("unord_s", 0x13)
2158 .Case("neq_us", 0x14)
2159 .Case("nlt_uq", 0x15)
2160 .Case("nle_uq", 0x16)
2161 .Case("ord_s", 0x17)
2162 .Case("eq_us", 0x18)
2163 .Case("nge_uq", 0x19)
2164 .Case("ngt_uq", 0x1A)
2165 .Case("false_os", 0x1B)
2166 .Case("neq_os", 0x1C)
2167 .Case("ge_oq", 0x1D)
2168 .Case("gt_oq", 0x1E)
2169 .Case("true_us", 0x1F)
2171 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
2172 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
2173 getParser().getContext());
2174 if (PatchedName.endswith("ss")) {
2175 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
2176 } else if (PatchedName.endswith("sd")) {
2177 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
2178 } else if (PatchedName.endswith("ps")) {
2179 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
2181 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
2182 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
2187 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
2189 if (ExtraImmOp && !isParsingIntelSyntax())
2190 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
2192 // Determine whether this is an instruction prefix.
2194 Name == "lock" || Name == "rep" ||
2195 Name == "repe" || Name == "repz" ||
2196 Name == "repne" || Name == "repnz" ||
2197 Name == "rex64" || Name == "data16";
2200 // This does the actual operand parsing. Don't parse any more if we have a
2201 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2202 // just want to parse the "lock" as the first instruction and the "incl" as
2204 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
2206 // Parse '*' modifier.
2207 if (getLexer().is(AsmToken::Star))
2208 Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2210 // Read the first operand.
2211 if (X86Operand *Op = ParseOperand())
2212 Operands.push_back(Op);
2214 Parser.eatToEndOfStatement();
2218 while (getLexer().is(AsmToken::Comma)) {
2219 Parser.Lex(); // Eat the comma.
2221 // Parse and remember the operand.
2222 if (X86Operand *Op = ParseOperand())
2223 Operands.push_back(Op);
2225 Parser.eatToEndOfStatement();
2230 if (STI.getFeatureBits() & X86::FeatureAVX512) {
2231 // Parse mask register {%k1}
2232 if (getLexer().is(AsmToken::LCurly)) {
2233 Operands.push_back(X86Operand::CreateToken("{", consumeToken()));
2234 if (X86Operand *Op = ParseOperand()) {
2235 Operands.push_back(Op);
2236 if (!getLexer().is(AsmToken::RCurly)) {
2237 SMLoc Loc = getLexer().getLoc();
2238 Parser.eatToEndOfStatement();
2239 return Error(Loc, "Expected } at this point");
2241 Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2243 Parser.eatToEndOfStatement();
2247 // TODO: add parsing of broadcasts {1to8}, {1to16}
2248 // Parse "zeroing non-masked" semantic {z}
2249 if (getLexer().is(AsmToken::LCurly)) {
2250 Operands.push_back(X86Operand::CreateToken("{z}", consumeToken()));
2251 if (!getLexer().is(AsmToken::Identifier) || getLexer().getTok().getIdentifier() != "z") {
2252 SMLoc Loc = getLexer().getLoc();
2253 Parser.eatToEndOfStatement();
2254 return Error(Loc, "Expected z at this point");
2256 Parser.Lex(); // Eat the z
2257 if (!getLexer().is(AsmToken::RCurly)) {
2258 SMLoc Loc = getLexer().getLoc();
2259 Parser.eatToEndOfStatement();
2260 return Error(Loc, "Expected } at this point");
2262 Parser.Lex(); // Eat the }
2266 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2267 SMLoc Loc = getLexer().getLoc();
2268 Parser.eatToEndOfStatement();
2269 return Error(Loc, "unexpected token in argument list");
2273 if (getLexer().is(AsmToken::EndOfStatement))
2274 Parser.Lex(); // Consume the EndOfStatement
2275 else if (isPrefix && getLexer().is(AsmToken::Slash))
2276 Parser.Lex(); // Consume the prefix separator Slash
2278 if (ExtraImmOp && isParsingIntelSyntax())
2279 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
2281 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
2282 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2283 // documented form in various unofficial manuals, so a lot of code uses it.
2284 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
2285 Operands.size() == 3) {
2286 X86Operand &Op = *(X86Operand*)Operands.back();
2287 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2288 isa<MCConstantExpr>(Op.Mem.Disp) &&
2289 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2290 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2291 SMLoc Loc = Op.getEndLoc();
2292 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2296 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
2297 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
2298 Operands.size() == 3) {
2299 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2300 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2301 isa<MCConstantExpr>(Op.Mem.Disp) &&
2302 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2303 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2304 SMLoc Loc = Op.getEndLoc();
2305 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2309 // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
2310 if (Name.startswith("ins") && Operands.size() == 3 &&
2311 (Name == "insb" || Name == "insw" || Name == "insl")) {
2312 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2313 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2314 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
2315 Operands.pop_back();
2316 Operands.pop_back();
2322 // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
2323 if (Name.startswith("outs") && Operands.size() == 3 &&
2324 (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
2325 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2326 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2327 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
2328 Operands.pop_back();
2329 Operands.pop_back();
2335 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
2336 if (Name.startswith("movs") && Operands.size() == 3 &&
2337 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
2338 (is64BitMode() && Name == "movsq"))) {
2339 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2340 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2341 if (isSrcOp(Op) && isDstOp(Op2)) {
2342 Operands.pop_back();
2343 Operands.pop_back();
2348 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2349 // values of $SIREG according to the mode. It would be nice if this
2350 // could be achieved with InstAlias in the tables.
2351 if (Name.startswith("lods") && Operands.size() == 1 &&
2352 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2353 Name == "lodsl" || Name == "lodsd" || Name == "lodsq"))
2354 Operands.push_back(DefaultMemSIOperand(NameLoc));
2356 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2357 // values of $DIREG according to the mode. It would be nice if this
2358 // could be achieved with InstAlias in the tables.
2359 if (Name.startswith("stos") && Operands.size() == 1 &&
2360 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2361 Name == "stosl" || Name == "stosd" || Name == "stosq"))
2362 Operands.push_back(DefaultMemDIOperand(NameLoc));
2364 // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2365 // values of $DIREG according to the mode. It would be nice if this
2366 // could be achieved with InstAlias in the tables.
2367 if (Name.startswith("scas") && Operands.size() == 1 &&
2368 (Name == "scas" || Name == "scasb" || Name == "scasw" ||
2369 Name == "scasl" || Name == "scasd" || Name == "scasq"))
2370 Operands.push_back(DefaultMemDIOperand(NameLoc));
2372 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2374 if ((Name.startswith("shr") || Name.startswith("sar") ||
2375 Name.startswith("shl") || Name.startswith("sal") ||
2376 Name.startswith("rcl") || Name.startswith("rcr") ||
2377 Name.startswith("rol") || Name.startswith("ror")) &&
2378 Operands.size() == 3) {
2379 if (isParsingIntelSyntax()) {
2381 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
2382 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2383 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2385 Operands.pop_back();
2388 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2389 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2390 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2392 Operands.erase(Operands.begin() + 1);
2397 // Transforms "int $3" into "int3" as a size optimization. We can't write an
2398 // instalias with an immediate operand yet.
2399 if (Name == "int" && Operands.size() == 2) {
2400 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2401 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2402 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
2404 Operands.erase(Operands.begin() + 1);
2405 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
2412 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
2415 TmpInst.setOpcode(Opcode);
2417 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2418 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2419 TmpInst.addOperand(Inst.getOperand(0));
2424 static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
2425 bool isCmp = false) {
2426 if (!Inst.getOperand(0).isImm() ||
2427 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
2430 return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2433 static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
2434 bool isCmp = false) {
2435 if (!Inst.getOperand(0).isImm() ||
2436 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
2439 return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2442 static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
2443 bool isCmp = false) {
2444 if (!Inst.getOperand(0).isImm() ||
2445 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
2448 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2452 processInstruction(MCInst &Inst,
2453 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
2454 switch (Inst.getOpcode()) {
2455 default: return false;
2456 case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2457 case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2458 case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2459 case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2460 case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2461 case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2462 case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
2463 case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
2464 case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
2465 case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2466 case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2467 case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2468 case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2469 case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2470 case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2471 case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2472 case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2473 case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2474 case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2475 case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2476 case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2477 case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2478 case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2479 case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2480 case X86::VMOVAPDrr:
2481 case X86::VMOVAPDYrr:
2482 case X86::VMOVAPSrr:
2483 case X86::VMOVAPSYrr:
2484 case X86::VMOVDQArr:
2485 case X86::VMOVDQAYrr:
2486 case X86::VMOVDQUrr:
2487 case X86::VMOVDQUYrr:
2488 case X86::VMOVUPDrr:
2489 case X86::VMOVUPDYrr:
2490 case X86::VMOVUPSrr:
2491 case X86::VMOVUPSYrr: {
2492 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2493 !X86II::isX86_64ExtendedReg(Inst.getOperand(1).getReg()))
2497 switch (Inst.getOpcode()) {
2498 default: llvm_unreachable("Invalid opcode");
2499 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2500 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2501 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2502 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2503 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2504 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2505 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2506 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2507 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2508 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2509 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2510 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2512 Inst.setOpcode(NewOpc);
2516 case X86::VMOVSSrr: {
2517 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2518 !X86II::isX86_64ExtendedReg(Inst.getOperand(2).getReg()))
2521 switch (Inst.getOpcode()) {
2522 default: llvm_unreachable("Invalid opcode");
2523 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
2524 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
2526 Inst.setOpcode(NewOpc);
2532 static const char *getSubtargetFeatureName(unsigned Val);
2534 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2535 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2536 MCStreamer &Out, unsigned &ErrorInfo,
2537 bool MatchingInlineAsm) {
2538 assert(!Operands.empty() && "Unexpect empty operand list!");
2539 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
2540 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
2541 ArrayRef<SMRange> EmptyRanges = None;
2543 // First, handle aliases that expand to multiple instructions.
2544 // FIXME: This should be replaced with a real .td file alias mechanism.
2545 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2547 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
2548 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
2549 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
2550 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
2552 Inst.setOpcode(X86::WAIT);
2554 if (!MatchingInlineAsm)
2555 Out.EmitInstruction(Inst);
2558 StringSwitch<const char*>(Op->getToken())
2559 .Case("finit", "fninit")
2560 .Case("fsave", "fnsave")
2561 .Case("fstcw", "fnstcw")
2562 .Case("fstcww", "fnstcw")
2563 .Case("fstenv", "fnstenv")
2564 .Case("fstsw", "fnstsw")
2565 .Case("fstsww", "fnstsw")
2566 .Case("fclex", "fnclex")
2568 assert(Repl && "Unknown wait-prefixed instruction");
2570 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2573 bool WasOriginallyInvalidOperand = false;
2576 // First, try a direct match.
2577 switch (MatchInstructionImpl(Operands, Inst,
2578 ErrorInfo, MatchingInlineAsm,
2579 isParsingIntelSyntax())) {
2582 // Some instructions need post-processing to, for example, tweak which
2583 // encoding is selected. Loop on it while changes happen so the
2584 // individual transformations can chain off each other.
2585 if (!MatchingInlineAsm)
2586 while (processInstruction(Inst, Operands))
2590 if (!MatchingInlineAsm)
2591 Out.EmitInstruction(Inst);
2592 Opcode = Inst.getOpcode();
2594 case Match_MissingFeature: {
2595 assert(ErrorInfo && "Unknown missing feature!");
2596 // Special case the error message for the very common case where only
2597 // a single subtarget feature is missing.
2598 std::string Msg = "instruction requires:";
2600 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2601 if (ErrorInfo & Mask) {
2603 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
2607 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2609 case Match_InvalidOperand:
2610 WasOriginallyInvalidOperand = true;
2612 case Match_MnemonicFail:
2616 // FIXME: Ideally, we would only attempt suffix matches for things which are
2617 // valid prefixes, and we could just infer the right unambiguous
2618 // type. However, that requires substantially more matcher support than the
2621 // Change the operand to point to a temporary token.
2622 StringRef Base = Op->getToken();
2623 SmallString<16> Tmp;
2626 Op->setTokenValue(Tmp.str());
2628 // If this instruction starts with an 'f', then it is a floating point stack
2629 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2630 // 80-bit floating point, which use the suffixes s,l,t respectively.
2632 // Otherwise, we assume that this may be an integer instruction, which comes
2633 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2634 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2636 // Check for the various suffix matches.
2637 Tmp[Base.size()] = Suffixes[0];
2638 unsigned ErrorInfoIgnore;
2639 unsigned ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2640 unsigned Match1, Match2, Match3, Match4;
2642 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2643 MatchingInlineAsm, isParsingIntelSyntax());
2644 // If this returned as a missing feature failure, remember that.
2645 if (Match1 == Match_MissingFeature)
2646 ErrorInfoMissingFeature = ErrorInfoIgnore;
2647 Tmp[Base.size()] = Suffixes[1];
2648 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2649 MatchingInlineAsm, isParsingIntelSyntax());
2650 // If this returned as a missing feature failure, remember that.
2651 if (Match2 == Match_MissingFeature)
2652 ErrorInfoMissingFeature = ErrorInfoIgnore;
2653 Tmp[Base.size()] = Suffixes[2];
2654 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2655 MatchingInlineAsm, isParsingIntelSyntax());
2656 // If this returned as a missing feature failure, remember that.
2657 if (Match3 == Match_MissingFeature)
2658 ErrorInfoMissingFeature = ErrorInfoIgnore;
2659 Tmp[Base.size()] = Suffixes[3];
2660 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2661 MatchingInlineAsm, isParsingIntelSyntax());
2662 // If this returned as a missing feature failure, remember that.
2663 if (Match4 == Match_MissingFeature)
2664 ErrorInfoMissingFeature = ErrorInfoIgnore;
2666 // Restore the old token.
2667 Op->setTokenValue(Base);
2669 // If exactly one matched, then we treat that as a successful match (and the
2670 // instruction will already have been filled in correctly, since the failing
2671 // matches won't have modified it).
2672 unsigned NumSuccessfulMatches =
2673 (Match1 == Match_Success) + (Match2 == Match_Success) +
2674 (Match3 == Match_Success) + (Match4 == Match_Success);
2675 if (NumSuccessfulMatches == 1) {
2677 if (!MatchingInlineAsm)
2678 Out.EmitInstruction(Inst);
2679 Opcode = Inst.getOpcode();
2683 // Otherwise, the match failed, try to produce a decent error message.
2685 // If we had multiple suffix matches, then identify this as an ambiguous
2687 if (NumSuccessfulMatches > 1) {
2689 unsigned NumMatches = 0;
2690 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
2691 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
2692 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
2693 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
2695 SmallString<126> Msg;
2696 raw_svector_ostream OS(Msg);
2697 OS << "ambiguous instructions require an explicit suffix (could be ";
2698 for (unsigned i = 0; i != NumMatches; ++i) {
2701 if (i + 1 == NumMatches)
2703 OS << "'" << Base << MatchChars[i] << "'";
2706 Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
2710 // Okay, we know that none of the variants matched successfully.
2712 // If all of the instructions reported an invalid mnemonic, then the original
2713 // mnemonic was invalid.
2714 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
2715 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
2716 if (!WasOriginallyInvalidOperand) {
2717 ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
2719 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2720 Ranges, MatchingInlineAsm);
2723 // Recover location info for the operand if we know which was the problem.
2724 if (ErrorInfo != ~0U) {
2725 if (ErrorInfo >= Operands.size())
2726 return Error(IDLoc, "too few operands for instruction",
2727 EmptyRanges, MatchingInlineAsm);
2729 X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
2730 if (Operand->getStartLoc().isValid()) {
2731 SMRange OperandRange = Operand->getLocRange();
2732 return Error(Operand->getStartLoc(), "invalid operand for instruction",
2733 OperandRange, MatchingInlineAsm);
2737 return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2741 // If one instruction matched with a missing feature, report this as a
2743 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
2744 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
2745 std::string Msg = "instruction requires:";
2747 for (unsigned i = 0; i < (sizeof(ErrorInfoMissingFeature)*8-1); ++i) {
2748 if (ErrorInfoMissingFeature & Mask) {
2750 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2754 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2757 // If one instruction matched with an invalid operand, report this as an
2759 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
2760 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
2761 Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2766 // If all of these were an outright failure, report it in a useless way.
2767 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2768 EmptyRanges, MatchingInlineAsm);
2773 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
2774 StringRef IDVal = DirectiveID.getIdentifier();
2775 if (IDVal == ".word")
2776 return ParseDirectiveWord(2, DirectiveID.getLoc());
2777 else if (IDVal.startswith(".code"))
2778 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
2779 else if (IDVal.startswith(".att_syntax")) {
2780 getParser().setAssemblerDialect(0);
2782 } else if (IDVal.startswith(".intel_syntax")) {
2783 getParser().setAssemblerDialect(1);
2784 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2785 // FIXME: Handle noprefix
2786 if (Parser.getTok().getString() == "noprefix")
2794 /// ParseDirectiveWord
2795 /// ::= .word [ expression (, expression)* ]
2796 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2797 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2799 const MCExpr *Value;
2800 if (getParser().parseExpression(Value))
2803 getParser().getStreamer().EmitValue(Value, Size);
2805 if (getLexer().is(AsmToken::EndOfStatement))
2808 // FIXME: Improve diagnostic.
2809 if (getLexer().isNot(AsmToken::Comma)) {
2810 Error(L, "unexpected token in directive");
2821 /// ParseDirectiveCode
2822 /// ::= .code16 | .code32 | .code64
2823 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
2824 if (IDVal == ".code16") {
2826 if (!is16BitMode()) {
2827 SwitchMode(X86::Mode16Bit);
2828 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2830 } else if (IDVal == ".code32") {
2832 if (!is32BitMode()) {
2833 SwitchMode(X86::Mode32Bit);
2834 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2836 } else if (IDVal == ".code64") {
2838 if (!is64BitMode()) {
2839 SwitchMode(X86::Mode64Bit);
2840 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
2843 Error(L, "unknown directive " + IDVal);
2850 // Force static initialization.
2851 extern "C" void LLVMInitializeX86AsmParser() {
2852 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2853 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2856 #define GET_REGISTER_MATCHER
2857 #define GET_MATCHER_IMPLEMENTATION
2858 #define GET_SUBTARGET_FEATURE_NAME
2859 #include "X86GenAsmMatcher.inc"