1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/MC/MCTargetAsmParser.h"
12 #include "llvm/MC/MCStreamer.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/MC/MCParser/MCAsmLexer.h"
18 #include "llvm/MC/MCParser/MCAsmParser.h"
19 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/Support/SourceMgr.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Support/raw_ostream.h"
33 class X86AsmParser : public MCTargetAsmParser {
37 MCAsmParser &getParser() const { return Parser; }
39 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
41 bool Error(SMLoc L, const Twine &Msg,
42 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
43 return Parser.Error(L, Msg, Ranges);
46 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
51 X86Operand *ParseOperand();
52 X86Operand *ParseATTOperand();
53 X86Operand *ParseIntelOperand();
54 X86Operand *ParseIntelMemOperand();
55 X86Operand *ParseIntelBracExpression(unsigned SegReg, unsigned Size);
56 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
58 bool ParseDirectiveWord(unsigned Size, SMLoc L);
59 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
61 bool processInstruction(MCInst &Inst,
62 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
64 bool MatchAndEmitInstruction(SMLoc IDLoc,
65 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
68 /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
69 /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
70 bool isSrcOp(X86Operand &Op);
72 /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
73 /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
74 bool isDstOp(X86Operand &Op);
76 bool is64BitMode() const {
77 // FIXME: Can tablegen auto-generate this?
78 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
81 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
82 setAvailableFeatures(FB);
85 /// @name Auto-generated Matcher Functions
88 #define GET_ASSEMBLER_HEADER
89 #include "X86GenAsmMatcher.inc"
94 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
95 : MCTargetAsmParser(), STI(sti), Parser(parser) {
97 // Initialize the set of available features.
98 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
100 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
102 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
103 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
105 virtual bool ParseDirective(AsmToken DirectiveID);
107 bool isParsingIntelSyntax() {
108 return getParser().getAssemblerDialect();
111 } // end anonymous namespace
113 /// @name Auto-generated Match Functions
116 static unsigned MatchRegisterName(StringRef Name);
120 static bool isImmSExti16i8Value(uint64_t Value) {
121 return (( Value <= 0x000000000000007FULL)||
122 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
123 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
126 static bool isImmSExti32i8Value(uint64_t Value) {
127 return (( Value <= 0x000000000000007FULL)||
128 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
129 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
132 static bool isImmZExtu32u8Value(uint64_t Value) {
133 return (Value <= 0x00000000000000FFULL);
136 static bool isImmSExti64i8Value(uint64_t Value) {
137 return (( Value <= 0x000000000000007FULL)||
138 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
141 static bool isImmSExti64i32Value(uint64_t Value) {
142 return (( Value <= 0x000000007FFFFFFFULL)||
143 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
147 /// X86Operand - Instances of this class represent a parsed X86 machine
149 struct X86Operand : public MCParsedAsmOperand {
157 SMLoc StartLoc, EndLoc;
183 X86Operand(KindTy K, SMLoc Start, SMLoc End)
184 : Kind(K), StartLoc(Start), EndLoc(End) {}
186 /// getStartLoc - Get the location of the first token of this operand.
187 SMLoc getStartLoc() const { return StartLoc; }
188 /// getEndLoc - Get the location of the last token of this operand.
189 SMLoc getEndLoc() const { return EndLoc; }
191 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
193 virtual void print(raw_ostream &OS) const {}
195 StringRef getToken() const {
196 assert(Kind == Token && "Invalid access!");
197 return StringRef(Tok.Data, Tok.Length);
199 void setTokenValue(StringRef Value) {
200 assert(Kind == Token && "Invalid access!");
201 Tok.Data = Value.data();
202 Tok.Length = Value.size();
205 unsigned getReg() const {
206 assert(Kind == Register && "Invalid access!");
210 const MCExpr *getImm() const {
211 assert(Kind == Immediate && "Invalid access!");
215 const MCExpr *getMemDisp() const {
216 assert(Kind == Memory && "Invalid access!");
219 unsigned getMemSegReg() const {
220 assert(Kind == Memory && "Invalid access!");
223 unsigned getMemBaseReg() const {
224 assert(Kind == Memory && "Invalid access!");
227 unsigned getMemIndexReg() const {
228 assert(Kind == Memory && "Invalid access!");
231 unsigned getMemScale() const {
232 assert(Kind == Memory && "Invalid access!");
236 bool isToken() const {return Kind == Token; }
238 bool isImm() const { return Kind == Immediate; }
240 bool isImmSExti16i8() const {
244 // If this isn't a constant expr, just assume it fits and let relaxation
246 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
250 // Otherwise, check the value is in a range that makes sense for this
252 return isImmSExti16i8Value(CE->getValue());
254 bool isImmSExti32i8() const {
258 // If this isn't a constant expr, just assume it fits and let relaxation
260 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
264 // Otherwise, check the value is in a range that makes sense for this
266 return isImmSExti32i8Value(CE->getValue());
268 bool isImmZExtu32u8() const {
272 // If this isn't a constant expr, just assume it fits and let relaxation
274 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
278 // Otherwise, check the value is in a range that makes sense for this
280 return isImmZExtu32u8Value(CE->getValue());
282 bool isImmSExti64i8() const {
286 // If this isn't a constant expr, just assume it fits and let relaxation
288 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
292 // Otherwise, check the value is in a range that makes sense for this
294 return isImmSExti64i8Value(CE->getValue());
296 bool isImmSExti64i32() const {
300 // If this isn't a constant expr, just assume it fits and let relaxation
302 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
306 // Otherwise, check the value is in a range that makes sense for this
308 return isImmSExti64i32Value(CE->getValue());
311 bool isMem() const { return Kind == Memory; }
312 bool isMem8() const {
313 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
315 bool isMem16() const {
316 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
318 bool isMem32() const {
319 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
321 bool isMem64() const {
322 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
324 bool isMem80() const {
325 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
327 bool isMem128() const {
328 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
330 bool isMem256() const {
331 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
334 bool isAbsMem() const {
335 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
336 !getMemIndexReg() && getMemScale() == 1;
339 bool isReg() const { return Kind == Register; }
341 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
342 // Add as immediates when possible.
343 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
344 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
346 Inst.addOperand(MCOperand::CreateExpr(Expr));
349 void addRegOperands(MCInst &Inst, unsigned N) const {
350 assert(N == 1 && "Invalid number of operands!");
351 Inst.addOperand(MCOperand::CreateReg(getReg()));
354 void addImmOperands(MCInst &Inst, unsigned N) const {
355 assert(N == 1 && "Invalid number of operands!");
356 addExpr(Inst, getImm());
359 void addMem8Operands(MCInst &Inst, unsigned N) const {
360 addMemOperands(Inst, N);
362 void addMem16Operands(MCInst &Inst, unsigned N) const {
363 addMemOperands(Inst, N);
365 void addMem32Operands(MCInst &Inst, unsigned N) const {
366 addMemOperands(Inst, N);
368 void addMem64Operands(MCInst &Inst, unsigned N) const {
369 addMemOperands(Inst, N);
371 void addMem80Operands(MCInst &Inst, unsigned N) const {
372 addMemOperands(Inst, N);
374 void addMem128Operands(MCInst &Inst, unsigned N) const {
375 addMemOperands(Inst, N);
377 void addMem256Operands(MCInst &Inst, unsigned N) const {
378 addMemOperands(Inst, N);
381 void addMemOperands(MCInst &Inst, unsigned N) const {
382 assert((N == 5) && "Invalid number of operands!");
383 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
384 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
385 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
386 addExpr(Inst, getMemDisp());
387 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
390 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
391 assert((N == 1) && "Invalid number of operands!");
392 // Add as immediates when possible.
393 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
394 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
396 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
399 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
400 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size() - 1);
401 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
402 Res->Tok.Data = Str.data();
403 Res->Tok.Length = Str.size();
407 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
408 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
409 Res->Reg.RegNo = RegNo;
413 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
414 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
419 /// Create an absolute memory operand.
420 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
421 SMLoc EndLoc, unsigned Size = 0) {
422 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
424 Res->Mem.Disp = Disp;
425 Res->Mem.BaseReg = 0;
426 Res->Mem.IndexReg = 0;
428 Res->Mem.Size = Size;
432 /// Create a generalized memory operand.
433 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
434 unsigned BaseReg, unsigned IndexReg,
435 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
437 // We should never just have a displacement, that should be parsed as an
438 // absolute memory operand.
439 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
441 // The scale should always be one of {1,2,4,8}.
442 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
444 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
445 Res->Mem.SegReg = SegReg;
446 Res->Mem.Disp = Disp;
447 Res->Mem.BaseReg = BaseReg;
448 Res->Mem.IndexReg = IndexReg;
449 Res->Mem.Scale = Scale;
450 Res->Mem.Size = Size;
455 } // end anonymous namespace.
457 bool X86AsmParser::isSrcOp(X86Operand &Op) {
458 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
460 return (Op.isMem() &&
461 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
462 isa<MCConstantExpr>(Op.Mem.Disp) &&
463 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
464 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
467 bool X86AsmParser::isDstOp(X86Operand &Op) {
468 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
471 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
472 isa<MCConstantExpr>(Op.Mem.Disp) &&
473 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
474 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
477 bool X86AsmParser::ParseRegister(unsigned &RegNo,
478 SMLoc &StartLoc, SMLoc &EndLoc) {
480 if (!isParsingIntelSyntax()) {
481 const AsmToken &TokPercent = Parser.getTok();
482 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
483 StartLoc = TokPercent.getLoc();
484 Parser.Lex(); // Eat percent token.
487 const AsmToken &Tok = Parser.getTok();
488 if (Tok.isNot(AsmToken::Identifier)) {
489 if (isParsingIntelSyntax()) return true;
490 return Error(StartLoc, "invalid register name",
491 SMRange(StartLoc, Tok.getEndLoc()));
494 RegNo = MatchRegisterName(Tok.getString());
496 // If the match failed, try the register name as lowercase.
498 RegNo = MatchRegisterName(Tok.getString().lower());
500 if (!is64BitMode()) {
501 // FIXME: This should be done using Requires<In32BitMode> and
502 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
504 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
506 if (RegNo == X86::RIZ ||
507 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
508 X86II::isX86_64NonExtLowByteReg(RegNo) ||
509 X86II::isX86_64ExtendedReg(RegNo))
510 return Error(StartLoc, "register %"
511 + Tok.getString() + " is only available in 64-bit mode",
512 SMRange(StartLoc, Tok.getEndLoc()));
515 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
516 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
518 EndLoc = Tok.getLoc();
519 Parser.Lex(); // Eat 'st'
521 // Check to see if we have '(4)' after %st.
522 if (getLexer().isNot(AsmToken::LParen))
527 const AsmToken &IntTok = Parser.getTok();
528 if (IntTok.isNot(AsmToken::Integer))
529 return Error(IntTok.getLoc(), "expected stack index");
530 switch (IntTok.getIntVal()) {
531 case 0: RegNo = X86::ST0; break;
532 case 1: RegNo = X86::ST1; break;
533 case 2: RegNo = X86::ST2; break;
534 case 3: RegNo = X86::ST3; break;
535 case 4: RegNo = X86::ST4; break;
536 case 5: RegNo = X86::ST5; break;
537 case 6: RegNo = X86::ST6; break;
538 case 7: RegNo = X86::ST7; break;
539 default: return Error(IntTok.getLoc(), "invalid stack index");
542 if (getParser().Lex().isNot(AsmToken::RParen))
543 return Error(Parser.getTok().getLoc(), "expected ')'");
545 EndLoc = Tok.getLoc();
546 Parser.Lex(); // Eat ')'
550 // If this is "db[0-7]", match it as an alias
552 if (RegNo == 0 && Tok.getString().size() == 3 &&
553 Tok.getString().startswith("db")) {
554 switch (Tok.getString()[2]) {
555 case '0': RegNo = X86::DR0; break;
556 case '1': RegNo = X86::DR1; break;
557 case '2': RegNo = X86::DR2; break;
558 case '3': RegNo = X86::DR3; break;
559 case '4': RegNo = X86::DR4; break;
560 case '5': RegNo = X86::DR5; break;
561 case '6': RegNo = X86::DR6; break;
562 case '7': RegNo = X86::DR7; break;
566 EndLoc = Tok.getLoc();
567 Parser.Lex(); // Eat it.
573 if (isParsingIntelSyntax()) return true;
574 return Error(StartLoc, "invalid register name",
575 SMRange(StartLoc, Tok.getEndLoc()));
578 EndLoc = Tok.getEndLoc();
579 Parser.Lex(); // Eat identifier token.
583 X86Operand *X86AsmParser::ParseOperand() {
584 if (isParsingIntelSyntax())
585 return ParseIntelOperand();
586 return ParseATTOperand();
589 /// getIntelMemOperandSize - Return intel memory operand size.
590 static unsigned getIntelMemOperandSize(StringRef OpStr) {
592 if (OpStr == "BYTE") Size = 8;
593 if (OpStr == "WORD") Size = 16;
594 if (OpStr == "DWORD") Size = 32;
595 if (OpStr == "QWORD") Size = 64;
596 if (OpStr == "XWORD") Size = 80;
597 if (OpStr == "XMMWORD") Size = 128;
598 if (OpStr == "YMMWORD") Size = 256;
602 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
604 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
605 SMLoc Start = Parser.getTok().getLoc(), End;
607 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
608 // Parse [ BaseReg + Scale*IndexReg + Disp ] or [ symbol ]
611 if (getLexer().isNot(AsmToken::LBrac))
612 return ErrorOperand(Start, "Expected '[' token!");
615 if (getLexer().is(AsmToken::Identifier)) {
617 if (ParseRegister(BaseReg, Start, End)) {
618 // Handle '[' 'symbol' ']'
619 if (getParser().ParseExpression(Disp, End)) return 0;
620 if (getLexer().isNot(AsmToken::RBrac))
621 return ErrorOperand(Start, "Expected ']' token!");
623 return X86Operand::CreateMem(Disp, Start, End, Size);
625 } else if (getLexer().is(AsmToken::Integer)) {
626 int64_t Val = Parser.getTok().getIntVal();
628 SMLoc Loc = Parser.getTok().getLoc();
629 if (getLexer().is(AsmToken::RBrac)) {
630 // Handle '[' number ']'
632 const MCExpr *Disp = MCConstantExpr::Create(Val, getContext());
634 return X86Operand::CreateMem(SegReg, Disp, 0, 0, Scale,
636 return X86Operand::CreateMem(Disp, Start, End, Size);
637 } else if (getLexer().is(AsmToken::Star)) {
638 // Handle '[' Scale*IndexReg ']'
640 SMLoc IdxRegLoc = Parser.getTok().getLoc();
641 if (ParseRegister(IndexReg, IdxRegLoc, End))
642 return ErrorOperand(IdxRegLoc, "Expected register");
645 return ErrorOperand(Loc, "Unepxeted token");
648 if (getLexer().is(AsmToken::Plus) || getLexer().is(AsmToken::Minus)) {
649 bool isPlus = getLexer().is(AsmToken::Plus);
651 SMLoc PlusLoc = Parser.getTok().getLoc();
652 if (getLexer().is(AsmToken::Integer)) {
653 int64_t Val = Parser.getTok().getIntVal();
655 if (getLexer().is(AsmToken::Star)) {
657 SMLoc IdxRegLoc = Parser.getTok().getLoc();
658 if (ParseRegister(IndexReg, IdxRegLoc, End))
659 return ErrorOperand(IdxRegLoc, "Expected register");
661 } else if (getLexer().is(AsmToken::RBrac)) {
662 const MCExpr *ValExpr = MCConstantExpr::Create(Val, getContext());
663 Disp = isPlus ? ValExpr : MCConstantExpr::Create(0-Val, getContext());
665 return ErrorOperand(PlusLoc, "unexpected token after +");
666 } else if (getLexer().is(AsmToken::Identifier)) {
667 // This could be an index register or a displacement expression.
668 End = Parser.getTok().getLoc();
670 ParseRegister(IndexReg, Start, End);
671 else if (getParser().ParseExpression(Disp, End)) return 0;
675 if (getLexer().isNot(AsmToken::RBrac))
676 if (getParser().ParseExpression(Disp, End)) return 0;
678 End = Parser.getTok().getLoc();
679 if (getLexer().isNot(AsmToken::RBrac))
680 return ErrorOperand(End, "expected ']' token!");
682 End = Parser.getTok().getLoc();
685 if (!BaseReg && !IndexReg)
686 return X86Operand::CreateMem(Disp, Start, End, Size);
688 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
692 /// ParseIntelMemOperand - Parse intel style memory operand.
693 X86Operand *X86AsmParser::ParseIntelMemOperand() {
694 const AsmToken &Tok = Parser.getTok();
695 SMLoc Start = Parser.getTok().getLoc(), End;
698 unsigned Size = getIntelMemOperandSize(Tok.getString());
701 assert (Tok.getString() == "PTR" && "Unexpected token!");
705 if (getLexer().is(AsmToken::LBrac))
706 return ParseIntelBracExpression(SegReg, Size);
708 if (!ParseRegister(SegReg, Start, End)) {
709 // Handel SegReg : [ ... ]
710 if (getLexer().isNot(AsmToken::Colon))
711 return ErrorOperand(Start, "Expected ':' token!");
712 Parser.Lex(); // Eat :
713 if (getLexer().isNot(AsmToken::LBrac))
714 return ErrorOperand(Start, "Expected '[' token!");
715 return ParseIntelBracExpression(SegReg, Size);
718 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
719 if (getParser().ParseExpression(Disp, End)) return 0;
720 return X86Operand::CreateMem(Disp, Start, End, Size);
723 X86Operand *X86AsmParser::ParseIntelOperand() {
724 SMLoc Start = Parser.getTok().getLoc(), End;
727 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Real) ||
728 getLexer().is(AsmToken::Minus)) {
730 if (!getParser().ParseExpression(Val, End)) {
731 End = Parser.getTok().getLoc();
732 return X86Operand::CreateImm(Val, Start, End);
738 if (!ParseRegister(RegNo, Start, End)) {
739 End = Parser.getTok().getLoc();
740 return X86Operand::CreateReg(RegNo, Start, End);
744 return ParseIntelMemOperand();
747 X86Operand *X86AsmParser::ParseATTOperand() {
748 switch (getLexer().getKind()) {
750 // Parse a memory operand with no segment register.
751 return ParseMemOperand(0, Parser.getTok().getLoc());
752 case AsmToken::Percent: {
753 // Read the register.
756 if (ParseRegister(RegNo, Start, End)) return 0;
757 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
758 Error(Start, "%eiz and %riz can only be used as index registers",
759 SMRange(Start, End));
763 // If this is a segment register followed by a ':', then this is the start
764 // of a memory reference, otherwise this is a normal register reference.
765 if (getLexer().isNot(AsmToken::Colon))
766 return X86Operand::CreateReg(RegNo, Start, End);
769 getParser().Lex(); // Eat the colon.
770 return ParseMemOperand(RegNo, Start);
772 case AsmToken::Dollar: {
774 SMLoc Start = Parser.getTok().getLoc(), End;
777 if (getParser().ParseExpression(Val, End))
779 return X86Operand::CreateImm(Val, Start, End);
784 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
785 /// has already been parsed if present.
786 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
788 // We have to disambiguate a parenthesized expression "(4+5)" from the start
789 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
790 // only way to do this without lookahead is to eat the '(' and see what is
792 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
793 if (getLexer().isNot(AsmToken::LParen)) {
795 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
797 // After parsing the base expression we could either have a parenthesized
798 // memory address or not. If not, return now. If so, eat the (.
799 if (getLexer().isNot(AsmToken::LParen)) {
800 // Unless we have a segment register, treat this as an immediate.
802 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
803 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
809 // Okay, we have a '('. We don't know if this is an expression or not, but
810 // so we have to eat the ( to see beyond it.
811 SMLoc LParenLoc = Parser.getTok().getLoc();
812 Parser.Lex(); // Eat the '('.
814 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
815 // Nothing to do here, fall into the code below with the '(' part of the
816 // memory operand consumed.
820 // It must be an parenthesized expression, parse it now.
821 if (getParser().ParseParenExpression(Disp, ExprEnd))
824 // After parsing the base expression we could either have a parenthesized
825 // memory address or not. If not, return now. If so, eat the (.
826 if (getLexer().isNot(AsmToken::LParen)) {
827 // Unless we have a segment register, treat this as an immediate.
829 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
830 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
838 // If we reached here, then we just ate the ( of the memory operand. Process
839 // the rest of the memory operand.
840 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
843 if (getLexer().is(AsmToken::Percent)) {
844 SMLoc StartLoc, EndLoc;
845 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
846 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
847 Error(StartLoc, "eiz and riz can only be used as index registers",
848 SMRange(StartLoc, EndLoc));
853 if (getLexer().is(AsmToken::Comma)) {
854 Parser.Lex(); // Eat the comma.
855 IndexLoc = Parser.getTok().getLoc();
857 // Following the comma we should have either an index register, or a scale
858 // value. We don't support the later form, but we want to parse it
861 // Not that even though it would be completely consistent to support syntax
862 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
863 if (getLexer().is(AsmToken::Percent)) {
865 if (ParseRegister(IndexReg, L, L)) return 0;
867 if (getLexer().isNot(AsmToken::RParen)) {
868 // Parse the scale amount:
869 // ::= ',' [scale-expression]
870 if (getLexer().isNot(AsmToken::Comma)) {
871 Error(Parser.getTok().getLoc(),
872 "expected comma in scale expression");
875 Parser.Lex(); // Eat the comma.
877 if (getLexer().isNot(AsmToken::RParen)) {
878 SMLoc Loc = Parser.getTok().getLoc();
881 if (getParser().ParseAbsoluteExpression(ScaleVal)){
882 Error(Loc, "expected scale expression");
886 // Validate the scale amount.
887 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
888 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
891 Scale = (unsigned)ScaleVal;
894 } else if (getLexer().isNot(AsmToken::RParen)) {
895 // A scale amount without an index is ignored.
897 SMLoc Loc = Parser.getTok().getLoc();
900 if (getParser().ParseAbsoluteExpression(Value))
904 Warning(Loc, "scale factor without index register is ignored");
909 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
910 if (getLexer().isNot(AsmToken::RParen)) {
911 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
914 SMLoc MemEnd = Parser.getTok().getLoc();
915 Parser.Lex(); // Eat the ')'.
917 // If we have both a base register and an index register make sure they are
918 // both 64-bit or 32-bit registers.
919 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
920 if (BaseReg != 0 && IndexReg != 0) {
921 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
922 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
923 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
924 IndexReg != X86::RIZ) {
925 Error(IndexLoc, "index register is 32-bit, but base register is 64-bit");
928 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
929 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
930 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
931 IndexReg != X86::EIZ){
932 Error(IndexLoc, "index register is 64-bit, but base register is 32-bit");
937 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
942 ParseInstruction(StringRef Name, SMLoc NameLoc,
943 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
944 StringRef PatchedName = Name;
946 // FIXME: Hack to recognize setneb as setne.
947 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
948 PatchedName != "setb" && PatchedName != "setnb")
949 PatchedName = PatchedName.substr(0, Name.size()-1);
951 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
952 const MCExpr *ExtraImmOp = 0;
953 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
954 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
955 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
956 bool IsVCMP = PatchedName[0] == 'v';
957 unsigned SSECCIdx = IsVCMP ? 4 : 3;
958 unsigned SSEComparisonCode = StringSwitch<unsigned>(
959 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
968 /* AVX only from here */
973 .Case("neq_oq", 0x0C)
980 .Case("unord_s", 0x13)
981 .Case("neq_us", 0x14)
982 .Case("nlt_uq", 0x15)
983 .Case("nle_uq", 0x16)
986 .Case("nge_uq", 0x19)
987 .Case("ngt_uq", 0x1A)
988 .Case("false_os", 0x1B)
989 .Case("neq_os", 0x1C)
992 .Case("true_us", 0x1F)
994 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
995 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
996 getParser().getContext());
997 if (PatchedName.endswith("ss")) {
998 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
999 } else if (PatchedName.endswith("sd")) {
1000 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
1001 } else if (PatchedName.endswith("ps")) {
1002 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1004 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1005 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1010 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1012 if (ExtraImmOp && !isParsingIntelSyntax())
1013 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1015 // Determine whether this is an instruction prefix.
1017 Name == "lock" || Name == "rep" ||
1018 Name == "repe" || Name == "repz" ||
1019 Name == "repne" || Name == "repnz" ||
1020 Name == "rex64" || Name == "data16";
1023 // This does the actual operand parsing. Don't parse any more if we have a
1024 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1025 // just want to parse the "lock" as the first instruction and the "incl" as
1027 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1029 // Parse '*' modifier.
1030 if (getLexer().is(AsmToken::Star)) {
1031 SMLoc Loc = Parser.getTok().getLoc();
1032 Operands.push_back(X86Operand::CreateToken("*", Loc));
1033 Parser.Lex(); // Eat the star.
1036 // Read the first operand.
1037 if (X86Operand *Op = ParseOperand())
1038 Operands.push_back(Op);
1040 Parser.EatToEndOfStatement();
1044 while (getLexer().is(AsmToken::Comma)) {
1045 Parser.Lex(); // Eat the comma.
1047 // Parse and remember the operand.
1048 if (X86Operand *Op = ParseOperand())
1049 Operands.push_back(Op);
1051 Parser.EatToEndOfStatement();
1056 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1057 SMLoc Loc = getLexer().getLoc();
1058 Parser.EatToEndOfStatement();
1059 return Error(Loc, "unexpected token in argument list");
1063 if (getLexer().is(AsmToken::EndOfStatement))
1064 Parser.Lex(); // Consume the EndOfStatement
1065 else if (isPrefix && getLexer().is(AsmToken::Slash))
1066 Parser.Lex(); // Consume the prefix separator Slash
1068 if (ExtraImmOp && isParsingIntelSyntax())
1069 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1071 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
1072 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
1073 // documented form in various unofficial manuals, so a lot of code uses it.
1074 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
1075 Operands.size() == 3) {
1076 X86Operand &Op = *(X86Operand*)Operands.back();
1077 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1078 isa<MCConstantExpr>(Op.Mem.Disp) &&
1079 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1080 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1081 SMLoc Loc = Op.getEndLoc();
1082 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1086 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
1087 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
1088 Operands.size() == 3) {
1089 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1090 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1091 isa<MCConstantExpr>(Op.Mem.Disp) &&
1092 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1093 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1094 SMLoc Loc = Op.getEndLoc();
1095 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1099 // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
1100 if (Name.startswith("ins") && Operands.size() == 3 &&
1101 (Name == "insb" || Name == "insw" || Name == "insl")) {
1102 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1103 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1104 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1105 Operands.pop_back();
1106 Operands.pop_back();
1112 // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
1113 if (Name.startswith("outs") && Operands.size() == 3 &&
1114 (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
1115 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1116 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1117 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1118 Operands.pop_back();
1119 Operands.pop_back();
1125 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
1126 if (Name.startswith("movs") && Operands.size() == 3 &&
1127 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
1128 (is64BitMode() && Name == "movsq"))) {
1129 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1130 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1131 if (isSrcOp(Op) && isDstOp(Op2)) {
1132 Operands.pop_back();
1133 Operands.pop_back();
1138 // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
1139 if (Name.startswith("lods") && Operands.size() == 3 &&
1140 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
1141 Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
1142 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1143 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1144 if (isSrcOp(*Op1) && Op2->isReg()) {
1146 unsigned reg = Op2->getReg();
1147 bool isLods = Name == "lods";
1148 if (reg == X86::AL && (isLods || Name == "lodsb"))
1150 else if (reg == X86::AX && (isLods || Name == "lodsw"))
1152 else if (reg == X86::EAX && (isLods || Name == "lodsl"))
1154 else if (reg == X86::RAX && (isLods || Name == "lodsq"))
1159 Operands.pop_back();
1160 Operands.pop_back();
1164 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1168 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
1169 if (Name.startswith("stos") && Operands.size() == 3 &&
1170 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
1171 Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
1172 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1173 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1174 if (isDstOp(*Op2) && Op1->isReg()) {
1176 unsigned reg = Op1->getReg();
1177 bool isStos = Name == "stos";
1178 if (reg == X86::AL && (isStos || Name == "stosb"))
1180 else if (reg == X86::AX && (isStos || Name == "stosw"))
1182 else if (reg == X86::EAX && (isStos || Name == "stosl"))
1184 else if (reg == X86::RAX && (isStos || Name == "stosq"))
1189 Operands.pop_back();
1190 Operands.pop_back();
1194 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1199 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
1201 if ((Name.startswith("shr") || Name.startswith("sar") ||
1202 Name.startswith("shl") || Name.startswith("sal") ||
1203 Name.startswith("rcl") || Name.startswith("rcr") ||
1204 Name.startswith("rol") || Name.startswith("ror")) &&
1205 Operands.size() == 3) {
1206 if (isParsingIntelSyntax()) {
1208 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
1209 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1210 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1212 Operands.pop_back();
1215 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1216 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1217 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1219 Operands.erase(Operands.begin() + 1);
1224 // Transforms "int $3" into "int3" as a size optimization. We can't write an
1225 // instalias with an immediate operand yet.
1226 if (Name == "int" && Operands.size() == 2) {
1227 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1228 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1229 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
1231 Operands.erase(Operands.begin() + 1);
1232 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
1240 processInstruction(MCInst &Inst,
1241 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
1242 switch (Inst.getOpcode()) {
1243 default: return false;
1244 case X86::AND16i16: {
1245 if (!Inst.getOperand(0).isImm() ||
1246 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1250 TmpInst.setOpcode(X86::AND16ri8);
1251 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1252 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1253 TmpInst.addOperand(Inst.getOperand(0));
1257 case X86::AND32i32: {
1258 if (!Inst.getOperand(0).isImm() ||
1259 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1263 TmpInst.setOpcode(X86::AND32ri8);
1264 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1265 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1266 TmpInst.addOperand(Inst.getOperand(0));
1270 case X86::AND64i32: {
1271 if (!Inst.getOperand(0).isImm() ||
1272 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1276 TmpInst.setOpcode(X86::AND64ri8);
1277 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1278 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1279 TmpInst.addOperand(Inst.getOperand(0));
1283 case X86::XOR16i16: {
1284 if (!Inst.getOperand(0).isImm() ||
1285 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1289 TmpInst.setOpcode(X86::XOR16ri8);
1290 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1291 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1292 TmpInst.addOperand(Inst.getOperand(0));
1296 case X86::XOR32i32: {
1297 if (!Inst.getOperand(0).isImm() ||
1298 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1302 TmpInst.setOpcode(X86::XOR32ri8);
1303 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1304 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1305 TmpInst.addOperand(Inst.getOperand(0));
1309 case X86::XOR64i32: {
1310 if (!Inst.getOperand(0).isImm() ||
1311 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1315 TmpInst.setOpcode(X86::XOR64ri8);
1316 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1317 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1318 TmpInst.addOperand(Inst.getOperand(0));
1322 case X86::OR16i16: {
1323 if (!Inst.getOperand(0).isImm() ||
1324 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1328 TmpInst.setOpcode(X86::OR16ri8);
1329 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1330 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1331 TmpInst.addOperand(Inst.getOperand(0));
1335 case X86::OR32i32: {
1336 if (!Inst.getOperand(0).isImm() ||
1337 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1341 TmpInst.setOpcode(X86::OR32ri8);
1342 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1343 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1344 TmpInst.addOperand(Inst.getOperand(0));
1348 case X86::OR64i32: {
1349 if (!Inst.getOperand(0).isImm() ||
1350 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1354 TmpInst.setOpcode(X86::OR64ri8);
1355 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1356 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1357 TmpInst.addOperand(Inst.getOperand(0));
1361 case X86::CMP16i16: {
1362 if (!Inst.getOperand(0).isImm() ||
1363 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1367 TmpInst.setOpcode(X86::CMP16ri8);
1368 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1369 TmpInst.addOperand(Inst.getOperand(0));
1373 case X86::CMP32i32: {
1374 if (!Inst.getOperand(0).isImm() ||
1375 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1379 TmpInst.setOpcode(X86::CMP32ri8);
1380 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1381 TmpInst.addOperand(Inst.getOperand(0));
1385 case X86::CMP64i32: {
1386 if (!Inst.getOperand(0).isImm() ||
1387 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1391 TmpInst.setOpcode(X86::CMP64ri8);
1392 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1393 TmpInst.addOperand(Inst.getOperand(0));
1397 case X86::ADD16i16: {
1398 if (!Inst.getOperand(0).isImm() ||
1399 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1403 TmpInst.setOpcode(X86::ADD16ri8);
1404 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1405 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1406 TmpInst.addOperand(Inst.getOperand(0));
1410 case X86::ADD32i32: {
1411 if (!Inst.getOperand(0).isImm() ||
1412 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1416 TmpInst.setOpcode(X86::ADD32ri8);
1417 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1418 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1419 TmpInst.addOperand(Inst.getOperand(0));
1423 case X86::ADD64i32: {
1424 if (!Inst.getOperand(0).isImm() ||
1425 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1429 TmpInst.setOpcode(X86::ADD64ri8);
1430 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1431 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1432 TmpInst.addOperand(Inst.getOperand(0));
1436 case X86::SUB16i16: {
1437 if (!Inst.getOperand(0).isImm() ||
1438 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1442 TmpInst.setOpcode(X86::SUB16ri8);
1443 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1444 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1445 TmpInst.addOperand(Inst.getOperand(0));
1449 case X86::SUB32i32: {
1450 if (!Inst.getOperand(0).isImm() ||
1451 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1455 TmpInst.setOpcode(X86::SUB32ri8);
1456 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1457 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1458 TmpInst.addOperand(Inst.getOperand(0));
1462 case X86::SUB64i32: {
1463 if (!Inst.getOperand(0).isImm() ||
1464 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1468 TmpInst.setOpcode(X86::SUB64ri8);
1469 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1470 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1471 TmpInst.addOperand(Inst.getOperand(0));
1479 MatchAndEmitInstruction(SMLoc IDLoc,
1480 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1482 assert(!Operands.empty() && "Unexpect empty operand list!");
1483 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1484 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1486 // First, handle aliases that expand to multiple instructions.
1487 // FIXME: This should be replaced with a real .td file alias mechanism.
1488 // Also, MatchInstructionImpl should do actually *do* the EmitInstruction
1490 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
1491 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
1492 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
1493 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
1495 Inst.setOpcode(X86::WAIT);
1497 Out.EmitInstruction(Inst);
1500 StringSwitch<const char*>(Op->getToken())
1501 .Case("finit", "fninit")
1502 .Case("fsave", "fnsave")
1503 .Case("fstcw", "fnstcw")
1504 .Case("fstcww", "fnstcw")
1505 .Case("fstenv", "fnstenv")
1506 .Case("fstsw", "fnstsw")
1507 .Case("fstsww", "fnstsw")
1508 .Case("fclex", "fnclex")
1510 assert(Repl && "Unknown wait-prefixed instruction");
1512 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
1515 bool WasOriginallyInvalidOperand = false;
1516 unsigned OrigErrorInfo;
1519 // First, try a direct match.
1520 switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo,
1521 isParsingIntelSyntax())) {
1524 // Some instructions need post-processing to, for example, tweak which
1525 // encoding is selected. Loop on it while changes happen so the
1526 // individual transformations can chain off each other.
1527 while (processInstruction(Inst, Operands))
1531 Out.EmitInstruction(Inst);
1533 case Match_MissingFeature:
1534 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1536 case Match_ConversionFail:
1537 return Error(IDLoc, "unable to convert operands to instruction");
1538 case Match_InvalidOperand:
1539 WasOriginallyInvalidOperand = true;
1541 case Match_MnemonicFail:
1545 // FIXME: Ideally, we would only attempt suffix matches for things which are
1546 // valid prefixes, and we could just infer the right unambiguous
1547 // type. However, that requires substantially more matcher support than the
1550 // Change the operand to point to a temporary token.
1551 StringRef Base = Op->getToken();
1552 SmallString<16> Tmp;
1555 Op->setTokenValue(Tmp.str());
1557 // If this instruction starts with an 'f', then it is a floating point stack
1558 // instruction. These come in up to three forms for 32-bit, 64-bit, and
1559 // 80-bit floating point, which use the suffixes s,l,t respectively.
1561 // Otherwise, we assume that this may be an integer instruction, which comes
1562 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
1563 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
1565 // Check for the various suffix matches.
1566 Tmp[Base.size()] = Suffixes[0];
1567 unsigned ErrorInfoIgnore;
1568 unsigned Match1, Match2, Match3, Match4;
1570 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1571 Tmp[Base.size()] = Suffixes[1];
1572 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1573 Tmp[Base.size()] = Suffixes[2];
1574 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1575 Tmp[Base.size()] = Suffixes[3];
1576 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1578 // Restore the old token.
1579 Op->setTokenValue(Base);
1581 // If exactly one matched, then we treat that as a successful match (and the
1582 // instruction will already have been filled in correctly, since the failing
1583 // matches won't have modified it).
1584 unsigned NumSuccessfulMatches =
1585 (Match1 == Match_Success) + (Match2 == Match_Success) +
1586 (Match3 == Match_Success) + (Match4 == Match_Success);
1587 if (NumSuccessfulMatches == 1) {
1589 Out.EmitInstruction(Inst);
1593 // Otherwise, the match failed, try to produce a decent error message.
1595 // If we had multiple suffix matches, then identify this as an ambiguous
1597 if (NumSuccessfulMatches > 1) {
1599 unsigned NumMatches = 0;
1600 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
1601 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
1602 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
1603 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
1605 SmallString<126> Msg;
1606 raw_svector_ostream OS(Msg);
1607 OS << "ambiguous instructions require an explicit suffix (could be ";
1608 for (unsigned i = 0; i != NumMatches; ++i) {
1611 if (i + 1 == NumMatches)
1613 OS << "'" << Base << MatchChars[i] << "'";
1616 Error(IDLoc, OS.str());
1620 // Okay, we know that none of the variants matched successfully.
1622 // If all of the instructions reported an invalid mnemonic, then the original
1623 // mnemonic was invalid.
1624 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
1625 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
1626 if (!WasOriginallyInvalidOperand) {
1627 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
1631 // Recover location info for the operand if we know which was the problem.
1632 if (OrigErrorInfo != ~0U) {
1633 if (OrigErrorInfo >= Operands.size())
1634 return Error(IDLoc, "too few operands for instruction");
1636 X86Operand *Operand = (X86Operand*)Operands[OrigErrorInfo];
1637 if (Operand->getStartLoc().isValid()) {
1638 SMRange OperandRange = Operand->getLocRange();
1639 return Error(Operand->getStartLoc(), "invalid operand for instruction",
1644 return Error(IDLoc, "invalid operand for instruction");
1647 // If one instruction matched with a missing feature, report this as a
1649 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
1650 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
1651 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1655 // If one instruction matched with an invalid operand, report this as an
1657 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
1658 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
1659 Error(IDLoc, "invalid operand for instruction");
1663 // If all of these were an outright failure, report it in a useless way.
1664 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
1669 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
1670 StringRef IDVal = DirectiveID.getIdentifier();
1671 if (IDVal == ".word")
1672 return ParseDirectiveWord(2, DirectiveID.getLoc());
1673 else if (IDVal.startswith(".code"))
1674 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
1675 else if (IDVal.startswith(".intel_syntax")) {
1676 getParser().setAssemblerDialect(1);
1677 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1678 if(Parser.getTok().getString() == "noprefix") {
1679 // FIXME : Handle noprefix
1689 /// ParseDirectiveWord
1690 /// ::= .word [ expression (, expression)* ]
1691 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1692 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1694 const MCExpr *Value;
1695 if (getParser().ParseExpression(Value))
1698 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1700 if (getLexer().is(AsmToken::EndOfStatement))
1703 // FIXME: Improve diagnostic.
1704 if (getLexer().isNot(AsmToken::Comma))
1705 return Error(L, "unexpected token in directive");
1714 /// ParseDirectiveCode
1715 /// ::= .code32 | .code64
1716 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
1717 if (IDVal == ".code32") {
1719 if (is64BitMode()) {
1721 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1723 } else if (IDVal == ".code64") {
1725 if (!is64BitMode()) {
1727 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
1730 return Error(L, "unexpected directive " + IDVal);
1737 extern "C" void LLVMInitializeX86AsmLexer();
1739 // Force static initialization.
1740 extern "C" void LLVMInitializeX86AsmParser() {
1741 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
1742 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
1743 LLVMInitializeX86AsmLexer();
1746 #define GET_REGISTER_MATCHER
1747 #define GET_MATCHER_IMPLEMENTATION
1748 #include "X86GenAsmMatcher.inc"