1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/ADT/APFloat.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/ADT/Twine.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
37 static const char OpPrecedence[] = {
50 class X86AsmParser : public MCTargetAsmParser {
53 ParseInstructionInfo *InstInfo;
55 SMLoc consumeToken() {
56 SMLoc Result = Parser.getTok().getLoc();
61 enum InfixCalculatorTok {
74 class InfixCalculator {
75 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
76 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
77 SmallVector<ICToken, 4> PostfixStack;
80 int64_t popOperand() {
81 assert (!PostfixStack.empty() && "Poped an empty stack!");
82 ICToken Op = PostfixStack.pop_back_val();
83 assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
84 && "Expected and immediate or register!");
87 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
88 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
89 "Unexpected operand!");
90 PostfixStack.push_back(std::make_pair(Op, Val));
93 void popOperator() { InfixOperatorStack.pop_back(); }
94 void pushOperator(InfixCalculatorTok Op) {
95 // Push the new operator if the stack is empty.
96 if (InfixOperatorStack.empty()) {
97 InfixOperatorStack.push_back(Op);
101 // Push the new operator if it has a higher precedence than the operator
102 // on the top of the stack or the operator on the top of the stack is a
104 unsigned Idx = InfixOperatorStack.size() - 1;
105 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
106 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
107 InfixOperatorStack.push_back(Op);
111 // The operator on the top of the stack has higher precedence than the
113 unsigned ParenCount = 0;
115 // Nothing to process.
116 if (InfixOperatorStack.empty())
119 Idx = InfixOperatorStack.size() - 1;
120 StackOp = InfixOperatorStack[Idx];
121 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
124 // If we have an even parentheses count and we see a left parentheses,
125 // then stop processing.
126 if (!ParenCount && StackOp == IC_LPAREN)
129 if (StackOp == IC_RPAREN) {
131 InfixOperatorStack.pop_back();
132 } else if (StackOp == IC_LPAREN) {
134 InfixOperatorStack.pop_back();
136 InfixOperatorStack.pop_back();
137 PostfixStack.push_back(std::make_pair(StackOp, 0));
140 // Push the new operator.
141 InfixOperatorStack.push_back(Op);
144 // Push any remaining operators onto the postfix stack.
145 while (!InfixOperatorStack.empty()) {
146 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
147 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
148 PostfixStack.push_back(std::make_pair(StackOp, 0));
151 if (PostfixStack.empty())
154 SmallVector<ICToken, 16> OperandStack;
155 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
156 ICToken Op = PostfixStack[i];
157 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
158 OperandStack.push_back(Op);
160 assert (OperandStack.size() > 1 && "Too few operands.");
162 ICToken Op2 = OperandStack.pop_back_val();
163 ICToken Op1 = OperandStack.pop_back_val();
166 report_fatal_error("Unexpected operator!");
169 Val = Op1.second + Op2.second;
170 OperandStack.push_back(std::make_pair(IC_IMM, Val));
173 Val = Op1.second - Op2.second;
174 OperandStack.push_back(std::make_pair(IC_IMM, Val));
177 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
178 "Multiply operation with an immediate and a register!");
179 Val = Op1.second * Op2.second;
180 OperandStack.push_back(std::make_pair(IC_IMM, Val));
183 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
184 "Divide operation with an immediate and a register!");
185 assert (Op2.second != 0 && "Division by zero!");
186 Val = Op1.second / Op2.second;
187 OperandStack.push_back(std::make_pair(IC_IMM, Val));
190 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
191 "Or operation with an immediate and a register!");
192 Val = Op1.second | Op2.second;
193 OperandStack.push_back(std::make_pair(IC_IMM, Val));
196 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
197 "And operation with an immediate and a register!");
198 Val = Op1.second & Op2.second;
199 OperandStack.push_back(std::make_pair(IC_IMM, Val));
204 assert (OperandStack.size() == 1 && "Expected a single result.");
205 return OperandStack.pop_back_val().second;
209 enum IntelExprState {
226 class IntelExprStateMachine {
227 IntelExprState State, PrevState;
228 unsigned BaseReg, IndexReg, TmpReg, Scale;
232 bool StopOnLBrac, AddImmPrefix;
234 InlineAsmIdentifierInfo Info;
236 IntelExprStateMachine(int64_t imm, bool stoponlbrac, bool addimmprefix) :
237 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
238 Scale(1), Imm(imm), Sym(0), StopOnLBrac(stoponlbrac),
239 AddImmPrefix(addimmprefix) { Info.clear(); }
241 unsigned getBaseReg() { return BaseReg; }
242 unsigned getIndexReg() { return IndexReg; }
243 unsigned getScale() { return Scale; }
244 const MCExpr *getSym() { return Sym; }
245 StringRef getSymName() { return SymName; }
246 int64_t getImm() { return Imm + IC.execute(); }
247 bool isValidEndState() {
248 return State == IES_RBRAC || State == IES_INTEGER;
250 bool getStopOnLBrac() { return StopOnLBrac; }
251 bool getAddImmPrefix() { return AddImmPrefix; }
252 bool hadError() { return State == IES_ERROR; }
254 InlineAsmIdentifierInfo &getIdentifierInfo() {
259 IntelExprState CurrState = State;
268 IC.pushOperator(IC_OR);
271 PrevState = CurrState;
274 IntelExprState CurrState = State;
283 IC.pushOperator(IC_AND);
286 PrevState = CurrState;
289 IntelExprState CurrState = State;
298 IC.pushOperator(IC_PLUS);
299 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
300 // If we already have a BaseReg, then assume this is the IndexReg with
305 assert (!IndexReg && "BaseReg/IndexReg already set!");
312 PrevState = CurrState;
315 IntelExprState CurrState = State;
330 // Only push the minus operator if it is not a unary operator.
331 if (!(CurrState == IES_PLUS || CurrState == IES_MINUS ||
332 CurrState == IES_MULTIPLY || CurrState == IES_DIVIDE ||
333 CurrState == IES_LPAREN || CurrState == IES_LBRAC))
334 IC.pushOperator(IC_MINUS);
335 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
336 // If we already have a BaseReg, then assume this is the IndexReg with
341 assert (!IndexReg && "BaseReg/IndexReg already set!");
348 PrevState = CurrState;
350 void onRegister(unsigned Reg) {
351 IntelExprState CurrState = State;
358 State = IES_REGISTER;
360 IC.pushOperand(IC_REGISTER);
363 // Index Register - Scale * Register
364 if (PrevState == IES_INTEGER) {
365 assert (!IndexReg && "IndexReg already set!");
366 State = IES_REGISTER;
368 // Get the scale and replace the 'Scale * Register' with '0'.
369 Scale = IC.popOperand();
370 IC.pushOperand(IC_IMM);
377 PrevState = CurrState;
379 void onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName) {
389 SymName = SymRefName;
390 IC.pushOperand(IC_IMM);
394 bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
395 IntelExprState CurrState = State;
408 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
409 // Index Register - Register * Scale
410 assert (!IndexReg && "IndexReg already set!");
413 if(Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
414 ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
417 // Get the scale and replace the 'Register * Scale' with '0'.
419 } else if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
420 PrevState == IES_OR || PrevState == IES_AND ||
421 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
422 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
423 CurrState == IES_MINUS) {
424 // Unary minus. No need to pop the minus operand because it was never
426 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm.
428 IC.pushOperand(IC_IMM, TmpInt);
432 PrevState = CurrState;
444 State = IES_MULTIPLY;
445 IC.pushOperator(IC_MULTIPLY);
458 IC.pushOperator(IC_DIVIDE);
470 IC.pushOperator(IC_PLUS);
475 IntelExprState CurrState = State;
484 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
485 // If we already have a BaseReg, then assume this is the IndexReg with
490 assert (!IndexReg && "BaseReg/IndexReg already set!");
497 PrevState = CurrState;
500 IntelExprState CurrState = State;
512 // FIXME: We don't handle this type of unary minus, yet.
513 if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
514 PrevState == IES_OR || PrevState == IES_AND ||
515 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
516 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
517 CurrState == IES_MINUS) {
522 IC.pushOperator(IC_LPAREN);
525 PrevState = CurrState;
537 IC.pushOperator(IC_RPAREN);
543 MCAsmParser &getParser() const { return Parser; }
545 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
547 bool Error(SMLoc L, const Twine &Msg,
548 ArrayRef<SMRange> Ranges = None,
549 bool MatchingInlineAsm = false) {
550 if (MatchingInlineAsm) return true;
551 return Parser.Error(L, Msg, Ranges);
554 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
559 X86Operand *DefaultMemSIOperand(SMLoc Loc);
560 X86Operand *DefaultMemDIOperand(SMLoc Loc);
561 X86Operand *ParseOperand();
562 X86Operand *ParseATTOperand();
563 X86Operand *ParseIntelOperand();
564 X86Operand *ParseIntelOffsetOfOperator();
565 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
566 X86Operand *ParseIntelOperator(unsigned OpKind);
567 X86Operand *ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
568 X86Operand *ParseIntelMemOperand(int64_t ImmDisp, SMLoc StartLoc,
570 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
571 X86Operand *ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
572 int64_t ImmDisp, unsigned Size);
573 bool ParseIntelIdentifier(const MCExpr *&Val, StringRef &Identifier,
574 InlineAsmIdentifierInfo &Info,
575 bool IsUnevaluatedOperand, SMLoc &End);
577 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
579 X86Operand *CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
580 unsigned BaseReg, unsigned IndexReg,
581 unsigned Scale, SMLoc Start, SMLoc End,
582 unsigned Size, StringRef Identifier,
583 InlineAsmIdentifierInfo &Info);
585 bool ParseDirectiveWord(unsigned Size, SMLoc L);
586 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
588 bool processInstruction(MCInst &Inst,
589 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
591 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
592 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
593 MCStreamer &Out, unsigned &ErrorInfo,
594 bool MatchingInlineAsm);
596 /// doSrcDstMatch - Returns true if operands are matching in their
597 /// word size (%si and %di, %esi and %edi, etc.). Order depends on
598 /// the parsing mode (Intel vs. AT&T).
599 bool doSrcDstMatch(X86Operand &Op1, X86Operand &Op2);
601 bool is64BitMode() const {
602 // FIXME: Can tablegen auto-generate this?
603 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
605 bool is32BitMode() const {
606 // FIXME: Can tablegen auto-generate this?
607 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
609 bool is16BitMode() const {
610 // FIXME: Can tablegen auto-generate this?
611 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
613 void SwitchMode(uint64_t mode) {
614 uint64_t oldMode = STI.getFeatureBits() &
615 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
616 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
617 setAvailableFeatures(FB);
618 assert(mode == (STI.getFeatureBits() &
619 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
622 bool isParsingIntelSyntax() {
623 return getParser().getAssemblerDialect();
626 /// @name Auto-generated Matcher Functions
629 #define GET_ASSEMBLER_HEADER
630 #include "X86GenAsmMatcher.inc"
635 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
636 const MCInstrInfo &MII)
637 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
639 // Initialize the set of available features.
640 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
642 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
644 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
646 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
648 virtual bool ParseDirective(AsmToken DirectiveID);
650 } // end anonymous namespace
652 /// @name Auto-generated Match Functions
655 static unsigned MatchRegisterName(StringRef Name);
659 static bool isImmSExti16i8Value(uint64_t Value) {
660 return (( Value <= 0x000000000000007FULL)||
661 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
662 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
665 static bool isImmSExti32i8Value(uint64_t Value) {
666 return (( Value <= 0x000000000000007FULL)||
667 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
668 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
671 static bool isImmZExtu32u8Value(uint64_t Value) {
672 return (Value <= 0x00000000000000FFULL);
675 static bool isImmSExti64i8Value(uint64_t Value) {
676 return (( Value <= 0x000000000000007FULL)||
677 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
680 static bool isImmSExti64i32Value(uint64_t Value) {
681 return (( Value <= 0x000000007FFFFFFFULL)||
682 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
686 /// X86Operand - Instances of this class represent a parsed X86 machine
688 struct X86Operand : public MCParsedAsmOperand {
696 SMLoc StartLoc, EndLoc;
731 X86Operand(KindTy K, SMLoc Start, SMLoc End)
732 : Kind(K), StartLoc(Start), EndLoc(End) {}
734 StringRef getSymName() { return SymName; }
735 void *getOpDecl() { return OpDecl; }
737 /// getStartLoc - Get the location of the first token of this operand.
738 SMLoc getStartLoc() const { return StartLoc; }
739 /// getEndLoc - Get the location of the last token of this operand.
740 SMLoc getEndLoc() const { return EndLoc; }
741 /// getLocRange - Get the range between the first and last token of this
743 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
744 /// getOffsetOfLoc - Get the location of the offset operator.
745 SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
747 virtual void print(raw_ostream &OS) const {}
749 StringRef getToken() const {
750 assert(Kind == Token && "Invalid access!");
751 return StringRef(Tok.Data, Tok.Length);
753 void setTokenValue(StringRef Value) {
754 assert(Kind == Token && "Invalid access!");
755 Tok.Data = Value.data();
756 Tok.Length = Value.size();
759 unsigned getReg() const {
760 assert(Kind == Register && "Invalid access!");
764 const MCExpr *getImm() const {
765 assert(Kind == Immediate && "Invalid access!");
769 const MCExpr *getMemDisp() const {
770 assert(Kind == Memory && "Invalid access!");
773 unsigned getMemSegReg() const {
774 assert(Kind == Memory && "Invalid access!");
777 unsigned getMemBaseReg() const {
778 assert(Kind == Memory && "Invalid access!");
781 unsigned getMemIndexReg() const {
782 assert(Kind == Memory && "Invalid access!");
785 unsigned getMemScale() const {
786 assert(Kind == Memory && "Invalid access!");
790 bool isToken() const {return Kind == Token; }
792 bool isImm() const { return Kind == Immediate; }
794 bool isImmSExti16i8() const {
798 // If this isn't a constant expr, just assume it fits and let relaxation
800 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 // Otherwise, check the value is in a range that makes sense for this
806 return isImmSExti16i8Value(CE->getValue());
808 bool isImmSExti32i8() const {
812 // If this isn't a constant expr, just assume it fits and let relaxation
814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818 // Otherwise, check the value is in a range that makes sense for this
820 return isImmSExti32i8Value(CE->getValue());
822 bool isImmZExtu32u8() const {
826 // If this isn't a constant expr, just assume it fits and let relaxation
828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832 // Otherwise, check the value is in a range that makes sense for this
834 return isImmZExtu32u8Value(CE->getValue());
836 bool isImmSExti64i8() const {
840 // If this isn't a constant expr, just assume it fits and let relaxation
842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846 // Otherwise, check the value is in a range that makes sense for this
848 return isImmSExti64i8Value(CE->getValue());
850 bool isImmSExti64i32() const {
854 // If this isn't a constant expr, just assume it fits and let relaxation
856 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860 // Otherwise, check the value is in a range that makes sense for this
862 return isImmSExti64i32Value(CE->getValue());
865 bool isOffsetOf() const {
866 return OffsetOfLoc.getPointer();
869 bool needAddressOf() const {
873 bool isMem() const { return Kind == Memory; }
874 bool isMem8() const {
875 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
877 bool isMem16() const {
878 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
880 bool isMem32() const {
881 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
883 bool isMem64() const {
884 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
886 bool isMem80() const {
887 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
889 bool isMem128() const {
890 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
892 bool isMem256() const {
893 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
895 bool isMem512() const {
896 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
899 bool isMemVX32() const {
900 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
901 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
903 bool isMemVY32() const {
904 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
905 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
907 bool isMemVX64() const {
908 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
909 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
911 bool isMemVY64() const {
912 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
913 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
915 bool isMemVZ32() const {
916 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
917 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
919 bool isMemVZ64() const {
920 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
921 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
924 bool isAbsMem() const {
925 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
926 !getMemIndexReg() && getMemScale() == 1;
929 bool isSrcIdx() const {
930 return !getMemIndexReg() && getMemScale() == 1 &&
931 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
932 getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
933 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
935 bool isSrcIdx8() const {
936 return isMem8() && isSrcIdx();
938 bool isSrcIdx16() const {
939 return isMem16() && isSrcIdx();
941 bool isSrcIdx32() const {
942 return isMem32() && isSrcIdx();
944 bool isSrcIdx64() const {
945 return isMem64() && isSrcIdx();
948 bool isDstIdx() const {
949 return !getMemIndexReg() && getMemScale() == 1 &&
950 (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
951 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
952 getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
953 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
955 bool isDstIdx8() const {
956 return isMem8() && isDstIdx();
958 bool isDstIdx16() const {
959 return isMem16() && isDstIdx();
961 bool isDstIdx32() const {
962 return isMem32() && isDstIdx();
964 bool isDstIdx64() const {
965 return isMem64() && isDstIdx();
968 bool isMemOffs8() const {
969 return Kind == Memory && !getMemBaseReg() &&
970 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 8);
972 bool isMemOffs16() const {
973 return Kind == Memory && !getMemBaseReg() &&
974 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 16);
976 bool isMemOffs32() const {
977 return Kind == Memory && !getMemBaseReg() &&
978 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 32);
980 bool isMemOffs64() const {
981 return Kind == Memory && !getMemBaseReg() &&
982 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 64);
985 bool isReg() const { return Kind == Register; }
987 bool isGR32orGR64() const {
988 return Kind == Register &&
989 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
990 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
993 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
994 // Add as immediates when possible.
995 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
996 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
998 Inst.addOperand(MCOperand::CreateExpr(Expr));
1001 void addRegOperands(MCInst &Inst, unsigned N) const {
1002 assert(N == 1 && "Invalid number of operands!");
1003 Inst.addOperand(MCOperand::CreateReg(getReg()));
1006 static unsigned getGR32FromGR64(unsigned RegNo) {
1008 default: llvm_unreachable("Unexpected register");
1009 case X86::RAX: return X86::EAX;
1010 case X86::RCX: return X86::ECX;
1011 case X86::RDX: return X86::EDX;
1012 case X86::RBX: return X86::EBX;
1013 case X86::RBP: return X86::EBP;
1014 case X86::RSP: return X86::ESP;
1015 case X86::RSI: return X86::ESI;
1016 case X86::RDI: return X86::EDI;
1017 case X86::R8: return X86::R8D;
1018 case X86::R9: return X86::R9D;
1019 case X86::R10: return X86::R10D;
1020 case X86::R11: return X86::R11D;
1021 case X86::R12: return X86::R12D;
1022 case X86::R13: return X86::R13D;
1023 case X86::R14: return X86::R14D;
1024 case X86::R15: return X86::R15D;
1025 case X86::RIP: return X86::EIP;
1029 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
1030 assert(N == 1 && "Invalid number of operands!");
1031 unsigned RegNo = getReg();
1032 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
1033 RegNo = getGR32FromGR64(RegNo);
1034 Inst.addOperand(MCOperand::CreateReg(RegNo));
1037 void addImmOperands(MCInst &Inst, unsigned N) const {
1038 assert(N == 1 && "Invalid number of operands!");
1039 addExpr(Inst, getImm());
1042 void addMemOperands(MCInst &Inst, unsigned N) const {
1043 assert((N == 5) && "Invalid number of operands!");
1044 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1045 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
1046 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
1047 addExpr(Inst, getMemDisp());
1048 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1051 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
1052 assert((N == 1) && "Invalid number of operands!");
1053 // Add as immediates when possible.
1054 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
1055 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1057 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
1060 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
1061 assert((N == 2) && "Invalid number of operands!");
1062 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1063 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1065 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
1066 assert((N == 1) && "Invalid number of operands!");
1067 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1070 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
1071 assert((N == 2) && "Invalid number of operands!");
1072 // Add as immediates when possible.
1073 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
1074 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1076 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
1077 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1080 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
1081 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
1082 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
1083 Res->Tok.Data = Str.data();
1084 Res->Tok.Length = Str.size();
1088 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
1089 bool AddressOf = false,
1090 SMLoc OffsetOfLoc = SMLoc(),
1091 StringRef SymName = StringRef(),
1093 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
1094 Res->Reg.RegNo = RegNo;
1095 Res->AddressOf = AddressOf;
1096 Res->OffsetOfLoc = OffsetOfLoc;
1097 Res->SymName = SymName;
1098 Res->OpDecl = OpDecl;
1102 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
1103 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
1108 /// Create an absolute memory operand.
1109 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
1110 unsigned Size = 0, StringRef SymName = StringRef(),
1112 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
1113 Res->Mem.SegReg = 0;
1114 Res->Mem.Disp = Disp;
1115 Res->Mem.BaseReg = 0;
1116 Res->Mem.IndexReg = 0;
1118 Res->Mem.Size = Size;
1119 Res->SymName = SymName;
1120 Res->OpDecl = OpDecl;
1121 Res->AddressOf = false;
1125 /// Create a generalized memory operand.
1126 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
1127 unsigned BaseReg, unsigned IndexReg,
1128 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
1130 StringRef SymName = StringRef(),
1132 // We should never just have a displacement, that should be parsed as an
1133 // absolute memory operand.
1134 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
1136 // The scale should always be one of {1,2,4,8}.
1137 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
1139 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
1140 Res->Mem.SegReg = SegReg;
1141 Res->Mem.Disp = Disp;
1142 Res->Mem.BaseReg = BaseReg;
1143 Res->Mem.IndexReg = IndexReg;
1144 Res->Mem.Scale = Scale;
1145 Res->Mem.Size = Size;
1146 Res->SymName = SymName;
1147 Res->OpDecl = OpDecl;
1148 Res->AddressOf = false;
1153 } // end anonymous namespace.
1155 bool X86AsmParser::doSrcDstMatch(X86Operand &Op1, X86Operand &Op2)
1157 // Return true and let a normal complaint about bogus operands happen.
1158 if (!Op1.isMem() || !Op2.isMem())
1161 // Actually these might be the other way round if Intel syntax is
1162 // being used. It doesn't matter.
1163 unsigned diReg = Op1.Mem.BaseReg;
1164 unsigned siReg = Op2.Mem.BaseReg;
1166 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(siReg))
1167 return X86MCRegisterClasses[X86::GR16RegClassID].contains(diReg);
1168 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(siReg))
1169 return X86MCRegisterClasses[X86::GR32RegClassID].contains(diReg);
1170 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(siReg))
1171 return X86MCRegisterClasses[X86::GR64RegClassID].contains(diReg);
1172 // Again, return true and let another error happen.
1176 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1177 SMLoc &StartLoc, SMLoc &EndLoc) {
1179 const AsmToken &PercentTok = Parser.getTok();
1180 StartLoc = PercentTok.getLoc();
1182 // If we encounter a %, ignore it. This code handles registers with and
1183 // without the prefix, unprefixed registers can occur in cfi directives.
1184 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1185 Parser.Lex(); // Eat percent token.
1187 const AsmToken &Tok = Parser.getTok();
1188 EndLoc = Tok.getEndLoc();
1190 if (Tok.isNot(AsmToken::Identifier)) {
1191 if (isParsingIntelSyntax()) return true;
1192 return Error(StartLoc, "invalid register name",
1193 SMRange(StartLoc, EndLoc));
1196 RegNo = MatchRegisterName(Tok.getString());
1198 // If the match failed, try the register name as lowercase.
1200 RegNo = MatchRegisterName(Tok.getString().lower());
1202 if (!is64BitMode()) {
1203 // FIXME: This should be done using Requires<Not64BitMode> and
1204 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1206 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1208 if (RegNo == X86::RIZ ||
1209 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1210 X86II::isX86_64NonExtLowByteReg(RegNo) ||
1211 X86II::isX86_64ExtendedReg(RegNo))
1212 return Error(StartLoc, "register %"
1213 + Tok.getString() + " is only available in 64-bit mode",
1214 SMRange(StartLoc, EndLoc));
1217 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1218 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
1220 Parser.Lex(); // Eat 'st'
1222 // Check to see if we have '(4)' after %st.
1223 if (getLexer().isNot(AsmToken::LParen))
1228 const AsmToken &IntTok = Parser.getTok();
1229 if (IntTok.isNot(AsmToken::Integer))
1230 return Error(IntTok.getLoc(), "expected stack index");
1231 switch (IntTok.getIntVal()) {
1232 case 0: RegNo = X86::ST0; break;
1233 case 1: RegNo = X86::ST1; break;
1234 case 2: RegNo = X86::ST2; break;
1235 case 3: RegNo = X86::ST3; break;
1236 case 4: RegNo = X86::ST4; break;
1237 case 5: RegNo = X86::ST5; break;
1238 case 6: RegNo = X86::ST6; break;
1239 case 7: RegNo = X86::ST7; break;
1240 default: return Error(IntTok.getLoc(), "invalid stack index");
1243 if (getParser().Lex().isNot(AsmToken::RParen))
1244 return Error(Parser.getTok().getLoc(), "expected ')'");
1246 EndLoc = Parser.getTok().getEndLoc();
1247 Parser.Lex(); // Eat ')'
1251 EndLoc = Parser.getTok().getEndLoc();
1253 // If this is "db[0-7]", match it as an alias
1255 if (RegNo == 0 && Tok.getString().size() == 3 &&
1256 Tok.getString().startswith("db")) {
1257 switch (Tok.getString()[2]) {
1258 case '0': RegNo = X86::DR0; break;
1259 case '1': RegNo = X86::DR1; break;
1260 case '2': RegNo = X86::DR2; break;
1261 case '3': RegNo = X86::DR3; break;
1262 case '4': RegNo = X86::DR4; break;
1263 case '5': RegNo = X86::DR5; break;
1264 case '6': RegNo = X86::DR6; break;
1265 case '7': RegNo = X86::DR7; break;
1269 EndLoc = Parser.getTok().getEndLoc();
1270 Parser.Lex(); // Eat it.
1276 if (isParsingIntelSyntax()) return true;
1277 return Error(StartLoc, "invalid register name",
1278 SMRange(StartLoc, EndLoc));
1281 Parser.Lex(); // Eat identifier token.
1285 X86Operand *X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1287 is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
1288 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
1289 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
1290 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
1293 X86Operand *X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1295 is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
1296 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
1297 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
1298 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
1301 X86Operand *X86AsmParser::ParseOperand() {
1302 if (isParsingIntelSyntax())
1303 return ParseIntelOperand();
1304 return ParseATTOperand();
1307 /// getIntelMemOperandSize - Return intel memory operand size.
1308 static unsigned getIntelMemOperandSize(StringRef OpStr) {
1309 unsigned Size = StringSwitch<unsigned>(OpStr)
1310 .Cases("BYTE", "byte", 8)
1311 .Cases("WORD", "word", 16)
1312 .Cases("DWORD", "dword", 32)
1313 .Cases("QWORD", "qword", 64)
1314 .Cases("XWORD", "xword", 80)
1315 .Cases("XMMWORD", "xmmword", 128)
1316 .Cases("YMMWORD", "ymmword", 256)
1317 .Cases("ZMMWORD", "zmmword", 512)
1318 .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter
1324 X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
1325 unsigned BaseReg, unsigned IndexReg,
1326 unsigned Scale, SMLoc Start, SMLoc End,
1327 unsigned Size, StringRef Identifier,
1328 InlineAsmIdentifierInfo &Info){
1329 if (isa<MCSymbolRefExpr>(Disp)) {
1330 // If this is not a VarDecl then assume it is a FuncDecl or some other label
1331 // reference. We need an 'r' constraint here, so we need to create register
1332 // operand to ensure proper matching. Just pick a GPR based on the size of
1334 if (!Info.IsVarDecl) {
1336 is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1337 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,
1338 SMLoc(), Identifier, Info.OpDecl);
1341 Size = Info.Type * 8; // Size is in terms of bits in this context.
1343 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_SizeDirective, Start,
1348 // When parsing inline assembly we set the base register to a non-zero value
1349 // if we don't know the actual value at this time. This is necessary to
1350 // get the matching correct in some cases.
1351 BaseReg = BaseReg ? BaseReg : 1;
1352 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1353 End, Size, Identifier, Info.OpDecl);
1357 RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> *AsmRewrites,
1358 StringRef SymName, int64_t ImmDisp,
1359 int64_t FinalImmDisp, SMLoc &BracLoc,
1360 SMLoc &StartInBrac, SMLoc &End) {
1361 // Remove the '[' and ']' from the IR string.
1362 AsmRewrites->push_back(AsmRewrite(AOK_Skip, BracLoc, 1));
1363 AsmRewrites->push_back(AsmRewrite(AOK_Skip, End, 1));
1365 // If ImmDisp is non-zero, then we parsed a displacement before the
1366 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1367 // If ImmDisp doesn't match the displacement computed by the state machine
1368 // then we have an additional displacement in the bracketed expression.
1369 if (ImmDisp != FinalImmDisp) {
1371 // We have an immediate displacement before the bracketed expression.
1372 // Adjust this to match the final immediate displacement.
1374 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1375 E = AsmRewrites->end(); I != E; ++I) {
1376 if ((*I).Loc.getPointer() > BracLoc.getPointer())
1378 if ((*I).Kind == AOK_ImmPrefix || (*I).Kind == AOK_Imm) {
1379 assert (!Found && "ImmDisp already rewritten.");
1380 (*I).Kind = AOK_Imm;
1381 (*I).Len = BracLoc.getPointer() - (*I).Loc.getPointer();
1382 (*I).Val = FinalImmDisp;
1387 assert (Found && "Unable to rewrite ImmDisp.");
1390 // We have a symbolic and an immediate displacement, but no displacement
1391 // before the bracketed expression. Put the immediate displacement
1392 // before the bracketed expression.
1393 AsmRewrites->push_back(AsmRewrite(AOK_Imm, BracLoc, 0, FinalImmDisp));
1396 // Remove all the ImmPrefix rewrites within the brackets.
1397 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1398 E = AsmRewrites->end(); I != E; ++I) {
1399 if ((*I).Loc.getPointer() < StartInBrac.getPointer())
1401 if ((*I).Kind == AOK_ImmPrefix)
1402 (*I).Kind = AOK_Delete;
1404 const char *SymLocPtr = SymName.data();
1405 // Skip everything before the symbol.
1406 if (unsigned Len = SymLocPtr - StartInBrac.getPointer()) {
1407 assert(Len > 0 && "Expected a non-negative length.");
1408 AsmRewrites->push_back(AsmRewrite(AOK_Skip, StartInBrac, Len));
1410 // Skip everything after the symbol.
1411 if (unsigned Len = End.getPointer() - (SymLocPtr + SymName.size())) {
1412 SMLoc Loc = SMLoc::getFromPointer(SymLocPtr + SymName.size());
1413 assert(Len > 0 && "Expected a non-negative length.");
1414 AsmRewrites->push_back(AsmRewrite(AOK_Skip, Loc, Len));
1418 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1419 const AsmToken &Tok = Parser.getTok();
1423 bool UpdateLocLex = true;
1425 // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1426 // identifier. Don't try an parse it as a register.
1427 if (Tok.getString().startswith("."))
1430 // If we're parsing an immediate expression, we don't expect a '['.
1431 if (SM.getStopOnLBrac() && getLexer().getKind() == AsmToken::LBrac)
1434 switch (getLexer().getKind()) {
1436 if (SM.isValidEndState()) {
1440 return Error(Tok.getLoc(), "unknown token in expression");
1442 case AsmToken::EndOfStatement: {
1446 case AsmToken::Identifier: {
1447 // This could be a register or a symbolic displacement.
1450 SMLoc IdentLoc = Tok.getLoc();
1451 StringRef Identifier = Tok.getString();
1452 if(!ParseRegister(TmpReg, IdentLoc, End)) {
1453 SM.onRegister(TmpReg);
1454 UpdateLocLex = false;
1457 if (!isParsingInlineAsm()) {
1458 if (getParser().parsePrimaryExpr(Val, End))
1459 return Error(Tok.getLoc(), "Unexpected identifier!");
1461 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1462 if (ParseIntelIdentifier(Val, Identifier, Info,
1463 /*Unevaluated=*/false, End))
1466 SM.onIdentifierExpr(Val, Identifier);
1467 UpdateLocLex = false;
1470 return Error(Tok.getLoc(), "Unexpected identifier!");
1472 case AsmToken::Integer: {
1474 if (isParsingInlineAsm() && SM.getAddImmPrefix())
1475 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1477 // Look for 'b' or 'f' following an Integer as a directional label
1478 SMLoc Loc = getTok().getLoc();
1479 int64_t IntVal = getTok().getIntVal();
1480 End = consumeToken();
1481 UpdateLocLex = false;
1482 if (getLexer().getKind() == AsmToken::Identifier) {
1483 StringRef IDVal = getTok().getString();
1484 if (IDVal == "f" || IDVal == "b") {
1486 getContext().GetDirectionalLocalSymbol(IntVal,
1487 IDVal == "f" ? 1 : 0);
1488 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1490 MCSymbolRefExpr::Create(Sym, Variant, getContext());
1491 if (IDVal == "b" && Sym->isUndefined())
1492 return Error(Loc, "invalid reference to undefined symbol");
1493 StringRef Identifier = Sym->getName();
1494 SM.onIdentifierExpr(Val, Identifier);
1495 End = consumeToken();
1497 if (SM.onInteger(IntVal, ErrMsg))
1498 return Error(Loc, ErrMsg);
1501 if (SM.onInteger(IntVal, ErrMsg))
1502 return Error(Loc, ErrMsg);
1506 case AsmToken::Plus: SM.onPlus(); break;
1507 case AsmToken::Minus: SM.onMinus(); break;
1508 case AsmToken::Star: SM.onStar(); break;
1509 case AsmToken::Slash: SM.onDivide(); break;
1510 case AsmToken::Pipe: SM.onOr(); break;
1511 case AsmToken::Amp: SM.onAnd(); break;
1512 case AsmToken::LBrac: SM.onLBrac(); break;
1513 case AsmToken::RBrac: SM.onRBrac(); break;
1514 case AsmToken::LParen: SM.onLParen(); break;
1515 case AsmToken::RParen: SM.onRParen(); break;
1518 return Error(Tok.getLoc(), "unknown token in expression");
1520 if (!Done && UpdateLocLex)
1521 End = consumeToken();
1526 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
1529 const AsmToken &Tok = Parser.getTok();
1530 SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
1531 if (getLexer().isNot(AsmToken::LBrac))
1532 return ErrorOperand(BracLoc, "Expected '[' token!");
1533 Parser.Lex(); // Eat '['
1535 SMLoc StartInBrac = Tok.getLoc();
1536 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1537 // may have already parsed an immediate displacement before the bracketed
1539 IntelExprStateMachine SM(ImmDisp, /*StopOnLBrac=*/false, /*AddImmPrefix=*/true);
1540 if (ParseIntelExpression(SM, End))
1544 if (const MCExpr *Sym = SM.getSym()) {
1545 // A symbolic displacement.
1547 if (isParsingInlineAsm())
1548 RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),
1549 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
1552 // An immediate displacement only.
1553 Disp = MCConstantExpr::Create(SM.getImm(), getContext());
1556 // Parse the dot operator (e.g., [ebx].foo.bar).
1557 if (Tok.getString().startswith(".")) {
1558 const MCExpr *NewDisp;
1559 if (ParseIntelDotOperator(Disp, NewDisp))
1562 End = Tok.getEndLoc();
1563 Parser.Lex(); // Eat the field.
1567 int BaseReg = SM.getBaseReg();
1568 int IndexReg = SM.getIndexReg();
1569 int Scale = SM.getScale();
1570 if (!isParsingInlineAsm()) {
1572 if (!BaseReg && !IndexReg) {
1574 return X86Operand::CreateMem(Disp, Start, End, Size);
1576 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
1578 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1582 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1583 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1584 End, Size, SM.getSymName(), Info);
1587 // Inline assembly may use variable names with namespace alias qualifiers.
1588 bool X86AsmParser::ParseIntelIdentifier(const MCExpr *&Val,
1589 StringRef &Identifier,
1590 InlineAsmIdentifierInfo &Info,
1591 bool IsUnevaluatedOperand, SMLoc &End) {
1592 assert (isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1595 StringRef LineBuf(Identifier.data());
1596 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1598 const AsmToken &Tok = Parser.getTok();
1600 // Advance the token stream until the end of the current token is
1601 // after the end of what the frontend claimed.
1602 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1604 End = Tok.getEndLoc();
1607 assert(End.getPointer() <= EndPtr && "frontend claimed part of a token?");
1608 if (End.getPointer() == EndPtr) break;
1611 // Create the symbol reference.
1612 Identifier = LineBuf;
1613 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1614 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1615 Val = MCSymbolRefExpr::Create(Sym, Variant, getParser().getContext());
1619 /// \brief Parse intel style segment override.
1620 X86Operand *X86AsmParser::ParseIntelSegmentOverride(unsigned SegReg,
1623 assert(SegReg != 0 && "Tried to parse a segment override without a segment!");
1624 const AsmToken &Tok = Parser.getTok(); // Eat colon.
1625 if (Tok.isNot(AsmToken::Colon))
1626 return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1627 Parser.Lex(); // Eat ':'
1629 int64_t ImmDisp = 0;
1630 if (getLexer().is(AsmToken::Integer)) {
1631 ImmDisp = Tok.getIntVal();
1632 AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
1634 if (isParsingInlineAsm())
1635 InstInfo->AsmRewrites->push_back(
1636 AsmRewrite(AOK_ImmPrefix, ImmDispToken.getLoc()));
1638 if (getLexer().isNot(AsmToken::LBrac)) {
1639 // An immediate following a 'segment register', 'colon' token sequence can
1640 // be followed by a bracketed expression. If it isn't we know we have our
1641 // final segment override.
1642 const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext());
1643 return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0, /*IndexReg=*/0,
1644 /*Scale=*/1, Start, ImmDispToken.getEndLoc(),
1649 if (getLexer().is(AsmToken::LBrac))
1650 return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1654 if (!isParsingInlineAsm()) {
1655 if (getParser().parsePrimaryExpr(Val, End))
1656 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1658 return X86Operand::CreateMem(Val, Start, End, Size);
1661 InlineAsmIdentifierInfo Info;
1662 StringRef Identifier = Tok.getString();
1663 if (ParseIntelIdentifier(Val, Identifier, Info,
1664 /*Unevaluated=*/false, End))
1666 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1667 /*Scale=*/1, Start, End, Size, Identifier, Info);
1670 /// ParseIntelMemOperand - Parse intel style memory operand.
1671 X86Operand *X86AsmParser::ParseIntelMemOperand(int64_t ImmDisp, SMLoc Start,
1673 const AsmToken &Tok = Parser.getTok();
1676 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1677 if (getLexer().is(AsmToken::LBrac))
1678 return ParseIntelBracExpression(/*SegReg=*/0, Start, ImmDisp, Size);
1681 if (!isParsingInlineAsm()) {
1682 if (getParser().parsePrimaryExpr(Val, End))
1683 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1685 return X86Operand::CreateMem(Val, Start, End, Size);
1688 InlineAsmIdentifierInfo Info;
1689 StringRef Identifier = Tok.getString();
1690 if (ParseIntelIdentifier(Val, Identifier, Info,
1691 /*Unevaluated=*/false, End))
1693 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1694 /*Scale=*/1, Start, End, Size, Identifier, Info);
1697 /// Parse the '.' operator.
1698 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
1699 const MCExpr *&NewDisp) {
1700 const AsmToken &Tok = Parser.getTok();
1701 int64_t OrigDispVal, DotDispVal;
1703 // FIXME: Handle non-constant expressions.
1704 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp))
1705 OrigDispVal = OrigDisp->getValue();
1707 return Error(Tok.getLoc(), "Non-constant offsets are not supported!");
1710 StringRef DotDispStr = Tok.getString().drop_front(1);
1712 // .Imm gets lexed as a real.
1713 if (Tok.is(AsmToken::Real)) {
1715 DotDispStr.getAsInteger(10, DotDisp);
1716 DotDispVal = DotDisp.getZExtValue();
1717 } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1719 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1720 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1722 return Error(Tok.getLoc(), "Unable to lookup field reference!");
1723 DotDispVal = DotDisp;
1725 return Error(Tok.getLoc(), "Unexpected token type!");
1727 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1728 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1729 unsigned Len = DotDispStr.size();
1730 unsigned Val = OrigDispVal + DotDispVal;
1731 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
1735 NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
1739 /// Parse the 'offset' operator. This operator is used to specify the
1740 /// location rather then the content of a variable.
1741 X86Operand *X86AsmParser::ParseIntelOffsetOfOperator() {
1742 const AsmToken &Tok = Parser.getTok();
1743 SMLoc OffsetOfLoc = Tok.getLoc();
1744 Parser.Lex(); // Eat offset.
1747 InlineAsmIdentifierInfo Info;
1748 SMLoc Start = Tok.getLoc(), End;
1749 StringRef Identifier = Tok.getString();
1750 if (ParseIntelIdentifier(Val, Identifier, Info,
1751 /*Unevaluated=*/false, End))
1754 // Don't emit the offset operator.
1755 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
1757 // The offset operator will have an 'r' constraint, thus we need to create
1758 // register operand to ensure proper matching. Just pick a GPR based on
1759 // the size of a pointer.
1761 is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1762 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1763 OffsetOfLoc, Identifier, Info.OpDecl);
1766 enum IntelOperatorKind {
1772 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1773 /// returns the number of elements in an array. It returns the value 1 for
1774 /// non-array variables. The SIZE operator returns the size of a C or C++
1775 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1776 /// TYPE operator returns the size of a C or C++ type or variable. If the
1777 /// variable is an array, TYPE returns the size of a single element.
1778 X86Operand *X86AsmParser::ParseIntelOperator(unsigned OpKind) {
1779 const AsmToken &Tok = Parser.getTok();
1780 SMLoc TypeLoc = Tok.getLoc();
1781 Parser.Lex(); // Eat operator.
1783 const MCExpr *Val = 0;
1784 InlineAsmIdentifierInfo Info;
1785 SMLoc Start = Tok.getLoc(), End;
1786 StringRef Identifier = Tok.getString();
1787 if (ParseIntelIdentifier(Val, Identifier, Info,
1788 /*Unevaluated=*/true, End))
1792 return ErrorOperand(Start, "unable to lookup expression");
1796 default: llvm_unreachable("Unexpected operand kind!");
1797 case IOK_LENGTH: CVal = Info.Length; break;
1798 case IOK_SIZE: CVal = Info.Size; break;
1799 case IOK_TYPE: CVal = Info.Type; break;
1802 // Rewrite the type operator and the C or C++ type or variable in terms of an
1803 // immediate. E.g. TYPE foo -> $$4
1804 unsigned Len = End.getPointer() - TypeLoc.getPointer();
1805 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, CVal));
1807 const MCExpr *Imm = MCConstantExpr::Create(CVal, getContext());
1808 return X86Operand::CreateImm(Imm, Start, End);
1811 X86Operand *X86AsmParser::ParseIntelOperand() {
1812 const AsmToken &Tok = Parser.getTok();
1815 // Offset, length, type and size operators.
1816 if (isParsingInlineAsm()) {
1817 StringRef AsmTokStr = Tok.getString();
1818 if (AsmTokStr == "offset" || AsmTokStr == "OFFSET")
1819 return ParseIntelOffsetOfOperator();
1820 if (AsmTokStr == "length" || AsmTokStr == "LENGTH")
1821 return ParseIntelOperator(IOK_LENGTH);
1822 if (AsmTokStr == "size" || AsmTokStr == "SIZE")
1823 return ParseIntelOperator(IOK_SIZE);
1824 if (AsmTokStr == "type" || AsmTokStr == "TYPE")
1825 return ParseIntelOperator(IOK_TYPE);
1828 unsigned Size = getIntelMemOperandSize(Tok.getString());
1830 Parser.Lex(); // Eat operand size (e.g., byte, word).
1831 if (Tok.getString() != "PTR" && Tok.getString() != "ptr")
1832 return ErrorOperand(Start, "Expected 'PTR' or 'ptr' token!");
1833 Parser.Lex(); // Eat ptr.
1835 Start = Tok.getLoc();
1838 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Minus) ||
1839 getLexer().is(AsmToken::LParen)) {
1840 AsmToken StartTok = Tok;
1841 IntelExprStateMachine SM(/*Imm=*/0, /*StopOnLBrac=*/true,
1842 /*AddImmPrefix=*/false);
1843 if (ParseIntelExpression(SM, End))
1846 int64_t Imm = SM.getImm();
1847 if (isParsingInlineAsm()) {
1848 unsigned Len = Tok.getLoc().getPointer() - Start.getPointer();
1849 if (StartTok.getString().size() == Len)
1850 // Just add a prefix if this wasn't a complex immediate expression.
1851 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix, Start));
1853 // Otherwise, rewrite the complex expression as a single immediate.
1854 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, Start, Len, Imm));
1857 if (getLexer().isNot(AsmToken::LBrac)) {
1858 // If a directional label (ie. 1f or 2b) was parsed above from
1859 // ParseIntelExpression() then SM.getSym() was set to a pointer to
1860 // to the MCExpr with the directional local symbol and this is a
1861 // memory operand not an immediate operand.
1863 return X86Operand::CreateMem(SM.getSym(), Start, End, Size);
1865 const MCExpr *ImmExpr = MCConstantExpr::Create(Imm, getContext());
1866 return X86Operand::CreateImm(ImmExpr, Start, End);
1869 // Only positive immediates are valid.
1871 return ErrorOperand(Start, "expected a positive immediate displacement "
1872 "before bracketed expr.");
1874 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1875 return ParseIntelMemOperand(Imm, Start, Size);
1880 if (!ParseRegister(RegNo, Start, End)) {
1881 // If this is a segment register followed by a ':', then this is the start
1882 // of a segment override, otherwise this is a normal register reference.
1883 if (getLexer().isNot(AsmToken::Colon))
1884 return X86Operand::CreateReg(RegNo, Start, End);
1886 return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
1890 return ParseIntelMemOperand(/*Disp=*/0, Start, Size);
1893 X86Operand *X86AsmParser::ParseATTOperand() {
1894 switch (getLexer().getKind()) {
1896 // Parse a memory operand with no segment register.
1897 return ParseMemOperand(0, Parser.getTok().getLoc());
1898 case AsmToken::Percent: {
1899 // Read the register.
1902 if (ParseRegister(RegNo, Start, End)) return 0;
1903 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1904 Error(Start, "%eiz and %riz can only be used as index registers",
1905 SMRange(Start, End));
1909 // If this is a segment register followed by a ':', then this is the start
1910 // of a memory reference, otherwise this is a normal register reference.
1911 if (getLexer().isNot(AsmToken::Colon))
1912 return X86Operand::CreateReg(RegNo, Start, End);
1914 getParser().Lex(); // Eat the colon.
1915 return ParseMemOperand(RegNo, Start);
1917 case AsmToken::Dollar: {
1918 // $42 -> immediate.
1919 SMLoc Start = Parser.getTok().getLoc(), End;
1922 if (getParser().parseExpression(Val, End))
1924 return X86Operand::CreateImm(Val, Start, End);
1929 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1930 /// has already been parsed if present.
1931 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
1933 // We have to disambiguate a parenthesized expression "(4+5)" from the start
1934 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
1935 // only way to do this without lookahead is to eat the '(' and see what is
1937 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1938 if (getLexer().isNot(AsmToken::LParen)) {
1940 if (getParser().parseExpression(Disp, ExprEnd)) return 0;
1942 // After parsing the base expression we could either have a parenthesized
1943 // memory address or not. If not, return now. If so, eat the (.
1944 if (getLexer().isNot(AsmToken::LParen)) {
1945 // Unless we have a segment register, treat this as an immediate.
1947 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
1948 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1954 // Okay, we have a '('. We don't know if this is an expression or not, but
1955 // so we have to eat the ( to see beyond it.
1956 SMLoc LParenLoc = Parser.getTok().getLoc();
1957 Parser.Lex(); // Eat the '('.
1959 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
1960 // Nothing to do here, fall into the code below with the '(' part of the
1961 // memory operand consumed.
1965 // It must be an parenthesized expression, parse it now.
1966 if (getParser().parseParenExpression(Disp, ExprEnd))
1969 // After parsing the base expression we could either have a parenthesized
1970 // memory address or not. If not, return now. If so, eat the (.
1971 if (getLexer().isNot(AsmToken::LParen)) {
1972 // Unless we have a segment register, treat this as an immediate.
1974 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
1975 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1983 // If we reached here, then we just ate the ( of the memory operand. Process
1984 // the rest of the memory operand.
1985 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1986 SMLoc IndexLoc, BaseLoc;
1988 if (getLexer().is(AsmToken::Percent)) {
1989 SMLoc StartLoc, EndLoc;
1990 BaseLoc = Parser.getTok().getLoc();
1991 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
1992 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1993 Error(StartLoc, "eiz and riz can only be used as index registers",
1994 SMRange(StartLoc, EndLoc));
1999 if (getLexer().is(AsmToken::Comma)) {
2000 Parser.Lex(); // Eat the comma.
2001 IndexLoc = Parser.getTok().getLoc();
2003 // Following the comma we should have either an index register, or a scale
2004 // value. We don't support the later form, but we want to parse it
2007 // Not that even though it would be completely consistent to support syntax
2008 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2009 if (getLexer().is(AsmToken::Percent)) {
2011 if (ParseRegister(IndexReg, L, L)) return 0;
2013 if (getLexer().isNot(AsmToken::RParen)) {
2014 // Parse the scale amount:
2015 // ::= ',' [scale-expression]
2016 if (getLexer().isNot(AsmToken::Comma)) {
2017 Error(Parser.getTok().getLoc(),
2018 "expected comma in scale expression");
2021 Parser.Lex(); // Eat the comma.
2023 if (getLexer().isNot(AsmToken::RParen)) {
2024 SMLoc Loc = Parser.getTok().getLoc();
2027 if (getParser().parseAbsoluteExpression(ScaleVal)){
2028 Error(Loc, "expected scale expression");
2032 // Validate the scale amount.
2033 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2035 Error(Loc, "scale factor in 16-bit address must be 1");
2038 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
2039 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
2042 Scale = (unsigned)ScaleVal;
2045 } else if (getLexer().isNot(AsmToken::RParen)) {
2046 // A scale amount without an index is ignored.
2048 SMLoc Loc = Parser.getTok().getLoc();
2051 if (getParser().parseAbsoluteExpression(Value))
2055 Warning(Loc, "scale factor without index register is ignored");
2060 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2061 if (getLexer().isNot(AsmToken::RParen)) {
2062 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
2065 SMLoc MemEnd = Parser.getTok().getEndLoc();
2066 Parser.Lex(); // Eat the ')'.
2068 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
2069 // and then only in non-64-bit modes. Except for DX, which is a special case
2070 // because an unofficial form of in/out instructions uses it.
2071 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2072 (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
2073 BaseReg != X86::SI && BaseReg != X86::DI)) &&
2074 BaseReg != X86::DX) {
2075 Error(BaseLoc, "invalid 16-bit base register");
2079 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2080 Error(IndexLoc, "16-bit memory operand may not include only index register");
2083 // If we have both a base register and an index register make sure they are
2084 // both 64-bit or 32-bit registers.
2085 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
2086 if (BaseReg != 0 && IndexReg != 0) {
2087 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
2088 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
2089 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
2090 IndexReg != X86::RIZ) {
2091 Error(BaseLoc, "base register is 64-bit, but index register is not");
2094 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
2095 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
2096 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
2097 IndexReg != X86::EIZ){
2098 Error(BaseLoc, "base register is 32-bit, but index register is not");
2101 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
2102 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
2103 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
2104 Error(BaseLoc, "base register is 16-bit, but index register is not");
2107 if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
2108 IndexReg != X86::SI && IndexReg != X86::DI) ||
2109 ((BaseReg == X86::SI || BaseReg == X86::DI) &&
2110 IndexReg != X86::BX && IndexReg != X86::BP)) {
2111 Error(BaseLoc, "invalid 16-bit base/index register combination");
2117 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
2122 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2123 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2125 StringRef PatchedName = Name;
2127 // FIXME: Hack to recognize setneb as setne.
2128 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2129 PatchedName != "setb" && PatchedName != "setnb")
2130 PatchedName = PatchedName.substr(0, Name.size()-1);
2132 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
2133 const MCExpr *ExtraImmOp = 0;
2134 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
2135 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2136 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
2137 bool IsVCMP = PatchedName[0] == 'v';
2138 unsigned SSECCIdx = IsVCMP ? 4 : 3;
2139 unsigned SSEComparisonCode = StringSwitch<unsigned>(
2140 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
2144 .Case("unord", 0x03)
2149 /* AVX only from here */
2150 .Case("eq_uq", 0x08)
2153 .Case("false", 0x0B)
2154 .Case("neq_oq", 0x0C)
2158 .Case("eq_os", 0x10)
2159 .Case("lt_oq", 0x11)
2160 .Case("le_oq", 0x12)
2161 .Case("unord_s", 0x13)
2162 .Case("neq_us", 0x14)
2163 .Case("nlt_uq", 0x15)
2164 .Case("nle_uq", 0x16)
2165 .Case("ord_s", 0x17)
2166 .Case("eq_us", 0x18)
2167 .Case("nge_uq", 0x19)
2168 .Case("ngt_uq", 0x1A)
2169 .Case("false_os", 0x1B)
2170 .Case("neq_os", 0x1C)
2171 .Case("ge_oq", 0x1D)
2172 .Case("gt_oq", 0x1E)
2173 .Case("true_us", 0x1F)
2175 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
2176 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
2177 getParser().getContext());
2178 if (PatchedName.endswith("ss")) {
2179 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
2180 } else if (PatchedName.endswith("sd")) {
2181 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
2182 } else if (PatchedName.endswith("ps")) {
2183 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
2185 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
2186 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
2191 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
2193 if (ExtraImmOp && !isParsingIntelSyntax())
2194 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
2196 // Determine whether this is an instruction prefix.
2198 Name == "lock" || Name == "rep" ||
2199 Name == "repe" || Name == "repz" ||
2200 Name == "repne" || Name == "repnz" ||
2201 Name == "rex64" || Name == "data16";
2204 // This does the actual operand parsing. Don't parse any more if we have a
2205 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2206 // just want to parse the "lock" as the first instruction and the "incl" as
2208 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
2210 // Parse '*' modifier.
2211 if (getLexer().is(AsmToken::Star))
2212 Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2214 // Read the first operand.
2215 if (X86Operand *Op = ParseOperand())
2216 Operands.push_back(Op);
2218 Parser.eatToEndOfStatement();
2222 while (getLexer().is(AsmToken::Comma)) {
2223 Parser.Lex(); // Eat the comma.
2225 // Parse and remember the operand.
2226 if (X86Operand *Op = ParseOperand())
2227 Operands.push_back(Op);
2229 Parser.eatToEndOfStatement();
2234 if (STI.getFeatureBits() & X86::FeatureAVX512) {
2235 // Parse mask register {%k1}
2236 if (getLexer().is(AsmToken::LCurly)) {
2237 Operands.push_back(X86Operand::CreateToken("{", consumeToken()));
2238 if (X86Operand *Op = ParseOperand()) {
2239 Operands.push_back(Op);
2240 if (!getLexer().is(AsmToken::RCurly)) {
2241 SMLoc Loc = getLexer().getLoc();
2242 Parser.eatToEndOfStatement();
2243 return Error(Loc, "Expected } at this point");
2245 Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2247 Parser.eatToEndOfStatement();
2251 // TODO: add parsing of broadcasts {1to8}, {1to16}
2252 // Parse "zeroing non-masked" semantic {z}
2253 if (getLexer().is(AsmToken::LCurly)) {
2254 Operands.push_back(X86Operand::CreateToken("{z}", consumeToken()));
2255 if (!getLexer().is(AsmToken::Identifier) || getLexer().getTok().getIdentifier() != "z") {
2256 SMLoc Loc = getLexer().getLoc();
2257 Parser.eatToEndOfStatement();
2258 return Error(Loc, "Expected z at this point");
2260 Parser.Lex(); // Eat the z
2261 if (!getLexer().is(AsmToken::RCurly)) {
2262 SMLoc Loc = getLexer().getLoc();
2263 Parser.eatToEndOfStatement();
2264 return Error(Loc, "Expected } at this point");
2266 Parser.Lex(); // Eat the }
2270 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2271 SMLoc Loc = getLexer().getLoc();
2272 Parser.eatToEndOfStatement();
2273 return Error(Loc, "unexpected token in argument list");
2277 if (getLexer().is(AsmToken::EndOfStatement))
2278 Parser.Lex(); // Consume the EndOfStatement
2279 else if (isPrefix && getLexer().is(AsmToken::Slash))
2280 Parser.Lex(); // Consume the prefix separator Slash
2282 if (ExtraImmOp && isParsingIntelSyntax())
2283 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
2285 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
2286 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2287 // documented form in various unofficial manuals, so a lot of code uses it.
2288 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
2289 Operands.size() == 3) {
2290 X86Operand &Op = *(X86Operand*)Operands.back();
2291 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2292 isa<MCConstantExpr>(Op.Mem.Disp) &&
2293 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2294 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2295 SMLoc Loc = Op.getEndLoc();
2296 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2300 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
2301 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
2302 Operands.size() == 3) {
2303 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2304 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2305 isa<MCConstantExpr>(Op.Mem.Disp) &&
2306 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2307 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2308 SMLoc Loc = Op.getEndLoc();
2309 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2314 // Append default arguments to "ins[bwld]"
2315 if (Name.startswith("ins") && Operands.size() == 1 &&
2316 (Name == "insb" || Name == "insw" || Name == "insl" ||
2318 if (isParsingIntelSyntax()) {
2319 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2320 Operands.push_back(DefaultMemDIOperand(NameLoc));
2322 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2323 Operands.push_back(DefaultMemDIOperand(NameLoc));
2327 // Append default arguments to "outs[bwld]"
2328 if (Name.startswith("outs") && Operands.size() == 1 &&
2329 (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
2330 Name == "outsd" )) {
2331 if (isParsingIntelSyntax()) {
2332 Operands.push_back(DefaultMemSIOperand(NameLoc));
2333 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2335 Operands.push_back(DefaultMemSIOperand(NameLoc));
2336 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2340 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2341 // values of $SIREG according to the mode. It would be nice if this
2342 // could be achieved with InstAlias in the tables.
2343 if (Name.startswith("lods") && Operands.size() == 1 &&
2344 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2345 Name == "lodsl" || Name == "lodsd" || Name == "lodsq"))
2346 Operands.push_back(DefaultMemSIOperand(NameLoc));
2348 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2349 // values of $DIREG according to the mode. It would be nice if this
2350 // could be achieved with InstAlias in the tables.
2351 if (Name.startswith("stos") && Operands.size() == 1 &&
2352 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2353 Name == "stosl" || Name == "stosd" || Name == "stosq"))
2354 Operands.push_back(DefaultMemDIOperand(NameLoc));
2356 // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2357 // values of $DIREG according to the mode. It would be nice if this
2358 // could be achieved with InstAlias in the tables.
2359 if (Name.startswith("scas") && Operands.size() == 1 &&
2360 (Name == "scas" || Name == "scasb" || Name == "scasw" ||
2361 Name == "scasl" || Name == "scasd" || Name == "scasq"))
2362 Operands.push_back(DefaultMemDIOperand(NameLoc));
2364 // Add default SI and DI operands to "cmps[bwlq]".
2365 if (Name.startswith("cmps") &&
2366 (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
2367 Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
2368 if (Operands.size() == 1) {
2369 if (isParsingIntelSyntax()) {
2370 Operands.push_back(DefaultMemSIOperand(NameLoc));
2371 Operands.push_back(DefaultMemDIOperand(NameLoc));
2373 Operands.push_back(DefaultMemDIOperand(NameLoc));
2374 Operands.push_back(DefaultMemSIOperand(NameLoc));
2376 } else if (Operands.size() == 3) {
2377 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2378 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2379 if (!doSrcDstMatch(Op, Op2))
2380 return Error(Op.getStartLoc(),
2381 "mismatching source and destination index registers");
2385 // Add default SI and DI operands to "movs[bwlq]".
2386 if ((Name.startswith("movs") &&
2387 (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2388 Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2389 (Name.startswith("smov") &&
2390 (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2391 Name == "smovl" || Name == "smovd" || Name == "smovq"))) {
2392 if (Operands.size() == 1) {
2393 if (Name == "movsd")
2394 Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2395 if (isParsingIntelSyntax()) {
2396 Operands.push_back(DefaultMemDIOperand(NameLoc));
2397 Operands.push_back(DefaultMemSIOperand(NameLoc));
2399 Operands.push_back(DefaultMemSIOperand(NameLoc));
2400 Operands.push_back(DefaultMemDIOperand(NameLoc));
2402 } else if (Operands.size() == 3) {
2403 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2404 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2405 if (!doSrcDstMatch(Op, Op2))
2406 return Error(Op.getStartLoc(),
2407 "mismatching source and destination index registers");
2411 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2413 if ((Name.startswith("shr") || Name.startswith("sar") ||
2414 Name.startswith("shl") || Name.startswith("sal") ||
2415 Name.startswith("rcl") || Name.startswith("rcr") ||
2416 Name.startswith("rol") || Name.startswith("ror")) &&
2417 Operands.size() == 3) {
2418 if (isParsingIntelSyntax()) {
2420 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
2421 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2422 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2424 Operands.pop_back();
2427 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2428 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2429 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2431 Operands.erase(Operands.begin() + 1);
2436 // Transforms "int $3" into "int3" as a size optimization. We can't write an
2437 // instalias with an immediate operand yet.
2438 if (Name == "int" && Operands.size() == 2) {
2439 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2440 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2441 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
2443 Operands.erase(Operands.begin() + 1);
2444 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
2451 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
2454 TmpInst.setOpcode(Opcode);
2456 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2457 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2458 TmpInst.addOperand(Inst.getOperand(0));
2463 static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
2464 bool isCmp = false) {
2465 if (!Inst.getOperand(0).isImm() ||
2466 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
2469 return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2472 static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
2473 bool isCmp = false) {
2474 if (!Inst.getOperand(0).isImm() ||
2475 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
2478 return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2481 static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
2482 bool isCmp = false) {
2483 if (!Inst.getOperand(0).isImm() ||
2484 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
2487 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2491 processInstruction(MCInst &Inst,
2492 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
2493 switch (Inst.getOpcode()) {
2494 default: return false;
2495 case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2496 case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2497 case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2498 case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2499 case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2500 case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2501 case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
2502 case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
2503 case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
2504 case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2505 case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2506 case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2507 case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2508 case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2509 case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2510 case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2511 case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2512 case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2513 case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2514 case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2515 case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2516 case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2517 case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2518 case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2519 case X86::VMOVAPDrr:
2520 case X86::VMOVAPDYrr:
2521 case X86::VMOVAPSrr:
2522 case X86::VMOVAPSYrr:
2523 case X86::VMOVDQArr:
2524 case X86::VMOVDQAYrr:
2525 case X86::VMOVDQUrr:
2526 case X86::VMOVDQUYrr:
2527 case X86::VMOVUPDrr:
2528 case X86::VMOVUPDYrr:
2529 case X86::VMOVUPSrr:
2530 case X86::VMOVUPSYrr: {
2531 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2532 !X86II::isX86_64ExtendedReg(Inst.getOperand(1).getReg()))
2536 switch (Inst.getOpcode()) {
2537 default: llvm_unreachable("Invalid opcode");
2538 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2539 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2540 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2541 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2542 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2543 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2544 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2545 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2546 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2547 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2548 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2549 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2551 Inst.setOpcode(NewOpc);
2555 case X86::VMOVSSrr: {
2556 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2557 !X86II::isX86_64ExtendedReg(Inst.getOperand(2).getReg()))
2560 switch (Inst.getOpcode()) {
2561 default: llvm_unreachable("Invalid opcode");
2562 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
2563 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
2565 Inst.setOpcode(NewOpc);
2571 static const char *getSubtargetFeatureName(unsigned Val);
2573 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2574 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2575 MCStreamer &Out, unsigned &ErrorInfo,
2576 bool MatchingInlineAsm) {
2577 assert(!Operands.empty() && "Unexpect empty operand list!");
2578 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
2579 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
2580 ArrayRef<SMRange> EmptyRanges = None;
2582 // First, handle aliases that expand to multiple instructions.
2583 // FIXME: This should be replaced with a real .td file alias mechanism.
2584 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2586 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
2587 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
2588 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
2589 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
2591 Inst.setOpcode(X86::WAIT);
2593 if (!MatchingInlineAsm)
2594 Out.EmitInstruction(Inst);
2597 StringSwitch<const char*>(Op->getToken())
2598 .Case("finit", "fninit")
2599 .Case("fsave", "fnsave")
2600 .Case("fstcw", "fnstcw")
2601 .Case("fstcww", "fnstcw")
2602 .Case("fstenv", "fnstenv")
2603 .Case("fstsw", "fnstsw")
2604 .Case("fstsww", "fnstsw")
2605 .Case("fclex", "fnclex")
2607 assert(Repl && "Unknown wait-prefixed instruction");
2609 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2612 bool WasOriginallyInvalidOperand = false;
2615 // First, try a direct match.
2616 switch (MatchInstructionImpl(Operands, Inst,
2617 ErrorInfo, MatchingInlineAsm,
2618 isParsingIntelSyntax())) {
2621 // Some instructions need post-processing to, for example, tweak which
2622 // encoding is selected. Loop on it while changes happen so the
2623 // individual transformations can chain off each other.
2624 if (!MatchingInlineAsm)
2625 while (processInstruction(Inst, Operands))
2629 if (!MatchingInlineAsm)
2630 Out.EmitInstruction(Inst);
2631 Opcode = Inst.getOpcode();
2633 case Match_MissingFeature: {
2634 assert(ErrorInfo && "Unknown missing feature!");
2635 // Special case the error message for the very common case where only
2636 // a single subtarget feature is missing.
2637 std::string Msg = "instruction requires:";
2639 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2640 if (ErrorInfo & Mask) {
2642 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
2646 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2648 case Match_InvalidOperand:
2649 WasOriginallyInvalidOperand = true;
2651 case Match_MnemonicFail:
2655 // FIXME: Ideally, we would only attempt suffix matches for things which are
2656 // valid prefixes, and we could just infer the right unambiguous
2657 // type. However, that requires substantially more matcher support than the
2660 // Change the operand to point to a temporary token.
2661 StringRef Base = Op->getToken();
2662 SmallString<16> Tmp;
2665 Op->setTokenValue(Tmp.str());
2667 // If this instruction starts with an 'f', then it is a floating point stack
2668 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2669 // 80-bit floating point, which use the suffixes s,l,t respectively.
2671 // Otherwise, we assume that this may be an integer instruction, which comes
2672 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2673 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2675 // Check for the various suffix matches.
2676 Tmp[Base.size()] = Suffixes[0];
2677 unsigned ErrorInfoIgnore;
2678 unsigned ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2679 unsigned Match1, Match2, Match3, Match4;
2681 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2682 MatchingInlineAsm, isParsingIntelSyntax());
2683 // If this returned as a missing feature failure, remember that.
2684 if (Match1 == Match_MissingFeature)
2685 ErrorInfoMissingFeature = ErrorInfoIgnore;
2686 Tmp[Base.size()] = Suffixes[1];
2687 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2688 MatchingInlineAsm, isParsingIntelSyntax());
2689 // If this returned as a missing feature failure, remember that.
2690 if (Match2 == Match_MissingFeature)
2691 ErrorInfoMissingFeature = ErrorInfoIgnore;
2692 Tmp[Base.size()] = Suffixes[2];
2693 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2694 MatchingInlineAsm, isParsingIntelSyntax());
2695 // If this returned as a missing feature failure, remember that.
2696 if (Match3 == Match_MissingFeature)
2697 ErrorInfoMissingFeature = ErrorInfoIgnore;
2698 Tmp[Base.size()] = Suffixes[3];
2699 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2700 MatchingInlineAsm, isParsingIntelSyntax());
2701 // If this returned as a missing feature failure, remember that.
2702 if (Match4 == Match_MissingFeature)
2703 ErrorInfoMissingFeature = ErrorInfoIgnore;
2705 // Restore the old token.
2706 Op->setTokenValue(Base);
2708 // If exactly one matched, then we treat that as a successful match (and the
2709 // instruction will already have been filled in correctly, since the failing
2710 // matches won't have modified it).
2711 unsigned NumSuccessfulMatches =
2712 (Match1 == Match_Success) + (Match2 == Match_Success) +
2713 (Match3 == Match_Success) + (Match4 == Match_Success);
2714 if (NumSuccessfulMatches == 1) {
2716 if (!MatchingInlineAsm)
2717 Out.EmitInstruction(Inst);
2718 Opcode = Inst.getOpcode();
2722 // Otherwise, the match failed, try to produce a decent error message.
2724 // If we had multiple suffix matches, then identify this as an ambiguous
2726 if (NumSuccessfulMatches > 1) {
2728 unsigned NumMatches = 0;
2729 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
2730 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
2731 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
2732 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
2734 SmallString<126> Msg;
2735 raw_svector_ostream OS(Msg);
2736 OS << "ambiguous instructions require an explicit suffix (could be ";
2737 for (unsigned i = 0; i != NumMatches; ++i) {
2740 if (i + 1 == NumMatches)
2742 OS << "'" << Base << MatchChars[i] << "'";
2745 Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
2749 // Okay, we know that none of the variants matched successfully.
2751 // If all of the instructions reported an invalid mnemonic, then the original
2752 // mnemonic was invalid.
2753 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
2754 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
2755 if (!WasOriginallyInvalidOperand) {
2756 ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
2758 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2759 Ranges, MatchingInlineAsm);
2762 // Recover location info for the operand if we know which was the problem.
2763 if (ErrorInfo != ~0U) {
2764 if (ErrorInfo >= Operands.size())
2765 return Error(IDLoc, "too few operands for instruction",
2766 EmptyRanges, MatchingInlineAsm);
2768 X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
2769 if (Operand->getStartLoc().isValid()) {
2770 SMRange OperandRange = Operand->getLocRange();
2771 return Error(Operand->getStartLoc(), "invalid operand for instruction",
2772 OperandRange, MatchingInlineAsm);
2776 return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2780 // If one instruction matched with a missing feature, report this as a
2782 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
2783 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
2784 std::string Msg = "instruction requires:";
2786 for (unsigned i = 0; i < (sizeof(ErrorInfoMissingFeature)*8-1); ++i) {
2787 if (ErrorInfoMissingFeature & Mask) {
2789 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2793 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2796 // If one instruction matched with an invalid operand, report this as an
2798 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
2799 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
2800 Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2805 // If all of these were an outright failure, report it in a useless way.
2806 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2807 EmptyRanges, MatchingInlineAsm);
2812 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
2813 StringRef IDVal = DirectiveID.getIdentifier();
2814 if (IDVal == ".word")
2815 return ParseDirectiveWord(2, DirectiveID.getLoc());
2816 else if (IDVal.startswith(".code"))
2817 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
2818 else if (IDVal.startswith(".att_syntax")) {
2819 getParser().setAssemblerDialect(0);
2821 } else if (IDVal.startswith(".intel_syntax")) {
2822 getParser().setAssemblerDialect(1);
2823 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2824 // FIXME: Handle noprefix
2825 if (Parser.getTok().getString() == "noprefix")
2833 /// ParseDirectiveWord
2834 /// ::= .word [ expression (, expression)* ]
2835 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2836 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2838 const MCExpr *Value;
2839 if (getParser().parseExpression(Value))
2842 getParser().getStreamer().EmitValue(Value, Size);
2844 if (getLexer().is(AsmToken::EndOfStatement))
2847 // FIXME: Improve diagnostic.
2848 if (getLexer().isNot(AsmToken::Comma)) {
2849 Error(L, "unexpected token in directive");
2860 /// ParseDirectiveCode
2861 /// ::= .code16 | .code32 | .code64
2862 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
2863 if (IDVal == ".code16") {
2865 if (!is16BitMode()) {
2866 SwitchMode(X86::Mode16Bit);
2867 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2869 } else if (IDVal == ".code32") {
2871 if (!is32BitMode()) {
2872 SwitchMode(X86::Mode32Bit);
2873 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2875 } else if (IDVal == ".code64") {
2877 if (!is64BitMode()) {
2878 SwitchMode(X86::Mode64Bit);
2879 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
2882 Error(L, "unknown directive " + IDVal);
2889 // Force static initialization.
2890 extern "C" void LLVMInitializeX86AsmParser() {
2891 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2892 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2895 #define GET_REGISTER_MATCHER
2896 #define GET_MATCHER_IMPLEMENTATION
2897 #define GET_SUBTARGET_FEATURE_NAME
2898 #include "X86GenAsmMatcher.inc"