1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssembly.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyTargetMachine.h"
18 #include "WebAssemblyTargetObjectFile.h"
19 #include "WebAssemblyTargetTransformInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Transforms/Scalar.h"
30 #define DEBUG_TYPE "wasm"
32 extern "C" void LLVMInitializeWebAssemblyTarget() {
33 // Register the target.
34 RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32);
35 RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64);
38 //===----------------------------------------------------------------------===//
39 // WebAssembly Lowering public interface.
40 //===----------------------------------------------------------------------===//
42 /// Create an WebAssembly architecture model.
44 WebAssemblyTargetMachine::WebAssemblyTargetMachine(
45 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
46 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
48 : LLVMTargetMachine(T, TT.isArch64Bit()
49 ? "e-p:64:64-i64:64-n32:64-S128"
50 : "e-p:32:32-i64:64-n32:64-S128",
51 TT, CPU, FS, Options, RM, CM, OL),
52 TLOF(make_unique<WebAssemblyTargetObjectFile>()) {
55 // We need a reducible CFG, so disable some optimizations which tend to
56 // introduce irreducibility.
57 setRequiresStructuredCFG(true);
60 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
62 const WebAssemblySubtarget *
63 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
64 Attribute CPUAttr = F.getFnAttribute("target-cpu");
65 Attribute FSAttr = F.getFnAttribute("target-features");
67 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
68 ? CPUAttr.getValueAsString().str()
70 std::string FS = !FSAttr.hasAttribute(Attribute::None)
71 ? FSAttr.getValueAsString().str()
74 auto &I = SubtargetMap[CPU + FS];
76 // This needs to be done before we create a new subtarget since any
77 // creation will depend on the TM and the code generation flags on the
78 // function that reside in TargetOptions.
79 resetTargetOptions(F);
80 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
86 /// WebAssembly Code Generator Pass Configuration Options.
87 class WebAssemblyPassConfig final : public TargetPassConfig {
89 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM)
90 : TargetPassConfig(TM, PM) {}
92 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
93 return getTM<WebAssemblyTargetMachine>();
96 FunctionPass *createTargetRegisterAllocator(bool) override;
98 void addIRPasses() override;
99 bool addPreISel() override;
100 bool addInstSelector() override;
101 bool addILPOpts() override;
102 void addPreRegAlloc() override;
103 void addPostRegAlloc() override;
104 void addPreSched2() override;
105 void addPreEmitPass() override;
107 } // end anonymous namespace
109 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
110 return TargetIRAnalysis([this](const Function &F) {
111 return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
116 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
117 return new WebAssemblyPassConfig(this, PM);
120 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
121 return nullptr; // No reg alloc
124 //===----------------------------------------------------------------------===//
125 // The following functions are called from lib/CodeGen/Passes.cpp to modify
126 // the CodeGen pass sequence.
127 //===----------------------------------------------------------------------===//
129 void WebAssemblyPassConfig::addIRPasses() {
130 // FIXME: the default for this option is currently POSIX, whereas
131 // WebAssembly's MVP should default to Single.
132 if (TM->Options.ThreadModel == ThreadModel::Single)
133 addPass(createLowerAtomicPass());
135 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
136 // control specifically what gets lowered.
137 addPass(createAtomicExpandPass(TM));
139 TargetPassConfig::addIRPasses();
142 bool WebAssemblyPassConfig::addPreISel() { return false; }
144 bool WebAssemblyPassConfig::addInstSelector() {
146 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
150 bool WebAssemblyPassConfig::addILPOpts() { return true; }
152 void WebAssemblyPassConfig::addPreRegAlloc() {}
154 void WebAssemblyPassConfig::addPostRegAlloc() {
155 // FIXME: the following passes dislike virtual registers. Disable them for now
156 // so that basic tests can pass. Future patches will remedy this.
158 // Fails with: Regalloc must assign all vregs.
159 disablePass(&PrologEpilogCodeInserterID);
160 // Fails with: should be run after register allocation.
161 disablePass(&MachineCopyPropagationID);
163 // TODO: Until we get ReverseBranchCondition support, MachineBlockPlacement
164 // can create ugly-looking control flow.
165 disablePass(&MachineBlockPlacementID);
168 void WebAssemblyPassConfig::addPreSched2() {}
170 void WebAssemblyPassConfig::addPreEmitPass() {
171 addPass(createWebAssemblyCFGStackify());