1 // WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief WebAssembly Memory operand code-gen constructs.
13 //===----------------------------------------------------------------------===//
17 // - WebAssemblyTargetLowering::isLegalAddressingMode
18 // - WebAssemblyTargetLowering having to do with atomics
19 // - Each has optional alignment and immediate byte offset.
21 // WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
22 // local types. These memory-only types instead zero- or sign-extend into local
23 // types when loading, and truncate when storing.
25 let Defs = [ARGUMENTS] in {
28 def LOAD_I32 : I<(outs I32:$dst), (ins I32:$addr),
29 [(set I32:$dst, (load I32:$addr))],
30 "i32.load\t$dst, $addr">;
31 def LOAD_I64 : I<(outs I64:$dst), (ins I32:$addr),
32 [(set I64:$dst, (load I32:$addr))],
33 "i64.load\t$dst, $addr">;
34 def LOAD_F32 : I<(outs F32:$dst), (ins I32:$addr),
35 [(set F32:$dst, (load I32:$addr))],
36 "f32.load\t$dst, $addr">;
37 def LOAD_F64 : I<(outs F64:$dst), (ins I32:$addr),
38 [(set F64:$dst, (load I32:$addr))],
39 "f64.load\t$dst, $addr">;
42 def LOAD8_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
43 [(set I32:$dst, (sextloadi8 I32:$addr))],
44 "i32.load8_s\t$dst, $addr">;
45 def LOAD8_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
46 [(set I32:$dst, (zextloadi8 I32:$addr))],
47 "i32.load8_u\t$dst, $addr">;
48 def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
49 [(set I32:$dst, (sextloadi16 I32:$addr))],
50 "i32.load16_s\t$dst, $addr">;
51 def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
52 [(set I32:$dst, (zextloadi16 I32:$addr))],
53 "i32.load16_u\t$dst, $addr">;
54 def LOAD8_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
55 [(set I64:$dst, (sextloadi8 I32:$addr))],
56 "i64.load8_s\t$dst, $addr">;
57 def LOAD8_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
58 [(set I64:$dst, (zextloadi8 I32:$addr))],
59 "i64.load8_u\t$dst, $addr">;
60 def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
61 [(set I64:$dst, (sextloadi16 I32:$addr))],
62 "i64.load16_s\t$dst, $addr">;
63 def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
64 [(set I64:$dst, (zextloadi16 I32:$addr))],
65 "i64.load16_u\t$dst, $addr">;
66 def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
67 [(set I64:$dst, (sextloadi32 I32:$addr))],
68 "i64.load32_s\t$dst, $addr">;
69 def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
70 [(set I64:$dst, (zextloadi32 I32:$addr))],
71 "i64.load32_u\t$dst, $addr">;
73 } // Defs = [ARGUMENTS]
75 // "Don't care" extending load become zero-extending load.
76 def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 $addr)>;
77 def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 $addr)>;
78 def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 $addr)>;
79 def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 $addr)>;
80 def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 $addr)>;
82 let Defs = [ARGUMENTS] in {
85 // Note that we split the patterns out of the instruction definitions because
86 // WebAssembly's stores return their operand value, and tablegen doesn't like
87 // instruction definition patterns that don't reference all of the output
89 // Note: WebAssembly inverts SelectionDAG's usual operand order.
90 def STORE_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
91 "i32.store\t$dst, $addr, $val">;
92 def STORE_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
93 "i64.store\t$dst, $addr, $val">;
94 def STORE_F32 : I<(outs F32:$dst), (ins I32:$addr, F32:$val), [],
95 "f32.store\t$dst, $addr, $val">;
96 def STORE_F64 : I<(outs F64:$dst), (ins I32:$addr, F64:$val), [],
97 "f64.store\t$dst, $addr, $val">;
99 } // Defs = [ARGUMENTS]
101 def : Pat<(store I32:$val, I32:$addr), (STORE_I32 I32:$addr, I32:$val)>;
102 def : Pat<(store I64:$val, I32:$addr), (STORE_I64 I32:$addr, I64:$val)>;
103 def : Pat<(store F32:$val, I32:$addr), (STORE_F32 I32:$addr, F32:$val)>;
104 def : Pat<(store F64:$val, I32:$addr), (STORE_F64 I32:$addr, F64:$val)>;
106 let Defs = [ARGUMENTS] in {
109 def STORE8_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
110 "i32.store8\t$dst, $addr, $val">;
111 def STORE16_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
112 "i32.store16\t$dst, $addr, $val">;
113 def STORE8_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
114 "i64.store8\t$dst, $addr, $val">;
115 def STORE16_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
116 "i64.store16\t$dst, $addr, $val">;
117 def STORE32_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
118 "i64.store32\t$dst, $addr, $val">;
120 } // Defs = [ARGUMENTS]
122 def : Pat<(truncstorei8 I32:$val, I32:$addr),
123 (STORE8_I32 I32:$addr, I32:$val)>;
124 def : Pat<(truncstorei16 I32:$val, I32:$addr),
125 (STORE16_I32 I32:$addr, I32:$val)>;
126 def : Pat<(truncstorei8 I64:$val, I32:$addr),
127 (STORE8_I64 I32:$addr, I64:$val)>;
128 def : Pat<(truncstorei16 I64:$val, I32:$addr),
129 (STORE16_I64 I32:$addr, I64:$val)>;
130 def : Pat<(truncstorei32 I64:$val, I32:$addr),
131 (STORE32_I64 I32:$addr, I64:$val)>;
133 let Defs = [ARGUMENTS] in {
136 def MEMORY_SIZE_I32 : I<(outs I32:$dst), (ins),
137 [(set I32:$dst, (int_wasm_memory_size))],
138 "memory_size\t$dst">,
139 Requires<[HasAddr32]>;
140 def MEMORY_SIZE_I64 : I<(outs I64:$dst), (ins),
141 [(set I64:$dst, (int_wasm_memory_size))],
142 "memory_size\t$dst">,
143 Requires<[HasAddr64]>;
146 def GROW_MEMORY_I32 : I<(outs), (ins I32:$delta),
147 [(int_wasm_grow_memory I32:$delta)],
148 "grow_memory\t$delta">,
149 Requires<[HasAddr32]>;
150 def GROW_MEMORY_I64 : I<(outs), (ins I64:$delta),
151 [(int_wasm_grow_memory I64:$delta)],
152 "grow_memory\t$delta">,
153 Requires<[HasAddr64]>;
155 } // Defs = [ARGUMENTS]