1 // WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief WebAssembly Memory operand code-gen constructs.
13 //===----------------------------------------------------------------------===//
17 // - WebAssemblyTargetLowering::isLegalAddressingMode
18 // - WebAssemblyTargetLowering having to do with atomics
19 // - Each has optional alignment and immediate byte offset.
21 // WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
22 // local types. These memory-only types instead zero- or sign-extend into local
23 // types when loading, and truncate when storing.
25 let Defs = [ARGUMENTS] in {
28 def LOAD_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
29 "i32.load\t$dst, $off($addr)">;
30 def LOAD_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
31 "i64.load\t$dst, $off($addr)">;
32 def LOAD_F32 : I<(outs F32:$dst), (ins I32:$off, I32:$addr), [],
33 "f32.load\t$dst, $off($addr)">;
34 def LOAD_F64 : I<(outs F64:$dst), (ins I32:$off, I32:$addr), [],
35 "f64.load\t$dst, $off($addr)">;
38 def LOAD8_S_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
39 "i32.load8_s\t$dst, $off($addr)">;
40 def LOAD8_U_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
41 "i32.load8_u\t$dst, $off($addr)">;
42 def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
43 "i32.load16_s\t$dst, $off($addr)">;
44 def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
45 "i32.load16_u\t$dst, $off($addr)">;
46 def LOAD8_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
47 "i64.load8_s\t$dst, $off($addr)">;
48 def LOAD8_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
49 "i64.load8_u\t$dst, $off($addr)">;
50 def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
51 "i64.load16_s\t$dst, $off($addr)">;
52 def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
53 "i64.load16_u\t$dst, $off($addr)">;
54 def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
55 "i64.load32_s\t$dst, $off($addr)">;
56 def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
57 "i64.load32_u\t$dst, $off($addr)">;
59 } // Defs = [ARGUMENTS]
61 // Select loads with no constant offset.
62 def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr)>;
63 def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr)>;
64 def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr)>;
65 def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr)>;
67 // Select extending loads with no constant offset.
68 def : Pat<(i32 (sextloadi8 I32:$addr)), (LOAD8_S_I32 0, $addr)>;
69 def : Pat<(i32 (zextloadi8 I32:$addr)), (LOAD8_U_I32 0, $addr)>;
70 def : Pat<(i32 (sextloadi16 I32:$addr)), (LOAD16_S_I32 0, $addr)>;
71 def : Pat<(i32 (zextloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr)>;
72 def : Pat<(i64 (sextloadi8 I32:$addr)), (LOAD8_S_I64 0, $addr)>;
73 def : Pat<(i64 (zextloadi8 I32:$addr)), (LOAD8_U_I64 0, $addr)>;
74 def : Pat<(i64 (sextloadi16 I32:$addr)), (LOAD16_S_I64 0, $addr)>;
75 def : Pat<(i64 (zextloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr)>;
76 def : Pat<(i64 (sextloadi32 I32:$addr)), (LOAD32_S_I64 0, $addr)>;
77 def : Pat<(i64 (zextloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr)>;
79 // "Don't care" extending load become zero-extending load.
80 def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 0, $addr)>;
81 def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr)>;
82 def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 0, $addr)>;
83 def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr)>;
84 def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr)>;
86 let Defs = [ARGUMENTS] in {
89 // Note that we split the patterns out of the instruction definitions because
90 // WebAssembly's stores return their operand value, and tablegen doesn't like
91 // instruction definition patterns that don't reference all of the output
93 // Note: WebAssembly inverts SelectionDAG's usual operand order.
94 def STORE_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
95 "i32.store\t$dst, $off($addr), $val">;
96 def STORE_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
97 "i64.store\t$dst, $off($addr), $val">;
98 def STORE_F32 : I<(outs F32:$dst), (ins I32:$off, I32:$addr, F32:$val), [],
99 "f32.store\t$dst, $off($addr), $val">;
100 def STORE_F64 : I<(outs F64:$dst), (ins I32:$off, I32:$addr, F64:$val), [],
101 "f64.store\t$dst, $off($addr), $val">;
103 } // Defs = [ARGUMENTS]
105 def : Pat<(store I32:$val, I32:$addr), (STORE_I32 0, I32:$addr, I32:$val)>;
106 def : Pat<(store I64:$val, I32:$addr), (STORE_I64 0, I32:$addr, I64:$val)>;
107 def : Pat<(store F32:$val, I32:$addr), (STORE_F32 0, I32:$addr, F32:$val)>;
108 def : Pat<(store F64:$val, I32:$addr), (STORE_F64 0, I32:$addr, F64:$val)>;
110 // FIXME: This pattern matches an immediate to actually use the offset field
111 // in the store instruction; however only unsigned offsets are supported in
112 // wasm, so we need to constrain the immediate we match. This may require
113 // custom code rather than a simple pattern.
114 // def : Pat<(store I32:$val, (add I32:$addr, (i32 imm:$off))),
115 // (STORE_I32 imm:$off, I32:$addr, I32:$val)>;
117 let Defs = [ARGUMENTS] in {
120 def STORE8_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
121 "i32.store8\t$dst, $off($addr), $val">;
122 def STORE16_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
123 "i32.store16\t$dst, $off($addr), $val">;
124 def STORE8_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
125 "i64.store8\t$dst, $off($addr), $val">;
126 def STORE16_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
127 "i64.store16\t$dst, $off($addr), $val">;
128 def STORE32_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
129 "i64.store32\t$dst, $off($addr), $val">;
131 } // Defs = [ARGUMENTS]
133 def : Pat<(truncstorei8 I32:$val, I32:$addr),
134 (STORE8_I32 0, I32:$addr, I32:$val)>;
135 def : Pat<(truncstorei16 I32:$val, I32:$addr),
136 (STORE16_I32 0, I32:$addr, I32:$val)>;
137 def : Pat<(truncstorei8 I64:$val, I32:$addr),
138 (STORE8_I64 0, I32:$addr, I64:$val)>;
139 def : Pat<(truncstorei16 I64:$val, I32:$addr),
140 (STORE16_I64 0, I32:$addr, I64:$val)>;
141 def : Pat<(truncstorei32 I64:$val, I32:$addr),
142 (STORE32_I64 0, I32:$addr, I64:$val)>;
144 let Defs = [ARGUMENTS] in {
147 def MEMORY_SIZE_I32 : I<(outs I32:$dst), (ins),
148 [(set I32:$dst, (int_wasm_memory_size))],
149 "memory_size\t$dst">,
150 Requires<[HasAddr32]>;
151 def MEMORY_SIZE_I64 : I<(outs I64:$dst), (ins),
152 [(set I64:$dst, (int_wasm_memory_size))],
153 "memory_size\t$dst">,
154 Requires<[HasAddr64]>;
157 def GROW_MEMORY_I32 : I<(outs), (ins I32:$delta),
158 [(int_wasm_grow_memory I32:$delta)],
159 "grow_memory\t$delta">,
160 Requires<[HasAddr32]>;
161 def GROW_MEMORY_I64 : I<(outs), (ins I64:$delta),
162 [(int_wasm_grow_memory I64:$delta)],
163 "grow_memory\t$delta">,
164 Requires<[HasAddr64]>;
166 } // Defs = [ARGUMENTS]