1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file implements the WebAssemblyTargetLowering class.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "WebAssemblyTargetObjectFile.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/DiagnosticPrinter.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "wasm-lower"
40 // Diagnostic information for unimplemented or unsupported feature reporting.
41 // TODO: This code is copied from BPF and AMDGPU; consider factoring it out
43 class DiagnosticInfoUnsupported final : public DiagnosticInfo {
45 // Debug location where this diagnostic is triggered.
47 const Twine &Description;
53 static int getKindID() {
55 KindID = llvm::getNextAvailablePluginDiagnosticKind();
60 DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
62 : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
63 Description(Desc), Fn(Fn), Value(Value) {}
65 void print(DiagnosticPrinter &DP) const override {
67 raw_string_ostream OS(Str);
70 auto DIL = DLoc.get();
71 StringRef Filename = DIL->getFilename();
72 unsigned Line = DIL->getLine();
73 unsigned Column = DIL->getColumn();
74 OS << Filename << ':' << Line << ':' << Column << ' ';
77 OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
86 static bool classof(const DiagnosticInfo *DI) {
87 return DI->getKind() == getKindID();
91 int DiagnosticInfoUnsupported::KindID = 0;
92 } // end anonymous namespace
94 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
95 const TargetMachine &TM, const WebAssemblySubtarget &STI)
96 : TargetLowering(TM), Subtarget(&STI) {
97 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
99 // Booleans always contain 0 or 1.
100 setBooleanContents(ZeroOrOneBooleanContent);
101 // WebAssembly does not produce floating-point exceptions on normal floating
103 setHasFloatingPointExceptions(false);
104 // We don't know the microarchitecture here, so just reduce register pressure.
105 setSchedulingPreference(Sched::RegPressure);
106 // Tell ISel that we have a stack pointer.
107 setStackPointerRegisterToSaveRestore(
108 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
109 // Set up the register classes.
110 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
111 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
112 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
113 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
114 // Compute derived properties from the register classes.
115 computeRegisterProperties(Subtarget->getRegisterInfo());
117 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
118 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
119 setOperationAction(ISD::JumpTable, MVTPtr, Custom);
121 for (auto T : {MVT::f32, MVT::f64}) {
122 // Don't expand the floating-point types to constant pools.
123 setOperationAction(ISD::ConstantFP, T, Legal);
124 // Expand floating-point comparisons.
125 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
126 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
127 setCondCodeAction(CC, T, Expand);
128 // Expand floating-point library function operators.
129 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW})
130 setOperationAction(Op, T, Expand);
131 // Note supported floating-point library function operators that otherwise
132 // default to expand.
134 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
135 setOperationAction(Op, T, Legal);
136 // Support minnan and maxnan, which otherwise default to expand.
137 setOperationAction(ISD::FMINNAN, T, Legal);
138 setOperationAction(ISD::FMAXNAN, T, Legal);
141 for (auto T : {MVT::i32, MVT::i64}) {
142 // Expand unavailable integer operations.
144 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
145 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
146 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
148 setOperationAction(Op, T, Expand);
152 // As a special case, these operators use the type to mean the type to
154 for (auto T : {MVT::i1, MVT::i8, MVT::i16})
155 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
157 // Dynamic stack allocation: use the default expansion.
158 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
159 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
160 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
162 // Expand these forms; we pattern-match the forms that we can handle in isel.
163 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
164 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
165 setOperationAction(Op, T, Expand);
167 // We have custom switch handling.
168 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
170 // WebAssembly doesn't have:
171 // - Floating-point extending loads.
172 // - Floating-point truncating stores.
173 // - i1 extending loads.
174 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f64, Expand);
175 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
176 for (auto T : MVT::integer_valuetypes())
177 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
178 setLoadExtAction(Ext, T, MVT::i1, Promote);
180 // Trap lowers to wasm unreachable
181 setOperationAction(ISD::TRAP, MVT::Other, Legal);
184 FastISel *WebAssemblyTargetLowering::createFastISel(
185 FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
186 return WebAssembly::createFastISel(FuncInfo, LibInfo);
189 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
190 const GlobalAddressSDNode * /*GA*/) const {
191 // The WebAssembly target doesn't support folding offsets into global
196 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
198 return VT.getSimpleVT();
202 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
203 switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
204 case WebAssemblyISD::FIRST_NUMBER:
206 #define HANDLE_NODETYPE(NODE) \
207 case WebAssemblyISD::NODE: \
208 return "WebAssemblyISD::" #NODE;
209 #include "WebAssemblyISD.def"
210 #undef HANDLE_NODETYPE
215 std::pair<unsigned, const TargetRegisterClass *>
216 WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
217 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
218 // First, see if this is a constraint that directly corresponds to a
219 // WebAssembly register class.
220 if (Constraint.size() == 1) {
221 switch (Constraint[0]) {
224 return std::make_pair(0U, &WebAssembly::I32RegClass);
226 return std::make_pair(0U, &WebAssembly::I64RegClass);
233 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
236 bool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
237 // Assume ctz is a relatively cheap operation.
241 bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
242 // Assume clz is a relatively cheap operation.
246 //===----------------------------------------------------------------------===//
247 // WebAssembly Lowering private implementation.
248 //===----------------------------------------------------------------------===//
250 //===----------------------------------------------------------------------===//
252 //===----------------------------------------------------------------------===//
254 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
255 MachineFunction &MF = DAG.getMachineFunction();
256 DAG.getContext()->diagnose(
257 DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
261 WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
262 SmallVectorImpl<SDValue> &InVals) const {
263 SelectionDAG &DAG = CLI.DAG;
265 SDValue Chain = CLI.Chain;
266 SDValue Callee = CLI.Callee;
267 MachineFunction &MF = DAG.getMachineFunction();
269 CallingConv::ID CallConv = CLI.CallConv;
270 if (CallConv != CallingConv::C && CallConv != CallingConv::Fast &&
271 CallConv != CallingConv::Cold)
273 "WebAssembly doesn't support language-specific or target-specific "
274 "calling conventions yet");
275 if (CLI.IsPatchPoint)
276 fail(DL, DAG, "WebAssembly doesn't support patch point yet");
278 // WebAssembly doesn't currently support explicit tail calls. If they are
279 // required, fail. Otherwise, just disable them.
280 if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
281 MF.getTarget().Options.GuaranteedTailCallOpt) ||
282 (CLI.CS && CLI.CS->isMustTailCall()))
283 fail(DL, DAG, "WebAssembly doesn't support tail call yet");
284 CLI.IsTailCall = false;
286 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
288 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
290 fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
292 bool IsVarArg = CLI.IsVarArg;
294 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
296 // Analyze operands of the call, assigning locations to each operand.
297 SmallVector<CCValAssign, 16> ArgLocs;
298 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
299 unsigned NumBytes = CCInfo.getNextStackOffset();
301 auto PtrVT = getPointerTy(MF.getDataLayout());
302 auto Zero = DAG.getConstant(0, DL, PtrVT, true);
303 auto NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
304 Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
306 SmallVector<SDValue, 16> Ops;
307 Ops.push_back(Chain);
308 Ops.push_back(Callee);
309 Ops.append(OutVals.begin(), OutVals.end());
311 SmallVector<EVT, 8> Tys;
312 for (const auto &In : Ins)
313 Tys.push_back(In.VT);
314 Tys.push_back(MVT::Other);
315 SDVTList TyList = DAG.getVTList(Tys);
317 DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
322 InVals.push_back(Res);
323 Chain = Res.getValue(1);
326 Chain = DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), DL);
331 bool WebAssemblyTargetLowering::CanLowerReturn(
332 CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
333 const SmallVectorImpl<ISD::OutputArg> &Outs,
334 LLVMContext & /*Context*/) const {
335 // WebAssembly can't currently handle returning tuples.
336 return Outs.size() <= 1;
339 SDValue WebAssemblyTargetLowering::LowerReturn(
340 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
341 const SmallVectorImpl<ISD::OutputArg> &Outs,
342 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
343 SelectionDAG &DAG) const {
344 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
345 if (CallConv != CallingConv::C)
346 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
348 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
350 SmallVector<SDValue, 4> RetOps(1, Chain);
351 RetOps.append(OutVals.begin(), OutVals.end());
352 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
354 // Record the number and types of the return values.
355 for (const ISD::OutputArg &Out : Outs) {
356 if (Out.Flags.isByVal())
357 fail(DL, DAG, "WebAssembly hasn't implemented byval results");
358 if (Out.Flags.isInAlloca())
359 fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
360 if (Out.Flags.isNest())
361 fail(DL, DAG, "WebAssembly hasn't implemented nest results");
362 if (Out.Flags.isInConsecutiveRegs())
363 fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
364 if (Out.Flags.isInConsecutiveRegsLast())
365 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
367 fail(DL, DAG, "WebAssembly doesn't support non-fixed results yet");
373 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
374 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
375 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
376 SmallVectorImpl<SDValue> &InVals) const {
377 MachineFunction &MF = DAG.getMachineFunction();
379 if (CallConv != CallingConv::C)
380 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
382 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
384 // Set up the incoming ARGUMENTS value, which serves to represent the liveness
385 // of the incoming values before they're represented by virtual registers.
386 MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
388 for (const ISD::InputArg &In : Ins) {
389 if (In.Flags.isByVal())
390 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
391 if (In.Flags.isInAlloca())
392 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
393 if (In.Flags.isNest())
394 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
395 if (In.Flags.isInConsecutiveRegs())
396 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
397 if (In.Flags.isInConsecutiveRegsLast())
398 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
399 // Ignore In.getOrigAlign() because all our arguments are passed in
403 ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
404 DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
405 : DAG.getNode(ISD::UNDEF, DL, In.VT));
407 // Record the number and types of arguments.
408 MF.getInfo<WebAssemblyFunctionInfo>()->addParam(In.VT);
414 //===----------------------------------------------------------------------===//
415 // Custom lowering hooks.
416 //===----------------------------------------------------------------------===//
418 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
419 SelectionDAG &DAG) const {
420 switch (Op.getOpcode()) {
422 llvm_unreachable("unimplemented operation lowering");
424 case ISD::GlobalAddress:
425 return LowerGlobalAddress(Op, DAG);
426 case ISD::ExternalSymbol:
427 return LowerExternalSymbol(Op, DAG);
429 return LowerJumpTable(Op, DAG);
431 return LowerBR_JT(Op, DAG);
435 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
436 SelectionDAG &DAG) const {
438 const auto *GA = cast<GlobalAddressSDNode>(Op);
439 EVT VT = Op.getValueType();
440 assert(GA->getOffset() == 0 &&
441 "offsets on global addresses are forbidden by isOffsetFoldingLegal");
442 assert(GA->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
443 if (GA->getAddressSpace() != 0)
444 fail(DL, DAG, "WebAssembly only expects the 0 address space");
445 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
446 DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
450 WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
451 SelectionDAG &DAG) const {
453 const auto *ES = cast<ExternalSymbolSDNode>(Op);
454 EVT VT = Op.getValueType();
455 assert(ES->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
456 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
457 DAG.getTargetExternalSymbol(ES->getSymbol(), VT));
460 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
461 SelectionDAG &DAG) const {
462 // There's no need for a Wrapper node because we always incorporate a jump
463 // table operand into a TABLESWITCH instruction, rather than ever
464 // materializing it in a register.
465 const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
466 return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
467 JT->getTargetFlags());
470 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
471 SelectionDAG &DAG) const {
473 SDValue Chain = Op.getOperand(0);
474 const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
475 SDValue Index = Op.getOperand(2);
476 assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
478 SmallVector<SDValue, 8> Ops;
479 Ops.push_back(Chain);
480 Ops.push_back(Index);
482 MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
483 const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
485 // TODO: For now, we just pick something arbitrary for a default case for now.
486 // We really want to sniff out the guard and put in the real default case (and
487 // delete the guard).
488 Ops.push_back(DAG.getBasicBlock(MBBs[0]));
490 // Add an operand for each case.
491 for (auto MBB : MBBs)
492 Ops.push_back(DAG.getBasicBlock(MBB));
494 return DAG.getNode(WebAssemblyISD::TABLESWITCH, DL, MVT::Other, Ops);
497 //===----------------------------------------------------------------------===//
498 // WebAssembly Optimization Hooks
499 //===----------------------------------------------------------------------===//
501 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
502 const GlobalValue *GV, SectionKind /*Kind*/, Mangler & /*Mang*/,
503 const TargetMachine & /*TM*/) const {
504 // TODO: Be more sophisticated than this.
505 return isa<Function>(GV) ? getTextSection() : getDataSection();