1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
192 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
196 def STDAtomic3 : SDTypeProfile<1, 3, [
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
199 def STDAtomic2 : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
203 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 1, constraints>;
205 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 2, constraints>;
208 //===----------------------------------------------------------------------===//
209 // Selection DAG Node Properties.
211 // Note: These are hard coded into tblgen.
213 class SDNodeProperty;
214 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
215 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
216 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
217 def SDNPOutFlag : SDNodeProperty; // Write a flag result
218 def SDNPInFlag : SDNodeProperty; // Read a flag operand
219 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
220 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
221 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
222 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
223 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
225 //===----------------------------------------------------------------------===//
226 // Selection DAG Node definitions.
228 class SDNode<string opcode, SDTypeProfile typeprof,
229 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
230 string Opcode = opcode;
231 string SDClass = sdclass;
232 list<SDNodeProperty> Properties = props;
233 SDTypeProfile TypeProfile = typeprof;
242 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
243 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
244 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
245 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
246 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
247 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
248 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
249 "GlobalAddressSDNode">;
250 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
251 "GlobalAddressSDNode">;
252 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
253 "GlobalAddressSDNode">;
254 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
255 "GlobalAddressSDNode">;
256 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
257 "ConstantPoolSDNode">;
258 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
259 "ConstantPoolSDNode">;
260 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
262 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
264 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
266 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
268 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
269 "ExternalSymbolSDNode">;
270 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
271 "ExternalSymbolSDNode">;
273 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
274 [SDNPCommutative, SDNPAssociative]>;
275 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
276 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
277 [SDNPCommutative, SDNPAssociative]>;
278 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
279 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
280 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
281 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
282 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
283 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
284 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
285 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
286 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
287 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
288 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
289 def and : SDNode<"ISD::AND" , SDTIntBinOp,
290 [SDNPCommutative, SDNPAssociative]>;
291 def or : SDNode<"ISD::OR" , SDTIntBinOp,
292 [SDNPCommutative, SDNPAssociative]>;
293 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
294 [SDNPCommutative, SDNPAssociative]>;
295 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
296 [SDNPCommutative, SDNPOutFlag]>;
297 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
298 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
299 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
301 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
302 [SDNPOutFlag, SDNPInFlag]>;
304 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
305 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
306 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
307 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
308 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
309 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
310 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
311 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
312 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
313 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
314 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
315 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
318 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
319 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
320 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
321 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
322 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
323 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
324 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
325 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
326 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
327 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
328 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
329 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
330 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
331 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
332 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
334 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
335 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
336 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
338 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
339 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
340 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
341 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
343 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
344 def select : SDNode<"ISD::SELECT" , SDTSelect>;
345 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
346 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
348 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
349 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
350 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
351 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
352 def trap : SDNode<"ISD::TRAP" , SDTNone,
353 [SDNPHasChain, SDNPSideEffect]>;
355 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
356 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
358 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
359 [SDNPHasChain, SDNPSideEffect]>;
361 // Do not use atomic_* directly, use atomic_*_size (see below)
362 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3,
363 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
364 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2,
365 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
366 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
368 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2,
369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
370 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
372 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
374 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
376 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2,
377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
378 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
380 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
382 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
384 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
387 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
388 // and truncst (see below).
389 def ld : SDNode<"ISD::LOAD" , SDTLoad,
390 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
391 def st : SDNode<"ISD::STORE" , SDTStore,
392 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
393 def ist : SDNode<"ISD::STORE" , SDTIStore,
394 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
396 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
397 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
398 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
400 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
401 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
402 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
403 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
405 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
406 SDTypeProfile<1, 2, []>>;
407 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
408 SDTypeProfile<1, 3, []>>;
410 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
411 // these internally. Don't reference these directly.
412 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
413 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
415 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
416 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
418 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
419 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
422 //===----------------------------------------------------------------------===//
423 // Selection DAG Condition Codes
425 class CondCode; // ISD::CondCode enums
426 def SETOEQ : CondCode; def SETOGT : CondCode;
427 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
428 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
429 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
430 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
432 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
433 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
436 //===----------------------------------------------------------------------===//
437 // Selection DAG Node Transformation Functions.
439 // This mechanism allows targets to manipulate nodes in the output DAG once a
440 // match has been formed. This is typically used to manipulate immediate
443 class SDNodeXForm<SDNode opc, code xformFunction> {
445 code XFormFunction = xformFunction;
448 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
451 //===----------------------------------------------------------------------===//
452 // Selection DAG Pattern Fragments.
454 // Pattern fragments are reusable chunks of dags that match specific things.
455 // They can take arguments and have C++ predicates that control whether they
456 // match. They are intended to make the patterns for common instructions more
457 // compact and readable.
460 /// PatFrag - Represents a pattern fragment. This can match something on the
461 /// DAG, frame a single node to multiply nested other fragments.
463 class PatFrag<dag ops, dag frag, code pred = [{}],
464 SDNodeXForm xform = NOOP_SDNodeXForm> {
467 code Predicate = pred;
468 SDNodeXForm OperandTransform = xform;
471 // PatLeaf's are pattern fragments that have no operands. This is just a helper
472 // to define immediates and other common things concisely.
473 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
474 : PatFrag<(ops), frag, pred, xform>;
478 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
479 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
481 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
482 def immAllOnesV: PatLeaf<(build_vector), [{
483 return ISD::isBuildVectorAllOnes(N);
485 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
486 return ISD::isBuildVectorAllOnes(N);
488 def immAllZerosV: PatLeaf<(build_vector), [{
489 return ISD::isBuildVectorAllZeros(N);
491 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
492 return ISD::isBuildVectorAllZeros(N);
497 // Other helper fragments.
498 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
499 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
500 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
501 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
504 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
505 LoadSDNode *LD = cast<LoadSDNode>(N);
506 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
507 LD->getAddressingMode() == ISD::UNINDEXED;
510 // extending load fragments.
511 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
512 LoadSDNode *LD = cast<LoadSDNode>(N);
513 return LD->getExtensionType() == ISD::EXTLOAD &&
514 LD->getAddressingMode() == ISD::UNINDEXED &&
515 LD->getMemoryVT() == MVT::i1;
517 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
518 LoadSDNode *LD = cast<LoadSDNode>(N);
519 return LD->getExtensionType() == ISD::EXTLOAD &&
520 LD->getAddressingMode() == ISD::UNINDEXED &&
521 LD->getMemoryVT() == MVT::i8;
523 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
524 LoadSDNode *LD = cast<LoadSDNode>(N);
525 return LD->getExtensionType() == ISD::EXTLOAD &&
526 LD->getAddressingMode() == ISD::UNINDEXED &&
527 LD->getMemoryVT() == MVT::i16;
529 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
530 LoadSDNode *LD = cast<LoadSDNode>(N);
531 return LD->getExtensionType() == ISD::EXTLOAD &&
532 LD->getAddressingMode() == ISD::UNINDEXED &&
533 LD->getMemoryVT() == MVT::i32;
535 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
536 LoadSDNode *LD = cast<LoadSDNode>(N);
537 return LD->getExtensionType() == ISD::EXTLOAD &&
538 LD->getAddressingMode() == ISD::UNINDEXED &&
539 LD->getMemoryVT() == MVT::f32;
541 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
542 LoadSDNode *LD = cast<LoadSDNode>(N);
543 return LD->getExtensionType() == ISD::EXTLOAD &&
544 LD->getAddressingMode() == ISD::UNINDEXED &&
545 LD->getMemoryVT() == MVT::f64;
548 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
549 LoadSDNode *LD = cast<LoadSDNode>(N);
550 return LD->getExtensionType() == ISD::SEXTLOAD &&
551 LD->getAddressingMode() == ISD::UNINDEXED &&
552 LD->getMemoryVT() == MVT::i1;
554 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
555 LoadSDNode *LD = cast<LoadSDNode>(N);
556 return LD->getExtensionType() == ISD::SEXTLOAD &&
557 LD->getAddressingMode() == ISD::UNINDEXED &&
558 LD->getMemoryVT() == MVT::i8;
560 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
561 LoadSDNode *LD = cast<LoadSDNode>(N);
562 return LD->getExtensionType() == ISD::SEXTLOAD &&
563 LD->getAddressingMode() == ISD::UNINDEXED &&
564 LD->getMemoryVT() == MVT::i16;
566 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
567 LoadSDNode *LD = cast<LoadSDNode>(N);
568 return LD->getExtensionType() == ISD::SEXTLOAD &&
569 LD->getAddressingMode() == ISD::UNINDEXED &&
570 LD->getMemoryVT() == MVT::i32;
573 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
574 LoadSDNode *LD = cast<LoadSDNode>(N);
575 return LD->getExtensionType() == ISD::ZEXTLOAD &&
576 LD->getAddressingMode() == ISD::UNINDEXED &&
577 LD->getMemoryVT() == MVT::i1;
579 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
580 LoadSDNode *LD = cast<LoadSDNode>(N);
581 return LD->getExtensionType() == ISD::ZEXTLOAD &&
582 LD->getAddressingMode() == ISD::UNINDEXED &&
583 LD->getMemoryVT() == MVT::i8;
585 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
586 LoadSDNode *LD = cast<LoadSDNode>(N);
587 return LD->getExtensionType() == ISD::ZEXTLOAD &&
588 LD->getAddressingMode() == ISD::UNINDEXED &&
589 LD->getMemoryVT() == MVT::i16;
591 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
592 LoadSDNode *LD = cast<LoadSDNode>(N);
593 return LD->getExtensionType() == ISD::ZEXTLOAD &&
594 LD->getAddressingMode() == ISD::UNINDEXED &&
595 LD->getMemoryVT() == MVT::i32;
599 def store : PatFrag<(ops node:$val, node:$ptr),
600 (st node:$val, node:$ptr), [{
601 StoreSDNode *ST = cast<StoreSDNode>(N);
602 return !ST->isTruncatingStore() &&
603 ST->getAddressingMode() == ISD::UNINDEXED;
606 // truncstore fragments.
607 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
608 (st node:$val, node:$ptr), [{
609 StoreSDNode *ST = cast<StoreSDNode>(N);
610 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
611 ST->getAddressingMode() == ISD::UNINDEXED;
613 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
614 (st node:$val, node:$ptr), [{
615 StoreSDNode *ST = cast<StoreSDNode>(N);
616 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
617 ST->getAddressingMode() == ISD::UNINDEXED;
619 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
620 (st node:$val, node:$ptr), [{
621 StoreSDNode *ST = cast<StoreSDNode>(N);
622 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
623 ST->getAddressingMode() == ISD::UNINDEXED;
625 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
626 (st node:$val, node:$ptr), [{
627 StoreSDNode *ST = cast<StoreSDNode>(N);
628 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
629 ST->getAddressingMode() == ISD::UNINDEXED;
631 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
632 (st node:$val, node:$ptr), [{
633 StoreSDNode *ST = cast<StoreSDNode>(N);
634 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
635 ST->getAddressingMode() == ISD::UNINDEXED;
638 // indexed store fragments.
639 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
640 (ist node:$val, node:$base, node:$offset), [{
641 StoreSDNode *ST = cast<StoreSDNode>(N);
642 ISD::MemIndexedMode AM = ST->getAddressingMode();
643 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
644 !ST->isTruncatingStore();
647 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
648 (ist node:$val, node:$base, node:$offset), [{
649 StoreSDNode *ST = cast<StoreSDNode>(N);
650 ISD::MemIndexedMode AM = ST->getAddressingMode();
651 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
652 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
654 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
655 (ist node:$val, node:$base, node:$offset), [{
656 StoreSDNode *ST = cast<StoreSDNode>(N);
657 ISD::MemIndexedMode AM = ST->getAddressingMode();
658 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
659 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
661 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
662 (ist node:$val, node:$base, node:$offset), [{
663 StoreSDNode *ST = cast<StoreSDNode>(N);
664 ISD::MemIndexedMode AM = ST->getAddressingMode();
665 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
666 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
668 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
669 (ist node:$val, node:$base, node:$offset), [{
670 StoreSDNode *ST = cast<StoreSDNode>(N);
671 ISD::MemIndexedMode AM = ST->getAddressingMode();
672 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
673 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
675 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
676 (ist node:$val, node:$base, node:$offset), [{
677 StoreSDNode *ST = cast<StoreSDNode>(N);
678 ISD::MemIndexedMode AM = ST->getAddressingMode();
679 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
680 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
683 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
684 (ist node:$val, node:$ptr, node:$offset), [{
685 StoreSDNode *ST = cast<StoreSDNode>(N);
686 ISD::MemIndexedMode AM = ST->getAddressingMode();
687 return !ST->isTruncatingStore() &&
688 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
691 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
692 (ist node:$val, node:$base, node:$offset), [{
693 StoreSDNode *ST = cast<StoreSDNode>(N);
694 ISD::MemIndexedMode AM = ST->getAddressingMode();
695 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
696 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
698 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
699 (ist node:$val, node:$base, node:$offset), [{
700 StoreSDNode *ST = cast<StoreSDNode>(N);
701 ISD::MemIndexedMode AM = ST->getAddressingMode();
702 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
703 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
705 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
706 (ist node:$val, node:$base, node:$offset), [{
707 StoreSDNode *ST = cast<StoreSDNode>(N);
708 ISD::MemIndexedMode AM = ST->getAddressingMode();
709 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
710 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
712 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
713 (ist node:$val, node:$base, node:$offset), [{
714 StoreSDNode *ST = cast<StoreSDNode>(N);
715 ISD::MemIndexedMode AM = ST->getAddressingMode();
716 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
717 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
719 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
720 (ist node:$val, node:$base, node:$offset), [{
721 StoreSDNode *ST = cast<StoreSDNode>(N);
722 ISD::MemIndexedMode AM = ST->getAddressingMode();
723 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
724 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
728 def atomic_cmp_swap_8 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
729 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
730 AtomicSDNode* V = cast<AtomicSDNode>(N);
731 return V->getValueType(0) == MVT::i8;
733 def atomic_cmp_swap_16 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
734 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
735 AtomicSDNode* V = cast<AtomicSDNode>(N);
736 return V->getValueType(0) == MVT::i16;
738 def atomic_cmp_swap_32 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
739 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
740 AtomicSDNode* V = cast<AtomicSDNode>(N);
741 return V->getValueType(0) == MVT::i32;
743 def atomic_cmp_swap_64 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
744 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
745 AtomicSDNode* V = cast<AtomicSDNode>(N);
746 return V->getValueType(0) == MVT::i64;
749 def atomic_load_add_8 : PatFrag<(ops node:$ptr, node:$inc),
750 (atomic_load_add node:$ptr, node:$inc), [{
751 AtomicSDNode* V = cast<AtomicSDNode>(N);
752 return V->getValueType(0) == MVT::i8;
754 def atomic_load_add_16 : PatFrag<(ops node:$ptr, node:$inc),
755 (atomic_load_add node:$ptr, node:$inc), [{
756 AtomicSDNode* V = cast<AtomicSDNode>(N);
757 return V->getValueType(0) == MVT::i16;
759 def atomic_load_add_32 : PatFrag<(ops node:$ptr, node:$inc),
760 (atomic_load_add node:$ptr, node:$inc), [{
761 AtomicSDNode* V = cast<AtomicSDNode>(N);
762 return V->getValueType(0) == MVT::i32;
764 def atomic_load_add_64 : PatFrag<(ops node:$ptr, node:$inc),
765 (atomic_load_add node:$ptr, node:$inc), [{
766 AtomicSDNode* V = cast<AtomicSDNode>(N);
767 return V->getValueType(0) == MVT::i64;
770 def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
771 (atomic_swap node:$ptr, node:$inc), [{
772 AtomicSDNode* V = cast<AtomicSDNode>(N);
773 return V->getValueType(0) == MVT::i8;
775 def atomic_swap_16 : PatFrag<(ops node:$ptr, node:$inc),
776 (atomic_swap node:$ptr, node:$inc), [{
777 AtomicSDNode* V = cast<AtomicSDNode>(N);
778 return V->getValueType(0) == MVT::i16;
780 def atomic_swap_32 : PatFrag<(ops node:$ptr, node:$inc),
781 (atomic_swap node:$ptr, node:$inc), [{
782 AtomicSDNode* V = cast<AtomicSDNode>(N);
783 return V->getValueType(0) == MVT::i32;
785 def atomic_swap_64 : PatFrag<(ops node:$ptr, node:$inc),
786 (atomic_swap node:$ptr, node:$inc), [{
787 AtomicSDNode* V = cast<AtomicSDNode>(N);
788 return V->getValueType(0) == MVT::i64;
793 // setcc convenience fragments.
794 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
795 (setcc node:$lhs, node:$rhs, SETOEQ)>;
796 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
797 (setcc node:$lhs, node:$rhs, SETOGT)>;
798 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
799 (setcc node:$lhs, node:$rhs, SETOGE)>;
800 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
801 (setcc node:$lhs, node:$rhs, SETOLT)>;
802 def setole : PatFrag<(ops node:$lhs, node:$rhs),
803 (setcc node:$lhs, node:$rhs, SETOLE)>;
804 def setone : PatFrag<(ops node:$lhs, node:$rhs),
805 (setcc node:$lhs, node:$rhs, SETONE)>;
806 def seto : PatFrag<(ops node:$lhs, node:$rhs),
807 (setcc node:$lhs, node:$rhs, SETO)>;
808 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
809 (setcc node:$lhs, node:$rhs, SETUO)>;
810 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
811 (setcc node:$lhs, node:$rhs, SETUEQ)>;
812 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
813 (setcc node:$lhs, node:$rhs, SETUGT)>;
814 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
815 (setcc node:$lhs, node:$rhs, SETUGE)>;
816 def setult : PatFrag<(ops node:$lhs, node:$rhs),
817 (setcc node:$lhs, node:$rhs, SETULT)>;
818 def setule : PatFrag<(ops node:$lhs, node:$rhs),
819 (setcc node:$lhs, node:$rhs, SETULE)>;
820 def setune : PatFrag<(ops node:$lhs, node:$rhs),
821 (setcc node:$lhs, node:$rhs, SETUNE)>;
822 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
823 (setcc node:$lhs, node:$rhs, SETEQ)>;
824 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
825 (setcc node:$lhs, node:$rhs, SETGT)>;
826 def setge : PatFrag<(ops node:$lhs, node:$rhs),
827 (setcc node:$lhs, node:$rhs, SETGE)>;
828 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
829 (setcc node:$lhs, node:$rhs, SETLT)>;
830 def setle : PatFrag<(ops node:$lhs, node:$rhs),
831 (setcc node:$lhs, node:$rhs, SETLE)>;
832 def setne : PatFrag<(ops node:$lhs, node:$rhs),
833 (setcc node:$lhs, node:$rhs, SETNE)>;
835 //===----------------------------------------------------------------------===//
836 // Selection DAG Pattern Support.
838 // Patterns are what are actually matched against the target-flavored
839 // instruction selection DAG. Instructions defined by the target implicitly
840 // define patterns in most cases, but patterns can also be explicitly added when
841 // an operation is defined by a sequence of instructions (e.g. loading a large
842 // immediate value on RISC targets that do not support immediates as large as
846 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
847 dag PatternToMatch = patternToMatch;
848 list<dag> ResultInstrs = resultInstrs;
849 list<Predicate> Predicates = []; // See class Instruction in Target.td.
850 int AddedComplexity = 0; // See class Instruction in Target.td.
853 // Pat - A simple (but common) form of a pattern, which produces a simple result
854 // not needing a full list.
855 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
857 //===----------------------------------------------------------------------===//
858 // Complex pattern definitions.
862 // Pass the parent Operand as root to CP function rather
863 // than the root of the sub-DAG
864 def CPAttrParentAsRoot : CPAttribute;
866 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
867 // in C++. NumOperands is the number of operands returned by the select function;
868 // SelectFunc is the name of the function used to pattern match the max. pattern;
869 // RootNodes are the list of possible root nodes of the sub-dags to match.
870 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
872 class ComplexPattern<ValueType ty, int numops, string fn,
873 list<SDNode> roots = [], list<SDNodeProperty> props = [],
874 list<CPAttribute> attrs = []> {
876 int NumOperands = numops;
877 string SelectFunc = fn;
878 list<SDNode> RootNodes = roots;
879 list<SDNodeProperty> Properties = props;
880 list<CPAttribute> Attributes = attrs;
883 //===----------------------------------------------------------------------===//
886 def SDT_dwarf_loc : SDTypeProfile<0, 3,
887 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
888 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;