1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 //===----------------------------------------------------------------------===//
64 // Selection DAG Type Profile definitions.
66 // These use the constraints defined above to describe the type requirements of
67 // the various nodes. These are not hard coded into tblgen, allowing targets to
68 // add their own if needed.
71 // SDTypeProfile - This profile describes the type requirements of a Selection
73 class SDTypeProfile<int numresults, int numoperands,
74 list<SDTypeConstraint> constraints> {
75 int NumResults = numresults;
76 int NumOperands = numoperands;
77 list<SDTypeConstraint> Constraints = constraints;
81 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
82 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
83 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
84 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
85 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
86 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
88 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
89 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
91 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
92 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
94 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
95 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
97 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
98 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
100 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
101 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
103 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
104 SDTCisSameAs<0, 1>, SDTCisInt<0>
106 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
107 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
109 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
110 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
112 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
113 SDTCisSameAs<0, 1>, SDTCisFP<0>
115 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
116 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
118 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
119 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
122 SDTCisFP<0>, SDTCisInt<1>
124 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
125 SDTCisInt<0>, SDTCisFP<1>
127 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
128 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
129 SDTCisVTSmallerThanOp<2, 1>
132 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
133 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
136 def SDTSelect : SDTypeProfile<1, 3, [ // select
137 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
140 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
141 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
145 def SDTBr : SDTypeProfile<0, 1, [ // br
149 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
150 SDTCisInt<0>, SDTCisVT<1, OtherVT>
153 def SDTBrind : SDTypeProfile<0, 1, [ // brind
157 def SDTRet : SDTypeProfile<0, 0, []>; // ret
159 def SDTLoad : SDTypeProfile<1, 1, [ // load
163 def SDTStore : SDTypeProfile<0, 2, [ // store
167 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
168 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
171 def SDTVecShuffle : SDTypeProfile<1, 3, [
172 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
175 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
176 SDTypeProfile<0, 1, constraints>;
177 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
178 SDTypeProfile<0, 2, constraints>;
180 //===----------------------------------------------------------------------===//
181 // Selection DAG Node Properties.
183 // Note: These are hard coded into tblgen.
185 class SDNodeProperty;
186 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
187 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
188 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
189 def SDNPOutFlag : SDNodeProperty; // Write a flag result
190 def SDNPInFlag : SDNodeProperty; // Read a flag operand
191 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
193 //===----------------------------------------------------------------------===//
194 // Selection DAG Node definitions.
196 class SDNode<string opcode, SDTypeProfile typeprof,
197 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
198 string Opcode = opcode;
199 string SDClass = sdclass;
200 list<SDNodeProperty> Properties = props;
201 SDTypeProfile TypeProfile = typeprof;
210 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
211 def fpimm : SDNode<"ISD::TargetConstantFP",
212 SDTFPLeaf, [], "ConstantFPSDNode">;
213 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
214 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
215 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
216 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
217 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
218 "GlobalAddressSDNode">;
219 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
220 "GlobalAddressSDNode">;
221 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
222 "GlobalAddressSDNode">;
223 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
224 "GlobalAddressSDNode">;
225 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
226 "ConstantPoolSDNode">;
227 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
228 "ConstantPoolSDNode">;
229 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
231 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
233 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
235 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
237 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
238 "ExternalSymbolSDNode">;
239 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
240 "ExternalSymbolSDNode">;
242 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
243 [SDNPCommutative, SDNPAssociative]>;
244 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
245 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
246 [SDNPCommutative, SDNPAssociative]>;
247 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
248 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
249 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
250 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
251 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
252 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
253 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
254 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
255 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
256 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
257 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
258 def and : SDNode<"ISD::AND" , SDTIntBinOp,
259 [SDNPCommutative, SDNPAssociative]>;
260 def or : SDNode<"ISD::OR" , SDTIntBinOp,
261 [SDNPCommutative, SDNPAssociative]>;
262 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
263 [SDNPCommutative, SDNPAssociative]>;
264 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
265 [SDNPCommutative, SDNPOutFlag]>;
266 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
267 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
268 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
270 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
271 [SDNPOutFlag, SDNPInFlag]>;
273 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
274 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
275 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
276 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
277 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
278 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
279 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
280 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
281 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
282 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
284 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
285 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
286 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
287 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
288 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
289 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
290 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
291 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
292 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
293 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
295 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
296 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
297 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
299 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
300 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
301 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
302 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
304 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
305 def select : SDNode<"ISD::SELECT" , SDTSelect>;
306 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
308 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
309 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
310 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
311 def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
313 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
314 // and truncst (see below).
315 def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
316 def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
317 def ist : SDNode<"ISD::STORE" , SDTIStore, [SDNPHasChain]>;
319 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
320 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
321 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
323 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
324 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
325 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
326 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
328 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
329 SDTypeProfile<1, 2, []>>;
330 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
331 SDTypeProfile<1, 3, []>>;
333 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
334 // these internally. Don't reference these directly.
335 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
336 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
338 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
339 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
341 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
342 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
345 //===----------------------------------------------------------------------===//
346 // Selection DAG Condition Codes
348 class CondCode; // ISD::CondCode enums
349 def SETOEQ : CondCode; def SETOGT : CondCode;
350 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
351 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
352 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
353 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
355 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
356 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
359 //===----------------------------------------------------------------------===//
360 // Selection DAG Node Transformation Functions.
362 // This mechanism allows targets to manipulate nodes in the output DAG once a
363 // match has been formed. This is typically used to manipulate immediate
366 class SDNodeXForm<SDNode opc, code xformFunction> {
368 code XFormFunction = xformFunction;
371 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
374 //===----------------------------------------------------------------------===//
375 // Selection DAG Pattern Fragments.
377 // Pattern fragments are reusable chunks of dags that match specific things.
378 // They can take arguments and have C++ predicates that control whether they
379 // match. They are intended to make the patterns for common instructions more
380 // compact and readable.
383 /// PatFrag - Represents a pattern fragment. This can match something on the
384 /// DAG, frame a single node to multiply nested other fragments.
386 class PatFrag<dag ops, dag frag, code pred = [{}],
387 SDNodeXForm xform = NOOP_SDNodeXForm> {
390 code Predicate = pred;
391 SDNodeXForm OperandTransform = xform;
394 // PatLeaf's are pattern fragments that have no operands. This is just a helper
395 // to define immediates and other common things concisely.
396 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
397 : PatFrag<(ops), frag, pred, xform>;
401 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
402 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
404 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
405 def immAllOnesV: PatLeaf<(build_vector), [{
406 return ISD::isBuildVectorAllOnes(N);
408 def immAllZerosV: PatLeaf<(build_vector), [{
409 return ISD::isBuildVectorAllZeros(N);
412 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
413 return ISD::isBuildVectorAllOnes(N);
417 // Other helper fragments.
418 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
419 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
420 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
421 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
424 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
425 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
426 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
427 LD->getAddressingMode() == ISD::UNINDEXED;
431 // extending load fragments.
432 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
433 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
434 return LD->getExtensionType() == ISD::EXTLOAD &&
435 LD->getAddressingMode() == ISD::UNINDEXED &&
436 LD->getLoadedVT() == MVT::i1;
439 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
440 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
441 return LD->getExtensionType() == ISD::EXTLOAD &&
442 LD->getAddressingMode() == ISD::UNINDEXED &&
443 LD->getLoadedVT() == MVT::i8;
446 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
447 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
448 return LD->getExtensionType() == ISD::EXTLOAD &&
449 LD->getAddressingMode() == ISD::UNINDEXED &&
450 LD->getLoadedVT() == MVT::i16;
453 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
454 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
455 return LD->getExtensionType() == ISD::EXTLOAD &&
456 LD->getAddressingMode() == ISD::UNINDEXED &&
457 LD->getLoadedVT() == MVT::i32;
460 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
461 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
462 return LD->getExtensionType() == ISD::EXTLOAD &&
463 LD->getAddressingMode() == ISD::UNINDEXED &&
464 LD->getLoadedVT() == MVT::f32;
467 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
468 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
469 return LD->getExtensionType() == ISD::EXTLOAD &&
470 LD->getAddressingMode() == ISD::UNINDEXED &&
471 LD->getLoadedVT() == MVT::f64;
475 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
476 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
477 return LD->getExtensionType() == ISD::SEXTLOAD &&
478 LD->getAddressingMode() == ISD::UNINDEXED &&
479 LD->getLoadedVT() == MVT::i1;
482 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
483 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
484 return LD->getExtensionType() == ISD::SEXTLOAD &&
485 LD->getAddressingMode() == ISD::UNINDEXED &&
486 LD->getLoadedVT() == MVT::i8;
489 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
490 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
491 return LD->getExtensionType() == ISD::SEXTLOAD &&
492 LD->getAddressingMode() == ISD::UNINDEXED &&
493 LD->getLoadedVT() == MVT::i16;
496 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
497 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
498 return LD->getExtensionType() == ISD::SEXTLOAD &&
499 LD->getAddressingMode() == ISD::UNINDEXED &&
500 LD->getLoadedVT() == MVT::i32;
504 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
505 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
506 return LD->getExtensionType() == ISD::ZEXTLOAD &&
507 LD->getAddressingMode() == ISD::UNINDEXED &&
508 LD->getLoadedVT() == MVT::i1;
511 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
512 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
513 return LD->getExtensionType() == ISD::ZEXTLOAD &&
514 LD->getAddressingMode() == ISD::UNINDEXED &&
515 LD->getLoadedVT() == MVT::i8;
518 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
519 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
520 return LD->getExtensionType() == ISD::ZEXTLOAD &&
521 LD->getAddressingMode() == ISD::UNINDEXED &&
522 LD->getLoadedVT() == MVT::i16;
525 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
526 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
527 return LD->getExtensionType() == ISD::ZEXTLOAD &&
528 LD->getAddressingMode() == ISD::UNINDEXED &&
529 LD->getLoadedVT() == MVT::i32;
534 def store : PatFrag<(ops node:$val, node:$ptr),
535 (st node:$val, node:$ptr), [{
536 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
537 return !ST->isTruncatingStore() &&
538 ST->getAddressingMode() == ISD::UNINDEXED;
542 // truncstore fragments.
543 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
544 (st node:$val, node:$ptr), [{
545 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
546 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1 &&
547 ST->getAddressingMode() == ISD::UNINDEXED;
550 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
551 (st node:$val, node:$ptr), [{
552 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
553 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8 &&
554 ST->getAddressingMode() == ISD::UNINDEXED;
557 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
558 (st node:$val, node:$ptr), [{
559 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
560 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16 &&
561 ST->getAddressingMode() == ISD::UNINDEXED;
564 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
565 (st node:$val, node:$ptr), [{
566 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
567 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32 &&
568 ST->getAddressingMode() == ISD::UNINDEXED;
571 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
572 (st node:$val, node:$ptr), [{
573 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
574 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32 &&
575 ST->getAddressingMode() == ISD::UNINDEXED;
578 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
579 (st node:$val, node:$ptr), [{
580 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
581 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f64 &&
582 ST->getAddressingMode() == ISD::UNINDEXED;
586 // indexed store fragments.
587 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
588 (ist node:$val, node:$base, node:$offset), [{
589 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
590 ISD::MemIndexedMode AM = ST->getAddressingMode();
591 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
592 !ST->isTruncatingStore();
597 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
598 (ist node:$val, node:$base, node:$offset), [{
599 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
600 ISD::MemIndexedMode AM = ST->getAddressingMode();
601 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
602 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
606 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
607 (ist node:$val, node:$base, node:$offset), [{
608 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
609 ISD::MemIndexedMode AM = ST->getAddressingMode();
610 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
611 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
615 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
616 (ist node:$val, node:$base, node:$offset), [{
617 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
618 ISD::MemIndexedMode AM = ST->getAddressingMode();
619 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
620 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
624 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
625 (ist node:$val, node:$base, node:$offset), [{
626 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
627 ISD::MemIndexedMode AM = ST->getAddressingMode();
628 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
629 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
633 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
634 (ist node:$val, node:$base, node:$offset), [{
635 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
636 ISD::MemIndexedMode AM = ST->getAddressingMode();
637 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
638 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
643 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
644 (ist node:$val, node:$ptr, node:$offset), [{
645 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
646 ISD::MemIndexedMode AM = ST->getAddressingMode();
647 return !ST->isTruncatingStore() &&
648 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
653 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
654 (ist node:$val, node:$base, node:$offset), [{
655 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
656 ISD::MemIndexedMode AM = ST->getAddressingMode();
657 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
658 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
662 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
663 (ist node:$val, node:$base, node:$offset), [{
664 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
665 ISD::MemIndexedMode AM = ST->getAddressingMode();
666 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
667 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
671 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
672 (ist node:$val, node:$base, node:$offset), [{
673 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
674 ISD::MemIndexedMode AM = ST->getAddressingMode();
675 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
676 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
680 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
681 (ist node:$val, node:$base, node:$offset), [{
682 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
683 ISD::MemIndexedMode AM = ST->getAddressingMode();
684 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
685 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
689 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
690 (ist node:$val, node:$base, node:$offset), [{
691 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
692 ISD::MemIndexedMode AM = ST->getAddressingMode();
693 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
694 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
699 // setcc convenience fragments.
700 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
701 (setcc node:$lhs, node:$rhs, SETOEQ)>;
702 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
703 (setcc node:$lhs, node:$rhs, SETOGT)>;
704 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
705 (setcc node:$lhs, node:$rhs, SETOGE)>;
706 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
707 (setcc node:$lhs, node:$rhs, SETOLT)>;
708 def setole : PatFrag<(ops node:$lhs, node:$rhs),
709 (setcc node:$lhs, node:$rhs, SETOLE)>;
710 def setone : PatFrag<(ops node:$lhs, node:$rhs),
711 (setcc node:$lhs, node:$rhs, SETONE)>;
712 def seto : PatFrag<(ops node:$lhs, node:$rhs),
713 (setcc node:$lhs, node:$rhs, SETO)>;
714 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
715 (setcc node:$lhs, node:$rhs, SETUO)>;
716 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
717 (setcc node:$lhs, node:$rhs, SETUEQ)>;
718 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
719 (setcc node:$lhs, node:$rhs, SETUGT)>;
720 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
721 (setcc node:$lhs, node:$rhs, SETUGE)>;
722 def setult : PatFrag<(ops node:$lhs, node:$rhs),
723 (setcc node:$lhs, node:$rhs, SETULT)>;
724 def setule : PatFrag<(ops node:$lhs, node:$rhs),
725 (setcc node:$lhs, node:$rhs, SETULE)>;
726 def setune : PatFrag<(ops node:$lhs, node:$rhs),
727 (setcc node:$lhs, node:$rhs, SETUNE)>;
728 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
729 (setcc node:$lhs, node:$rhs, SETEQ)>;
730 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
731 (setcc node:$lhs, node:$rhs, SETGT)>;
732 def setge : PatFrag<(ops node:$lhs, node:$rhs),
733 (setcc node:$lhs, node:$rhs, SETGE)>;
734 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
735 (setcc node:$lhs, node:$rhs, SETLT)>;
736 def setle : PatFrag<(ops node:$lhs, node:$rhs),
737 (setcc node:$lhs, node:$rhs, SETLE)>;
738 def setne : PatFrag<(ops node:$lhs, node:$rhs),
739 (setcc node:$lhs, node:$rhs, SETNE)>;
741 //===----------------------------------------------------------------------===//
742 // Selection DAG Pattern Support.
744 // Patterns are what are actually matched against the target-flavored
745 // instruction selection DAG. Instructions defined by the target implicitly
746 // define patterns in most cases, but patterns can also be explicitly added when
747 // an operation is defined by a sequence of instructions (e.g. loading a large
748 // immediate value on RISC targets that do not support immediates as large as
752 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
753 dag PatternToMatch = patternToMatch;
754 list<dag> ResultInstrs = resultInstrs;
755 list<Predicate> Predicates = []; // See class Instruction in Target.td.
756 int AddedComplexity = 0; // See class Instruction in Target.td.
759 // Pat - A simple (but common) form of a pattern, which produces a simple result
760 // not needing a full list.
761 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
763 //===----------------------------------------------------------------------===//
764 // Complex pattern definitions.
766 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
767 // in C++. NumOperands is the number of operands returned by the select function;
768 // SelectFunc is the name of the function used to pattern match the max. pattern;
769 // RootNodes are the list of possible root nodes of the sub-dags to match.
770 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
772 class ComplexPattern<ValueType ty, int numops, string fn,
773 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
775 int NumOperands = numops;
776 string SelectFunc = fn;
777 list<SDNode> RootNodes = roots;
778 list<SDNodeProperty> Properties = props;
781 //===----------------------------------------------------------------------===//
784 def SDT_dwarf_loc : SDTypeProfile<0, 3,
785 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
786 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;