1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
192 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
196 def STDAtomic3 : SDTypeProfile<1, 3, [
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
199 def STDAtomic2 : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
203 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 1, constraints>;
205 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 2, constraints>;
208 //===----------------------------------------------------------------------===//
209 // Selection DAG Node Properties.
211 // Note: These are hard coded into tblgen.
213 class SDNodeProperty;
214 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
215 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
216 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
217 def SDNPOutFlag : SDNodeProperty; // Write a flag result
218 def SDNPInFlag : SDNodeProperty; // Read a flag operand
219 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
220 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
221 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
222 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
223 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
225 //===----------------------------------------------------------------------===//
226 // Selection DAG Node definitions.
228 class SDNode<string opcode, SDTypeProfile typeprof,
229 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
230 string Opcode = opcode;
231 string SDClass = sdclass;
232 list<SDNodeProperty> Properties = props;
233 SDTypeProfile TypeProfile = typeprof;
242 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
243 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
244 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
245 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
246 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
247 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
248 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
249 "GlobalAddressSDNode">;
250 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
251 "GlobalAddressSDNode">;
252 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
253 "GlobalAddressSDNode">;
254 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
255 "GlobalAddressSDNode">;
256 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
257 "ConstantPoolSDNode">;
258 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
259 "ConstantPoolSDNode">;
260 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
262 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
264 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
266 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
268 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
269 "ExternalSymbolSDNode">;
270 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
271 "ExternalSymbolSDNode">;
273 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
274 [SDNPCommutative, SDNPAssociative]>;
275 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
276 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
277 [SDNPCommutative, SDNPAssociative]>;
278 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
279 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
280 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
281 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
282 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
283 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
284 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
285 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
286 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
287 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
288 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
289 def and : SDNode<"ISD::AND" , SDTIntBinOp,
290 [SDNPCommutative, SDNPAssociative]>;
291 def or : SDNode<"ISD::OR" , SDTIntBinOp,
292 [SDNPCommutative, SDNPAssociative]>;
293 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
294 [SDNPCommutative, SDNPAssociative]>;
295 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
296 [SDNPCommutative, SDNPOutFlag]>;
297 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
298 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
299 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
301 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
302 [SDNPOutFlag, SDNPInFlag]>;
304 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
305 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
306 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
307 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
308 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
309 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
310 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
311 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
312 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
313 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
314 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
315 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
318 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
319 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
320 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
321 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
322 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
323 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
324 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
325 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
326 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
327 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
329 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
330 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
331 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
333 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
334 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
335 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
336 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
338 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
339 def select : SDNode<"ISD::SELECT" , SDTSelect>;
340 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
341 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
343 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
344 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
345 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
346 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
347 def trap : SDNode<"ISD::TRAP" , SDTNone,
348 [SDNPHasChain, SDNPSideEffect]>;
350 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
351 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
353 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
354 [SDNPHasChain, SDNPSideEffect]>;
356 // Do not use atomic_* directly, use atomic_*_size (see below)
357 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3,
358 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
359 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2,
360 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
361 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
362 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
363 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2,
364 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
365 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
366 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
367 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
368 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
369 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
371 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2,
372 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
373 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
374 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
375 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
376 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
377 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
378 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
379 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
380 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
382 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
383 // and truncst (see below).
384 def ld : SDNode<"ISD::LOAD" , SDTLoad,
385 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
386 def st : SDNode<"ISD::STORE" , SDTStore,
387 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
388 def ist : SDNode<"ISD::STORE" , SDTIStore,
389 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
391 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
392 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
393 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
395 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
396 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
397 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
398 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
400 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
401 SDTypeProfile<1, 2, []>>;
402 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
403 SDTypeProfile<1, 3, []>>;
405 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
406 // these internally. Don't reference these directly.
407 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
408 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
410 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
411 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
413 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
414 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
417 //===----------------------------------------------------------------------===//
418 // Selection DAG Condition Codes
420 class CondCode; // ISD::CondCode enums
421 def SETOEQ : CondCode; def SETOGT : CondCode;
422 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
423 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
424 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
425 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
427 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
428 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
431 //===----------------------------------------------------------------------===//
432 // Selection DAG Node Transformation Functions.
434 // This mechanism allows targets to manipulate nodes in the output DAG once a
435 // match has been formed. This is typically used to manipulate immediate
438 class SDNodeXForm<SDNode opc, code xformFunction> {
440 code XFormFunction = xformFunction;
443 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
446 //===----------------------------------------------------------------------===//
447 // Selection DAG Pattern Fragments.
449 // Pattern fragments are reusable chunks of dags that match specific things.
450 // They can take arguments and have C++ predicates that control whether they
451 // match. They are intended to make the patterns for common instructions more
452 // compact and readable.
455 /// PatFrag - Represents a pattern fragment. This can match something on the
456 /// DAG, frame a single node to multiply nested other fragments.
458 class PatFrag<dag ops, dag frag, code pred = [{}],
459 SDNodeXForm xform = NOOP_SDNodeXForm> {
462 code Predicate = pred;
463 SDNodeXForm OperandTransform = xform;
466 // PatLeaf's are pattern fragments that have no operands. This is just a helper
467 // to define immediates and other common things concisely.
468 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
469 : PatFrag<(ops), frag, pred, xform>;
473 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
474 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
476 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
477 def immAllOnesV: PatLeaf<(build_vector), [{
478 return ISD::isBuildVectorAllOnes(N);
480 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
481 return ISD::isBuildVectorAllOnes(N);
483 def immAllZerosV: PatLeaf<(build_vector), [{
484 return ISD::isBuildVectorAllZeros(N);
486 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
487 return ISD::isBuildVectorAllZeros(N);
492 // Other helper fragments.
493 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
494 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
495 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
496 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
499 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
500 LoadSDNode *LD = cast<LoadSDNode>(N);
501 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
502 LD->getAddressingMode() == ISD::UNINDEXED;
505 // extending load fragments.
506 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
507 LoadSDNode *LD = cast<LoadSDNode>(N);
508 return LD->getExtensionType() == ISD::EXTLOAD &&
509 LD->getAddressingMode() == ISD::UNINDEXED &&
510 LD->getMemoryVT() == MVT::i1;
512 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
513 LoadSDNode *LD = cast<LoadSDNode>(N);
514 return LD->getExtensionType() == ISD::EXTLOAD &&
515 LD->getAddressingMode() == ISD::UNINDEXED &&
516 LD->getMemoryVT() == MVT::i8;
518 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
519 LoadSDNode *LD = cast<LoadSDNode>(N);
520 return LD->getExtensionType() == ISD::EXTLOAD &&
521 LD->getAddressingMode() == ISD::UNINDEXED &&
522 LD->getMemoryVT() == MVT::i16;
524 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
525 LoadSDNode *LD = cast<LoadSDNode>(N);
526 return LD->getExtensionType() == ISD::EXTLOAD &&
527 LD->getAddressingMode() == ISD::UNINDEXED &&
528 LD->getMemoryVT() == MVT::i32;
530 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
531 LoadSDNode *LD = cast<LoadSDNode>(N);
532 return LD->getExtensionType() == ISD::EXTLOAD &&
533 LD->getAddressingMode() == ISD::UNINDEXED &&
534 LD->getMemoryVT() == MVT::f32;
536 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
537 LoadSDNode *LD = cast<LoadSDNode>(N);
538 return LD->getExtensionType() == ISD::EXTLOAD &&
539 LD->getAddressingMode() == ISD::UNINDEXED &&
540 LD->getMemoryVT() == MVT::f64;
543 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
544 LoadSDNode *LD = cast<LoadSDNode>(N);
545 return LD->getExtensionType() == ISD::SEXTLOAD &&
546 LD->getAddressingMode() == ISD::UNINDEXED &&
547 LD->getMemoryVT() == MVT::i1;
549 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
550 LoadSDNode *LD = cast<LoadSDNode>(N);
551 return LD->getExtensionType() == ISD::SEXTLOAD &&
552 LD->getAddressingMode() == ISD::UNINDEXED &&
553 LD->getMemoryVT() == MVT::i8;
555 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
556 LoadSDNode *LD = cast<LoadSDNode>(N);
557 return LD->getExtensionType() == ISD::SEXTLOAD &&
558 LD->getAddressingMode() == ISD::UNINDEXED &&
559 LD->getMemoryVT() == MVT::i16;
561 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
562 LoadSDNode *LD = cast<LoadSDNode>(N);
563 return LD->getExtensionType() == ISD::SEXTLOAD &&
564 LD->getAddressingMode() == ISD::UNINDEXED &&
565 LD->getMemoryVT() == MVT::i32;
568 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
569 LoadSDNode *LD = cast<LoadSDNode>(N);
570 return LD->getExtensionType() == ISD::ZEXTLOAD &&
571 LD->getAddressingMode() == ISD::UNINDEXED &&
572 LD->getMemoryVT() == MVT::i1;
574 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
575 LoadSDNode *LD = cast<LoadSDNode>(N);
576 return LD->getExtensionType() == ISD::ZEXTLOAD &&
577 LD->getAddressingMode() == ISD::UNINDEXED &&
578 LD->getMemoryVT() == MVT::i8;
580 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
581 LoadSDNode *LD = cast<LoadSDNode>(N);
582 return LD->getExtensionType() == ISD::ZEXTLOAD &&
583 LD->getAddressingMode() == ISD::UNINDEXED &&
584 LD->getMemoryVT() == MVT::i16;
586 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
587 LoadSDNode *LD = cast<LoadSDNode>(N);
588 return LD->getExtensionType() == ISD::ZEXTLOAD &&
589 LD->getAddressingMode() == ISD::UNINDEXED &&
590 LD->getMemoryVT() == MVT::i32;
594 def store : PatFrag<(ops node:$val, node:$ptr),
595 (st node:$val, node:$ptr), [{
596 StoreSDNode *ST = cast<StoreSDNode>(N);
597 return !ST->isTruncatingStore() &&
598 ST->getAddressingMode() == ISD::UNINDEXED;
601 // truncstore fragments.
602 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
603 (st node:$val, node:$ptr), [{
604 StoreSDNode *ST = cast<StoreSDNode>(N);
605 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
606 ST->getAddressingMode() == ISD::UNINDEXED;
608 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
609 (st node:$val, node:$ptr), [{
610 StoreSDNode *ST = cast<StoreSDNode>(N);
611 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
612 ST->getAddressingMode() == ISD::UNINDEXED;
614 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
615 (st node:$val, node:$ptr), [{
616 StoreSDNode *ST = cast<StoreSDNode>(N);
617 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
618 ST->getAddressingMode() == ISD::UNINDEXED;
621 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
622 (st node:$val, node:$ptr), [{
623 StoreSDNode *ST = cast<StoreSDNode>(N);
624 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
625 ST->getAddressingMode() == ISD::UNINDEXED;
627 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
628 (st node:$val, node:$ptr), [{
629 StoreSDNode *ST = cast<StoreSDNode>(N);
630 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
631 ST->getAddressingMode() == ISD::UNINDEXED;
634 // indexed store fragments.
635 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
636 (ist node:$val, node:$base, node:$offset), [{
637 StoreSDNode *ST = cast<StoreSDNode>(N);
638 ISD::MemIndexedMode AM = ST->getAddressingMode();
639 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
640 !ST->isTruncatingStore();
643 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
644 (ist node:$val, node:$base, node:$offset), [{
645 StoreSDNode *ST = cast<StoreSDNode>(N);
646 ISD::MemIndexedMode AM = ST->getAddressingMode();
647 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
648 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
650 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
651 (ist node:$val, node:$base, node:$offset), [{
652 StoreSDNode *ST = cast<StoreSDNode>(N);
653 ISD::MemIndexedMode AM = ST->getAddressingMode();
654 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
655 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
657 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
658 (ist node:$val, node:$base, node:$offset), [{
659 StoreSDNode *ST = cast<StoreSDNode>(N);
660 ISD::MemIndexedMode AM = ST->getAddressingMode();
661 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
662 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
664 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
665 (ist node:$val, node:$base, node:$offset), [{
666 StoreSDNode *ST = cast<StoreSDNode>(N);
667 ISD::MemIndexedMode AM = ST->getAddressingMode();
668 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
669 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
671 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
672 (ist node:$val, node:$base, node:$offset), [{
673 StoreSDNode *ST = cast<StoreSDNode>(N);
674 ISD::MemIndexedMode AM = ST->getAddressingMode();
675 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
676 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
679 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
680 (ist node:$val, node:$ptr, node:$offset), [{
681 StoreSDNode *ST = cast<StoreSDNode>(N);
682 ISD::MemIndexedMode AM = ST->getAddressingMode();
683 return !ST->isTruncatingStore() &&
684 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
687 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
688 (ist node:$val, node:$base, node:$offset), [{
689 StoreSDNode *ST = cast<StoreSDNode>(N);
690 ISD::MemIndexedMode AM = ST->getAddressingMode();
691 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
692 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
694 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
695 (ist node:$val, node:$base, node:$offset), [{
696 StoreSDNode *ST = cast<StoreSDNode>(N);
697 ISD::MemIndexedMode AM = ST->getAddressingMode();
698 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
699 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
701 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
702 (ist node:$val, node:$base, node:$offset), [{
703 StoreSDNode *ST = cast<StoreSDNode>(N);
704 ISD::MemIndexedMode AM = ST->getAddressingMode();
705 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
706 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
708 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
709 (ist node:$val, node:$base, node:$offset), [{
710 StoreSDNode *ST = cast<StoreSDNode>(N);
711 ISD::MemIndexedMode AM = ST->getAddressingMode();
712 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
713 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
715 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
716 (ist node:$val, node:$base, node:$offset), [{
717 StoreSDNode *ST = cast<StoreSDNode>(N);
718 ISD::MemIndexedMode AM = ST->getAddressingMode();
719 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
720 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
724 def atomic_cmp_swap_8 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
725 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
726 AtomicSDNode* V = cast<AtomicSDNode>(N);
727 return V->getValueType(0) == MVT::i8;
729 def atomic_cmp_swap_16 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
730 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
731 AtomicSDNode* V = cast<AtomicSDNode>(N);
732 return V->getValueType(0) == MVT::i16;
734 def atomic_cmp_swap_32 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
735 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
736 AtomicSDNode* V = cast<AtomicSDNode>(N);
737 return V->getValueType(0) == MVT::i32;
739 def atomic_cmp_swap_64 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
740 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
741 AtomicSDNode* V = cast<AtomicSDNode>(N);
742 return V->getValueType(0) == MVT::i64;
745 def atomic_load_add_8 : PatFrag<(ops node:$ptr, node:$inc),
746 (atomic_load_add node:$ptr, node:$inc), [{
747 AtomicSDNode* V = cast<AtomicSDNode>(N);
748 return V->getValueType(0) == MVT::i8;
750 def atomic_load_add_16 : PatFrag<(ops node:$ptr, node:$inc),
751 (atomic_load_add node:$ptr, node:$inc), [{
752 AtomicSDNode* V = cast<AtomicSDNode>(N);
753 return V->getValueType(0) == MVT::i16;
755 def atomic_load_add_32 : PatFrag<(ops node:$ptr, node:$inc),
756 (atomic_load_add node:$ptr, node:$inc), [{
757 AtomicSDNode* V = cast<AtomicSDNode>(N);
758 return V->getValueType(0) == MVT::i32;
760 def atomic_load_add_64 : PatFrag<(ops node:$ptr, node:$inc),
761 (atomic_load_add node:$ptr, node:$inc), [{
762 AtomicSDNode* V = cast<AtomicSDNode>(N);
763 return V->getValueType(0) == MVT::i64;
766 def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
767 (atomic_swap node:$ptr, node:$inc), [{
768 AtomicSDNode* V = cast<AtomicSDNode>(N);
769 return V->getValueType(0) == MVT::i8;
771 def atomic_swap_16 : PatFrag<(ops node:$ptr, node:$inc),
772 (atomic_swap node:$ptr, node:$inc), [{
773 AtomicSDNode* V = cast<AtomicSDNode>(N);
774 return V->getValueType(0) == MVT::i16;
776 def atomic_swap_32 : PatFrag<(ops node:$ptr, node:$inc),
777 (atomic_swap node:$ptr, node:$inc), [{
778 AtomicSDNode* V = cast<AtomicSDNode>(N);
779 return V->getValueType(0) == MVT::i32;
781 def atomic_swap_64 : PatFrag<(ops node:$ptr, node:$inc),
782 (atomic_swap node:$ptr, node:$inc), [{
783 AtomicSDNode* V = cast<AtomicSDNode>(N);
784 return V->getValueType(0) == MVT::i64;
789 // setcc convenience fragments.
790 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
791 (setcc node:$lhs, node:$rhs, SETOEQ)>;
792 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
793 (setcc node:$lhs, node:$rhs, SETOGT)>;
794 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
795 (setcc node:$lhs, node:$rhs, SETOGE)>;
796 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
797 (setcc node:$lhs, node:$rhs, SETOLT)>;
798 def setole : PatFrag<(ops node:$lhs, node:$rhs),
799 (setcc node:$lhs, node:$rhs, SETOLE)>;
800 def setone : PatFrag<(ops node:$lhs, node:$rhs),
801 (setcc node:$lhs, node:$rhs, SETONE)>;
802 def seto : PatFrag<(ops node:$lhs, node:$rhs),
803 (setcc node:$lhs, node:$rhs, SETO)>;
804 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
805 (setcc node:$lhs, node:$rhs, SETUO)>;
806 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
807 (setcc node:$lhs, node:$rhs, SETUEQ)>;
808 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
809 (setcc node:$lhs, node:$rhs, SETUGT)>;
810 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
811 (setcc node:$lhs, node:$rhs, SETUGE)>;
812 def setult : PatFrag<(ops node:$lhs, node:$rhs),
813 (setcc node:$lhs, node:$rhs, SETULT)>;
814 def setule : PatFrag<(ops node:$lhs, node:$rhs),
815 (setcc node:$lhs, node:$rhs, SETULE)>;
816 def setune : PatFrag<(ops node:$lhs, node:$rhs),
817 (setcc node:$lhs, node:$rhs, SETUNE)>;
818 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
819 (setcc node:$lhs, node:$rhs, SETEQ)>;
820 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
821 (setcc node:$lhs, node:$rhs, SETGT)>;
822 def setge : PatFrag<(ops node:$lhs, node:$rhs),
823 (setcc node:$lhs, node:$rhs, SETGE)>;
824 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
825 (setcc node:$lhs, node:$rhs, SETLT)>;
826 def setle : PatFrag<(ops node:$lhs, node:$rhs),
827 (setcc node:$lhs, node:$rhs, SETLE)>;
828 def setne : PatFrag<(ops node:$lhs, node:$rhs),
829 (setcc node:$lhs, node:$rhs, SETNE)>;
831 //===----------------------------------------------------------------------===//
832 // Selection DAG Pattern Support.
834 // Patterns are what are actually matched against the target-flavored
835 // instruction selection DAG. Instructions defined by the target implicitly
836 // define patterns in most cases, but patterns can also be explicitly added when
837 // an operation is defined by a sequence of instructions (e.g. loading a large
838 // immediate value on RISC targets that do not support immediates as large as
842 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
843 dag PatternToMatch = patternToMatch;
844 list<dag> ResultInstrs = resultInstrs;
845 list<Predicate> Predicates = []; // See class Instruction in Target.td.
846 int AddedComplexity = 0; // See class Instruction in Target.td.
849 // Pat - A simple (but common) form of a pattern, which produces a simple result
850 // not needing a full list.
851 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
853 //===----------------------------------------------------------------------===//
854 // Complex pattern definitions.
858 // Pass the parent Operand as root to CP function rather
859 // than the root of the sub-DAG
860 def CPAttrParentAsRoot : CPAttribute;
862 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
863 // in C++. NumOperands is the number of operands returned by the select function;
864 // SelectFunc is the name of the function used to pattern match the max. pattern;
865 // RootNodes are the list of possible root nodes of the sub-dags to match.
866 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
868 class ComplexPattern<ValueType ty, int numops, string fn,
869 list<SDNode> roots = [], list<SDNodeProperty> props = [],
870 list<CPAttribute> attrs = []> {
872 int NumOperands = numops;
873 string SelectFunc = fn;
874 list<SDNode> RootNodes = roots;
875 list<SDNodeProperty> Properties = props;
876 list<CPAttribute> Attributes = attrs;
879 //===----------------------------------------------------------------------===//
882 def SDT_dwarf_loc : SDTypeProfile<0, 3,
883 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
884 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;