1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 5>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 10>; // 128-bit floating point value
39 def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
40 def isVoid : ValueType<0 , 12>; // Produces no value
42 //===----------------------------------------------------------------------===//
43 // Register file description - These classes are used to fill in the target
44 // description classes in llvm/Target/MRegisterInfo.h
47 // Register - You should define one instance of this class for each register
48 // in the target machine. String n will become the "name" of the register.
49 class RegisterBase<string n> {
50 string Namespace = "";
53 // SpillSize - If this value is set to a non-zero value, it is the size in
54 // bits of the spill slot required to hold this register. If this value is
55 // set to zero, the information is inferred from any register classes the
56 // register belongs to.
59 // SpillAlignment - This value is used to specify the alignment required for
60 // spilling the register. Like SpillSize, this should only be explicitly
61 // specified if the register is not in a register class.
62 int SpillAlignment = 0;
65 class Register<string n> : RegisterBase<n> {
66 list<RegisterBase> Aliases = [];
69 // RegisterGroup - This can be used to define instances of Register which
70 // need to specify aliases.
71 // List "aliases" specifies which registers are aliased to this one. This
72 // allows the code generator to be careful not to put two values with
73 // overlapping live ranges into registers which alias.
74 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
75 let Aliases = aliases;
78 // RegisterClass - Now that all of the registers are defined, and aliases
79 // between registers are defined, specify which registers belong to which
80 // register classes. This also defines the default allocation order of
81 // registers by register allocators.
83 class RegisterClass<string namespace, ValueType regType, int alignment,
84 list<Register> regList> {
85 string Namespace = namespace;
87 // RegType - Specify the ValueType of the registers in this register class.
88 // Note that all registers in a register class must have the same ValueType.
90 ValueType RegType = regType;
92 // Alignment - Specify the alignment required of the registers when they are
93 // stored or loaded to memory.
95 int Size = RegType.Size;
96 int Alignment = alignment;
98 // MemberList - Specify which registers are in this class. If the
99 // allocation_order_* method are not specified, this also defines the order of
100 // allocation used by the register allocator.
102 list<Register> MemberList = regList;
104 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
105 // code into a generated register class. The normal usage of this is to
106 // overload virtual methods.
107 code MethodProtos = [{}];
108 code MethodBodies = [{}];
112 //===----------------------------------------------------------------------===//
113 // Instruction set description - These classes correspond to the C++ classes in
114 // the Target/TargetInstrInfo.h file.
117 string Name = ""; // The opcode string for this instruction
118 string Namespace = "";
120 dag OperandList; // An dag containing the MI operand list.
121 string AsmString = ""; // The .s format to print the instruction with.
123 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
124 // otherwise, uninitialized.
127 // The follow state will eventually be inferred automatically from the
128 // instruction pattern.
130 list<Register> Uses = []; // Default to using no non-operand registers
131 list<Register> Defs = []; // Default to modifying no non-operand registers
133 // These bits capture information about the high-level semantics of the
135 bit isReturn = 0; // Is this instruction a return instruction?
136 bit isBranch = 0; // Is this instruction a branch instruction?
137 bit isBarrier = 0; // Can control flow fall through this instruction?
138 bit isCall = 0; // Is this instruction a call instruction?
139 bit isLoad = 0; // Is this instruction a load instruction?
140 bit isStore = 0; // Is this instruction a store instruction?
141 bit isTwoAddress = 0; // Is this a two address instruction?
142 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
143 bit isCommutable = 0; // Is this 3 operand instruction commutable?
144 bit isTerminator = 0; // Is this part of the terminator for a basic block?
145 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
149 /// ops definition - This is just a simple marker used to identify the operands
150 /// list for an instruction. This should be used like this:
151 /// (ops R32:$dst, R32:$src) or something similar.
154 /// variable_ops definition - Mark this instruction as taking a variable number
158 /// Operand Types - These provide the built-in operand types that may be used
159 /// by a target. Targets can optionally provide their own operand types as
160 /// needed, though this should not be needed for RISC targets.
161 class Operand<ValueType ty> {
162 int NumMIOperands = 1;
164 string PrintMethod = "printOperand";
167 def i1imm : Operand<i1>;
168 def i8imm : Operand<i8>;
169 def i16imm : Operand<i16>;
170 def i32imm : Operand<i32>;
171 def i64imm : Operand<i64>;
173 // InstrInfo - This class should only be instantiated once to provide parameters
174 // which are global to the the target machine.
179 // If the target wants to associate some target-specific information with each
180 // instruction, it should provide these two lists to indicate how to assemble
181 // the target specific information into the 32 bits available.
183 list<string> TSFlagsFields = [];
184 list<int> TSFlagsShifts = [];
186 // Target can specify its instructions in either big or little-endian formats.
187 // For instance, while both Sparc and PowerPC are big-endian platforms, the
188 // Sparc manual specifies its instructions in the format [31..0] (big), while
189 // PowerPC specifies them using the format [0..31] (little).
190 bit isLittleEndianEncoding = 0;
193 //===----------------------------------------------------------------------===//
194 // AsmWriter - This class can be implemented by targets that need to customize
195 // the format of the .s file writer.
197 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
198 // on X86 for example).
201 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
202 // class. Generated AsmWriter classes are always prefixed with the target
204 string AsmWriterClassName = "AsmPrinter";
206 // InstFormatName - AsmWriters can specify the name of the format string to
207 // print instructions with.
208 string InstFormatName = "AsmString";
210 // Variant - AsmWriters can be of multiple different variants. Variants are
211 // used to support targets that need to emit assembly code in ways that are
212 // mostly the same for different targets, but have minor differences in
213 // syntax. If the asmstring contains {|} characters in them, this integer
214 // will specify which alternative to use. For example "{x|y|z}" with Variant
215 // == 1, will expand to "y".
218 def DefaultAsmWriter : AsmWriter;
221 //===----------------------------------------------------------------------===//
222 // Target - This class contains the "global" target information
225 // CalleeSavedRegisters - As you might guess, this is a list of the callee
226 // saved registers for a target.
227 list<Register> CalleeSavedRegisters = [];
229 // PointerType - Specify the value type to be used to represent pointers in
230 // this target. Typically this is an i32 or i64 type.
231 ValueType PointerType;
233 // InstructionSet - Instruction set description for this target.
234 InstrInfo InstructionSet;
236 // AssemblyWriters - The AsmWriter instances available for this target.
237 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
241 //===----------------------------------------------------------------------===//
242 // DAG node definitions used by the instruction selector.
244 // NOTE: all of this is a work-in-progress and should be ignored for now.
247 class Expander<dag pattern, list<dag> result> {
248 dag Pattern = pattern;
249 list<dag> Result = result;
252 class DagNodeValType;
253 def DNVT_any : DagNodeValType; // No constraint on tree node
254 def DNVT_void : DagNodeValType; // Tree node always returns void
255 def DNVT_val : DagNodeValType; // A non-void type
256 def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
257 def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
258 def DNVT_ptr : DagNodeValType; // The target pointer type
259 def DNVT_i8 : DagNodeValType; // Always have an i8 value
261 class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
262 DagNodeValType RetType = ret;
263 list<DagNodeValType> ArgTypes = args;
267 // BuiltinDagNodes are built into the instruction selector and correspond to
269 class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
270 string Ename> : DagNode<Ret, Args> {
271 let EnumName = Ename;
275 def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
276 def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
277 def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
278 def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
280 def ChainExpander : Expander<(chain Void, Void), []>;
281 def BlockChainExpander : Expander<(blockchain Void, Void), []>;
285 def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
286 def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
287 def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
290 def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
291 def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
292 def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
293 def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
294 def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
295 def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
296 def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
297 def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
298 def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
299 def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
302 def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
303 def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
304 def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
305 def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
306 def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
307 def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
309 def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
310 //def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
313 def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
314 def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
315 def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
316 def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
319 def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
320 def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
322 //===----------------------------------------------------------------------===//
323 // DAG nonterminals definitions used by the instruction selector...
325 class Nonterminal<dag pattern> {
326 dag Pattern = pattern;