1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // Register - You should define one instance of this class for each register
25 // in the target machine. String n will become the "name" of the register.
26 class Register<string n> {
27 string Namespace = "";
30 // SpillSize - If this value is set to a non-zero value, it is the size in
31 // bits of the spill slot required to hold this register. If this value is
32 // set to zero, the information is inferred from any register classes the
33 // register belongs to.
36 // SpillAlignment - This value is used to specify the alignment required for
37 // spilling the register. Like SpillSize, this should only be explicitly
38 // specified if the register is not in a register class.
39 int SpillAlignment = 0;
41 // Aliases - A list of registers that this register overlaps with. A read or
42 // modification of this register can potentially read or modify the aliased
44 list<Register> Aliases = [];
46 // SubRegs - A list of registers that are parts of this register. Note these
47 // are "immediate" sub-registers and the registers within the list do not
48 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
50 list<Register> SubRegs = [];
52 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
53 // These values can be determined by locating the <target>.h file in the
54 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
55 // order of these names correspond to the enumeration used by gcc. A value of
56 // -1 indicates that the gcc number is undefined.
60 // RegisterWithSubRegs - This can be used to define instances of Register which
61 // need to specify sub-registers.
62 // List "subregs" specifies which registers are sub-registers to this one. This
63 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
64 // This allows the code generator to be careful not to put two values with
65 // overlapping live ranges into registers which alias.
66 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
67 let SubRegs = subregs;
70 // RegisterGroup - This can be used to define instances of Register which
71 // need to specify aliases.
72 // List "aliases" specifies which registers are aliased to this one. This
73 // allows the code generator to be careful not to put two values with
74 // overlapping live ranges into registers which alias.
75 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
76 let Aliases = aliases;
79 // RegisterClass - Now that all of the registers are defined, and aliases
80 // between registers are defined, specify which registers belong to which
81 // register classes. This also defines the default allocation order of
82 // registers by register allocators.
84 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
85 list<Register> regList> {
86 string Namespace = namespace;
88 // RegType - Specify the list ValueType of the registers in this register
89 // class. Note that all registers in a register class must have the same
90 // ValueTypes. This is a list because some targets permit storing different
91 // types in same register, for example vector values with 128-bit total size,
92 // but different count/size of items, like SSE on x86.
94 list<ValueType> RegTypes = regTypes;
96 // Size - Specify the spill size in bits of the registers. A default value of
97 // zero lets tablgen pick an appropriate size.
100 // Alignment - Specify the alignment required of the registers when they are
101 // stored or loaded to memory.
103 int Alignment = alignment;
105 // MemberList - Specify which registers are in this class. If the
106 // allocation_order_* method are not specified, this also defines the order of
107 // allocation used by the register allocator.
109 list<Register> MemberList = regList;
111 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
112 // code into a generated register class. The normal usage of this is to
113 // overload virtual methods.
114 code MethodProtos = [{}];
115 code MethodBodies = [{}];
119 //===----------------------------------------------------------------------===//
120 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
121 // to the register numbering used by gcc and gdb. These values are used by a
122 // debug information writer (ex. DwarfWriter) to describe where values may be
123 // located during execution.
124 class DwarfRegNum<int N> {
125 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
126 // These values can be determined by locating the <target>.h file in the
127 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
128 // order of these names correspond to the enumeration used by gcc. A value of
129 // -1 indicates that the gcc number is undefined.
133 //===----------------------------------------------------------------------===//
134 // Pull in the common support for scheduling
136 include "TargetSchedule.td"
138 class Predicate; // Forward def
140 //===----------------------------------------------------------------------===//
141 // Instruction set description - These classes correspond to the C++ classes in
142 // the Target/TargetInstrInfo.h file.
145 string Name = ""; // The opcode string for this instruction
146 string Namespace = "";
148 dag OperandList; // An dag containing the MI operand list.
149 string AsmString = ""; // The .s format to print the instruction with.
151 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
152 // otherwise, uninitialized.
155 // The follow state will eventually be inferred automatically from the
156 // instruction pattern.
158 list<Register> Uses = []; // Default to using no non-operand registers
159 list<Register> Defs = []; // Default to modifying no non-operand registers
161 // Predicates - List of predicates which will be turned into isel matching
163 list<Predicate> Predicates = [];
168 // Added complexity passed onto matching pattern.
169 int AddedComplexity = 0;
171 // These bits capture information about the high-level semantics of the
173 bit isReturn = 0; // Is this instruction a return instruction?
174 bit isBranch = 0; // Is this instruction a branch instruction?
175 bit isBarrier = 0; // Can control flow fall through this instruction?
176 bit isCall = 0; // Is this instruction a call instruction?
177 bit isLoad = 0; // Is this instruction a load instruction?
178 bit isStore = 0; // Is this instruction a store instruction?
179 bit isTwoAddress = 0; // Is this a two address instruction?
180 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
181 bit isCommutable = 0; // Is this 3 operand instruction commutable?
182 bit isTerminator = 0; // Is this part of the terminator for a basic block?
183 bit isReMaterializable = 0; // Is this instruction re-materializable?
184 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
185 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
186 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
187 bit noResults = 0; // Does this instruction produce no results?
189 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
191 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
193 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
194 /// be encoded into the output machineinstr.
195 string DisableEncoding = "";
198 /// Imp - Helper class for specifying the implicit uses/defs set for an
200 class Imp<list<Register> uses, list<Register> defs> {
201 list<Register> Uses = uses;
202 list<Register> Defs = defs;
205 /// Predicates - These are extra conditionals which are turned into instruction
206 /// selector matching code. Currently each predicate is just a string.
207 class Predicate<string cond> {
208 string CondString = cond;
211 class Requires<list<Predicate> preds> {
212 list<Predicate> Predicates = preds;
215 /// ops definition - This is just a simple marker used to identify the operands
216 /// list for an instruction. This should be used like this:
217 /// (ops R32:$dst, R32:$src) or something similar.
220 /// variable_ops definition - Mark this instruction as taking a variable number
224 /// ptr_rc definition - Mark this operand as being a pointer value whose
225 /// register class is resolved dynamically via a callback to TargetInstrInfo.
226 /// FIXME: We should probably change this to a class which contain a list of
227 /// flags. But currently we have but one flag.
230 /// Operand Types - These provide the built-in operand types that may be used
231 /// by a target. Targets can optionally provide their own operand types as
232 /// needed, though this should not be needed for RISC targets.
233 class Operand<ValueType ty> {
235 string PrintMethod = "printOperand";
236 dag MIOperandInfo = (ops);
239 def i1imm : Operand<i1>;
240 def i8imm : Operand<i8>;
241 def i16imm : Operand<i16>;
242 def i32imm : Operand<i32>;
243 def i64imm : Operand<i64>;
246 /// PredicateOperand - This can be used to define a predicate operand for an
247 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
248 /// AlwaysVal specifies the value of this predicate when set to "always
250 class PredicateOperand<dag OpTypes, dag AlwaysVal> : Operand<OtherVT> {
251 let MIOperandInfo = OpTypes;
252 dag ExecuteAlways = AlwaysVal;
256 // InstrInfo - This class should only be instantiated once to provide parameters
257 // which are global to the the target machine.
260 // If the target wants to associate some target-specific information with each
261 // instruction, it should provide these two lists to indicate how to assemble
262 // the target specific information into the 32 bits available.
264 list<string> TSFlagsFields = [];
265 list<int> TSFlagsShifts = [];
267 // Target can specify its instructions in either big or little-endian formats.
268 // For instance, while both Sparc and PowerPC are big-endian platforms, the
269 // Sparc manual specifies its instructions in the format [31..0] (big), while
270 // PowerPC specifies them using the format [0..31] (little).
271 bit isLittleEndianEncoding = 0;
274 // Standard Instructions.
275 def PHI : Instruction {
276 let OperandList = (ops variable_ops);
277 let AsmString = "PHINODE";
278 let Namespace = "TargetInstrInfo";
280 def INLINEASM : Instruction {
281 let OperandList = (ops variable_ops);
283 let Namespace = "TargetInstrInfo";
285 def LABEL : Instruction {
286 let OperandList = (ops i32imm:$id);
288 let Namespace = "TargetInstrInfo";
292 //===----------------------------------------------------------------------===//
293 // AsmWriter - This class can be implemented by targets that need to customize
294 // the format of the .s file writer.
296 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
297 // on X86 for example).
300 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
301 // class. Generated AsmWriter classes are always prefixed with the target
303 string AsmWriterClassName = "AsmPrinter";
305 // InstFormatName - AsmWriters can specify the name of the format string to
306 // print instructions with.
307 string InstFormatName = "AsmString";
309 // Variant - AsmWriters can be of multiple different variants. Variants are
310 // used to support targets that need to emit assembly code in ways that are
311 // mostly the same for different targets, but have minor differences in
312 // syntax. If the asmstring contains {|} characters in them, this integer
313 // will specify which alternative to use. For example "{x|y|z}" with Variant
314 // == 1, will expand to "y".
317 def DefaultAsmWriter : AsmWriter;
320 //===----------------------------------------------------------------------===//
321 // Target - This class contains the "global" target information
324 // InstructionSet - Instruction set description for this target.
325 InstrInfo InstructionSet;
327 // AssemblyWriters - The AsmWriter instances available for this target.
328 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
331 //===----------------------------------------------------------------------===//
332 // SubtargetFeature - A characteristic of the chip set.
334 class SubtargetFeature<string n, string a, string v, string d> {
335 // Name - Feature name. Used by command line (-mattr=) to determine the
336 // appropriate target chip.
340 // Attribute - Attribute to be set by feature.
342 string Attribute = a;
344 // Value - Value the attribute to be set to by feature.
348 // Desc - Feature description. Used by command line (-mattr=) to display help
354 //===----------------------------------------------------------------------===//
355 // Processor chip sets - These values represent each of the chip sets supported
356 // by the scheduler. Each Processor definition requires corresponding
357 // instruction itineraries.
359 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
360 // Name - Chip set name. Used by command line (-mcpu=) to determine the
361 // appropriate target chip.
365 // ProcItin - The scheduling information for the target processor.
367 ProcessorItineraries ProcItin = pi;
369 // Features - list of
370 list<SubtargetFeature> Features = f;
373 //===----------------------------------------------------------------------===//
374 // Pull in the common support for calling conventions.
376 include "TargetCallingConv.td"
378 //===----------------------------------------------------------------------===//
379 // Pull in the common support for DAG isel generation.
381 include "TargetSelectionDAG.td"