1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass tries to replace instructions with shorter forms. For example,
11 // IILF can be replaced with LLILL or LLILH if the constant fits and if the
12 // other 32 bits of the GR64 destination are not live.
14 //===----------------------------------------------------------------------===//
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/LivePhysRegs.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
24 #define DEBUG_TYPE "systemz-shorten-inst"
27 class SystemZShortenInst : public MachineFunctionPass {
30 SystemZShortenInst(const SystemZTargetMachine &tm);
32 const char *getPassName() const override {
33 return "SystemZ Instruction Shortening";
36 bool processBlock(MachineBasicBlock &MBB);
37 bool runOnMachineFunction(MachineFunction &F) override;
40 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
41 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
42 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
43 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
44 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
45 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
47 const SystemZInstrInfo *TII;
48 const TargetRegisterInfo *TRI;
49 LivePhysRegs LiveRegs;
52 char SystemZShortenInst::ID = 0;
53 } // end anonymous namespace
55 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
56 return new SystemZShortenInst(TM);
59 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
60 : MachineFunctionPass(ID), TII(nullptr) {}
62 // Tie operands if MI has become a two-address instruction.
63 static void tieOpsIfNeeded(MachineInstr &MI) {
64 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
65 !MI.getOperand(0).isTied())
69 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
70 // are the halfword immediate loads for the same word. Try to use one of them
72 bool SystemZShortenInst::shortenIIF(MachineInstr &MI,
73 unsigned LLIxL, unsigned LLIxH) {
74 unsigned Reg = MI.getOperand(0).getReg();
75 // The new opcode will clear the other half of the GR64 reg, so
76 // cancel if that is live.
77 unsigned thisSubRegIdx = (SystemZ::GRH32BitRegClass.contains(Reg) ?
78 SystemZ::subreg_h32 : SystemZ::subreg_l32);
79 unsigned otherSubRegIdx = (thisSubRegIdx == SystemZ::subreg_l32 ?
80 SystemZ::subreg_h32 : SystemZ::subreg_l32);
81 unsigned GR64BitReg = TRI->getMatchingSuperReg(Reg, thisSubRegIdx,
82 &SystemZ::GR64BitRegClass);
83 unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
84 if (LiveRegs.contains(OtherReg))
87 uint64_t Imm = MI.getOperand(1).getImm();
88 if (SystemZ::isImmLL(Imm)) {
89 MI.setDesc(TII->get(LLIxL));
90 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 if (SystemZ::isImmLH(Imm)) {
94 MI.setDesc(TII->get(LLIxH));
95 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
96 MI.getOperand(1).setImm(Imm >> 16);
102 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
103 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
104 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
105 MI.setDesc(TII->get(Opcode));
111 // Change MI's opcode to Opcode if register operands 0 and 1 have a
113 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
114 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
115 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
116 MI.setDesc(TII->get(Opcode));
122 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
123 // 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
124 // with op 1, if MI becomes 2-address.
125 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
126 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
127 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
128 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
129 MI.setDesc(TII->get(Opcode));
136 // Calls shortenOn001 if CCLive is false. CC def operand is added in
138 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI,
140 if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
141 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
142 .addReg(SystemZ::CC, RegState::ImplicitDefine);
148 // MI is a vector-style conversion instruction with the operand order:
149 // destination, source, exact-suppress, rounding-mode. If both registers
150 // have a 4-bit encoding then change it to Opcode, which has operand order:
151 // destination, rouding-mode, source, exact-suppress.
152 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
153 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
154 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
155 MachineOperand Dest(MI.getOperand(0));
156 MachineOperand Src(MI.getOperand(1));
157 MachineOperand Suppress(MI.getOperand(2));
158 MachineOperand Mode(MI.getOperand(3));
163 MI.setDesc(TII->get(Opcode));
164 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
168 .addOperand(Suppress);
174 // Process all instructions in MBB. Return true if something changed.
175 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
176 bool Changed = false;
178 // Set up the set of live registers at the end of MBB (live out)
180 LiveRegs.addLiveOuts(&MBB);
182 // Iterate backwards through the block looking for instructions to change.
183 for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
184 MachineInstr &MI = *MBBI;
185 switch (MI.getOpcode()) {
187 Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
191 Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
195 Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
199 Changed |= shortenOn001(MI, SystemZ::DDBR);
203 Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
207 Changed |= shortenOn01(MI, SystemZ::LDEBR);
211 Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
215 Changed |= shortenOn001(MI, SystemZ::MDBR);
218 case SystemZ::WFLCDB:
219 Changed |= shortenOn01(MI, SystemZ::LCDFR);
222 case SystemZ::WFLNDB:
223 Changed |= shortenOn01(MI, SystemZ::LNDFR);
226 case SystemZ::WFLPDB:
227 Changed |= shortenOn01(MI, SystemZ::LPDFR);
230 case SystemZ::WFSQDB:
231 Changed |= shortenOn01(MI, SystemZ::SQDBR);
235 Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
239 Changed |= shortenOn01(MI, SystemZ::CDBR);
243 // For z13 we prefer LDE over LE to avoid partial register dependencies.
244 Changed |= shortenOn0(MI, SystemZ::LDE32);
248 Changed |= shortenOn0(MI, SystemZ::STE);
252 Changed |= shortenOn0(MI, SystemZ::LD);
256 Changed |= shortenOn0(MI, SystemZ::STD);
260 LiveRegs.stepBackward(MI);
266 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
267 const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
268 TII = ST.getInstrInfo();
269 TRI = ST.getRegisterInfo();
272 bool Changed = false;
274 Changed |= processBlock(MBB);