1 //===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class SystemZReg<string n> : Register<n> {
14 let Namespace = "SystemZ";
17 class SystemZRegWithSubregs<string n, list<Register> subregs>
18 : RegisterWithSubRegs<n, subregs> {
19 let Namespace = "SystemZ";
22 // We identify all our registers with a 4-bit ID, for consistency's sake.
24 // GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers
25 class GPR32<bits<4> num, string n> : SystemZReg<n> {
26 field bits<4> Num = num;
29 // GPR64 - One of the 16 64-bit general-purpose registers
30 class GPR64<bits<4> num, string n, list<Register> subregs>
31 : SystemZRegWithSubregs<n, subregs> {
32 field bits<4> Num = num;
35 // FPR - One of the 16 64-bit floating-point registers
36 class FPR<bits<4> num, string n> : SystemZReg<n> {
37 field bits<4> Num = num;
40 // General-purpose registers
41 def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>;
42 def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>;
43 def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>;
44 def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>;
45 def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>;
46 def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>;
47 def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>;
48 def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>;
49 def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>;
50 def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>;
51 def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>;
52 def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>;
53 def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>;
54 def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>;
55 def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>;
56 def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>;
58 def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>;
59 def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>;
60 def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>;
61 def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>;
62 def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>;
63 def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>;
64 def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>;
65 def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>;
66 def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>;
67 def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>;
68 def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>;
69 def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>;
70 def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>;
71 def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>;
72 def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>;
73 def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>;
75 // Floating-point registers
76 def F0 : FPR< 0, "f0">, DwarfRegNum<[16]>;
77 def F1 : FPR< 1, "f1">, DwarfRegNum<[17]>;
78 def F2 : FPR< 2, "f2">, DwarfRegNum<[18]>;
79 def F3 : FPR< 3, "f3">, DwarfRegNum<[19]>;
80 def F4 : FPR< 4, "f4">, DwarfRegNum<[20]>;
81 def F5 : FPR< 5, "f5">, DwarfRegNum<[21]>;
82 def F6 : FPR< 6, "f6">, DwarfRegNum<[22]>;
83 def F7 : FPR< 7, "f7">, DwarfRegNum<[23]>;
84 def F8 : FPR< 8, "f8">, DwarfRegNum<[24]>;
85 def F9 : FPR< 9, "f9">, DwarfRegNum<[25]>;
86 def F10 : FPR<10, "f10">, DwarfRegNum<[26]>;
87 def F11 : FPR<11, "f11">, DwarfRegNum<[27]>;
88 def F12 : FPR<12, "f12">, DwarfRegNum<[28]>;
89 def F13 : FPR<13, "f13">, DwarfRegNum<[29]>;
90 def F14 : FPR<14, "f14">, DwarfRegNum<[30]>;
91 def F15 : FPR<15, "f15">, DwarfRegNum<[31]>;
94 def PSW : SystemZReg<"psw">;
96 def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D,
97 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
98 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W,
99 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
101 def subreg_32bit : PatLeaf<(i32 1)>;
104 def GR32 : RegisterClass<"SystemZ", [i32], 32,
105 // Volatile registers
106 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
107 // Frame pointer, sometimes allocable
109 // Volatile, but not allocable
112 let MethodProtos = [{
113 iterator allocation_order_end(const MachineFunction &MF) const;
115 let MethodBodies = [{
117 GR32Class::allocation_order_end(const MachineFunction &MF) const {
118 const TargetMachine &TM = MF.getTarget();
119 const TargetRegisterInfo *RI = TM.getRegisterInfo();
120 // Depending on whether the function uses frame pointer or not, last 2 or 3
121 // registers on the list above are reserved
130 def GR64 : RegisterClass<"SystemZ", [i64], 64,
131 // Volatile registers
132 [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
133 // Frame pointer, sometimes allocable
135 // Volatile, but not allocable
138 let SubRegClassList = [GR32];
139 let MethodProtos = [{
140 iterator allocation_order_end(const MachineFunction &MF) const;
142 let MethodBodies = [{
144 GR64Class::allocation_order_end(const MachineFunction &MF) const {
145 const TargetMachine &TM = MF.getTarget();
146 const TargetRegisterInfo *RI = TM.getRegisterInfo();
147 // Depending on whether the function uses frame pointer or not, last 2 or 3
148 // registers on the list above are reserved
157 def FP64 : RegisterClass<"SystemZ", [f64], 64,
158 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15]>;
160 // Status flags registers.
161 def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> {
162 let CopyCost = -1; // Don't allow copying of status registers.