1 //===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZInstrInfo.h"
16 #include "SystemZMachineFunctionInfo.h"
17 #include "SystemZRegisterInfo.h"
18 #include "SystemZSubtarget.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetFrameLowering.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/BitVector.h"
29 #define GET_REGINFO_MC_DESC
30 #define GET_REGINFO_TARGET_DESC
31 #include "SystemZGenRegisterInfo.inc"
35 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
36 const SystemZInstrInfo &tii)
37 : SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc,
38 SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
43 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
44 static const unsigned CalleeSavedRegs[] = {
45 SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
46 SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
47 SystemZ::R14D, SystemZ::R15D,
48 SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L,
49 SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L,
53 return CalleeSavedRegs;
56 BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
57 BitVector Reserved(getNumRegs());
58 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
61 // R11D is the frame pointer. Reserve all aliases.
62 Reserved.set(SystemZ::R11D);
63 Reserved.set(SystemZ::R11W);
64 Reserved.set(SystemZ::R10P);
65 Reserved.set(SystemZ::R10Q);
68 Reserved.set(SystemZ::R14D);
69 Reserved.set(SystemZ::R15D);
70 Reserved.set(SystemZ::R14W);
71 Reserved.set(SystemZ::R15W);
72 Reserved.set(SystemZ::R14P);
73 Reserved.set(SystemZ::R14Q);
77 const TargetRegisterClass*
78 SystemZRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
79 const TargetRegisterClass *B,
82 // Exact sub-classes don't exist for the other sub-register indexes.
84 case SystemZ::subreg_32bit:
85 if (B == SystemZ::ADDR32RegisterClass)
86 return A->getSize() == 8 ? SystemZ::ADDR64RegisterClass : 0;
91 void SystemZRegisterInfo::
92 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator I) const {
98 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
99 int SPAdj, RegScavenger *RS) const {
100 assert(SPAdj == 0 && "Unxpected");
103 MachineInstr &MI = *II;
104 MachineFunction &MF = *MI.getParent()->getParent();
105 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
107 while (!MI.getOperand(i).isFI()) {
109 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
112 int FrameIndex = MI.getOperand(i).getIndex();
114 unsigned BasePtr = (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
116 // This must be part of a rri or ri operand memory reference. Replace the
117 // FrameIndex with base register with BasePtr. Add an offset to the
118 // displacement field.
119 MI.getOperand(i).ChangeToRegister(BasePtr, false);
121 // Offset is a either 12-bit unsigned or 20-bit signed integer.
122 // FIXME: handle "too long" displacements.
124 TFI->getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
126 // Check whether displacement is too long to fit into 12 bit zext field.
127 MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
129 MI.getOperand(i+1).ChangeToImmediate(Offset);
132 unsigned SystemZRegisterInfo::getRARegister() const {
133 assert(0 && "What is the return address register");
138 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
139 assert(0 && "What is the frame register");
143 unsigned SystemZRegisterInfo::getEHExceptionRegister() const {
144 assert(0 && "What is the exception register");
148 unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
149 assert(0 && "What is the exception handler register");
153 int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
154 assert(0 && "What is the dwarf register number");
158 int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
159 assert(0 && "What is the dwarf register number");