1 //===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
14 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
16 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
17 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
18 def SDT_ZBRCCMask : SDTypeProfile<0, 3,
21 SDTCisVT<2, OtherVT>]>;
22 def SDT_ZSelectCCMask : SDTypeProfile<1, 4,
27 def SDT_ZWrapPtr : SDTypeProfile<1, 1,
30 def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
31 def SDT_ZExtractAccess : SDTypeProfile<1, 1,
34 def SDT_ZGR128Binary32 : SDTypeProfile<1, 2,
35 [SDTCisVT<0, untyped>,
38 def SDT_ZGR128Binary64 : SDTypeProfile<1, 2,
39 [SDTCisVT<0, untyped>,
42 def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
49 def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
57 def SDT_ZMemMemLength : SDTypeProfile<0, 3,
62 //===----------------------------------------------------------------------===//
64 //===----------------------------------------------------------------------===//
66 // These are target-independent nodes, but have target-specific formats.
67 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
68 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
69 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
70 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue,
73 // Nodes for SystemZISD::*. See SystemZISelLowering.h for more details.
74 def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
75 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
76 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
77 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
79 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
80 def z_cmp : SDNode<"SystemZISD::CMP", SDT_ZCmp, [SDNPOutGlue]>;
81 def z_ucmp : SDNode<"SystemZISD::UCMP", SDT_ZCmp, [SDNPOutGlue]>;
82 def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask,
83 [SDNPHasChain, SDNPInGlue]>;
84 def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
86 def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
87 def z_extract_access : SDNode<"SystemZISD::EXTRACT_ACCESS",
89 def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>;
90 def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>;
91 def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>;
92 def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
93 def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
95 class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
96 : SDNode<"SystemZISD::"##name, profile,
97 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
99 def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
100 def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">;
101 def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">;
102 def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">;
103 def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">;
104 def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">;
105 def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">;
106 def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">;
107 def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">;
108 def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
109 def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
110 def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
112 def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
113 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
114 def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
115 [SDNPHasChain, SDNPMayLoad]>;
117 //===----------------------------------------------------------------------===//
119 //===----------------------------------------------------------------------===//
121 // Register sign-extend operations. Sub-32-bit values are represented as i32s.
122 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
123 def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>;
124 def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>;
126 // Register zero-extend operations. Sub-32-bit values are represented as i32s.
127 def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
128 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
129 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
131 // Typed floating-point loads.
132 def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>;
133 def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>;
135 // Extending loads in which the extension type doesn't matter.
136 def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
137 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;
139 def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
140 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
142 def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
143 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
145 def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
146 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
150 class AlignedLoad<SDPatternOperator load>
151 : PatFrag<(ops node:$addr), (load node:$addr), [{
152 LoadSDNode *Load = cast<LoadSDNode>(N);
153 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
155 def aligned_load : AlignedLoad<load>;
156 def aligned_sextloadi16 : AlignedLoad<sextloadi16>;
157 def aligned_sextloadi32 : AlignedLoad<sextloadi32>;
158 def aligned_zextloadi16 : AlignedLoad<zextloadi16>;
159 def aligned_zextloadi32 : AlignedLoad<zextloadi32>;
162 class AlignedStore<SDPatternOperator store>
163 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
164 StoreSDNode *Store = cast<StoreSDNode>(N);
165 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
167 def aligned_store : AlignedStore<store>;
168 def aligned_truncstorei16 : AlignedStore<truncstorei16>;
169 def aligned_truncstorei32 : AlignedStore<truncstorei32>;
171 // Non-volatile loads. Used for instructions that might access the storage
172 // location multiple times.
173 class NonvolatileLoad<SDPatternOperator load>
174 : PatFrag<(ops node:$addr), (load node:$addr), [{
175 LoadSDNode *Load = cast<LoadSDNode>(N);
176 return !Load->isVolatile();
178 def nonvolatile_load : NonvolatileLoad<load>;
179 def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>;
180 def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>;
181 def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>;
183 // Non-volatile stores.
184 class NonvolatileStore<SDPatternOperator store>
185 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
186 StoreSDNode *Store = cast<StoreSDNode>(N);
187 return !Store->isVolatile();
189 def nonvolatile_store : NonvolatileStore<store>;
190 def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>;
191 def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>;
192 def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>;
195 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
196 (or (and node:$src1, -256), node:$src2)>;
197 def insertll : PatFrag<(ops node:$src1, node:$src2),
198 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
199 def insertlh : PatFrag<(ops node:$src1, node:$src2),
200 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
201 def inserthl : PatFrag<(ops node:$src1, node:$src2),
202 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
203 def inserthh : PatFrag<(ops node:$src1, node:$src2),
204 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
205 def insertlf : PatFrag<(ops node:$src1, node:$src2),
206 (or (and node:$src1, 0xffffffff00000000), node:$src2)>;
207 def inserthf : PatFrag<(ops node:$src1, node:$src2),
208 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>;
210 // ORs that can be treated as insertions.
211 def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2),
212 (or node:$src1, node:$src2), [{
213 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
214 return CurDAG->MaskedValueIsZero(N->getOperand(0),
215 APInt::getLowBitsSet(BitWidth, 8));
218 // ORs that can be treated as reversed insertions.
219 def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
220 (or node:$src1, node:$src2), [{
221 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
222 return CurDAG->MaskedValueIsZero(N->getOperand(1),
223 APInt::getLowBitsSet(BitWidth, 8));
226 // Fused multiply-add and multiply-subtract, but with the order of the
227 // operands matching SystemZ's MA and MS instructions.
228 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
229 (fma node:$src2, node:$src3, node:$src1)>;
230 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
231 (fma node:$src2, node:$src3, (fneg node:$src1))>;
233 // Floating-point negative absolute.
234 def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>;
236 // Create a unary operator that loads from memory and then performs
237 // the given operation on it.
238 class loadu<SDPatternOperator operator, SDPatternOperator load = load>
239 : PatFrag<(ops node:$addr), (operator (load node:$addr))>;
241 // Create a store operator that performs the given unary operation
242 // on the value before storing it.
243 class storeu<SDPatternOperator operator, SDPatternOperator store = store>
244 : PatFrag<(ops node:$value, node:$addr),
245 (store (operator node:$value), node:$addr)>;