1 //===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
14 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
16 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
17 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
18 def SDT_ZICmp : SDTypeProfile<0, 3,
21 def SDT_ZBRCCMask : SDTypeProfile<0, 3,
24 SDTCisVT<2, OtherVT>]>;
25 def SDT_ZSelectCCMask : SDTypeProfile<1, 4,
30 def SDT_ZWrapPtr : SDTypeProfile<1, 1,
33 def SDT_ZWrapOffset : SDTypeProfile<1, 2,
37 def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
38 def SDT_ZExtractAccess : SDTypeProfile<1, 1,
41 def SDT_ZGR128Binary32 : SDTypeProfile<1, 2,
42 [SDTCisVT<0, untyped>,
45 def SDT_ZGR128Binary64 : SDTypeProfile<1, 2,
46 [SDTCisVT<0, untyped>,
49 def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
56 def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
64 def SDT_ZMemMemLength : SDTypeProfile<0, 3,
68 def SDT_ZMemMemLoop : SDTypeProfile<0, 4,
73 def SDT_ZString : SDTypeProfile<1, 3,
78 def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
79 def SDT_ZPrefetch : SDTypeProfile<0, 2,
82 def SDT_ZTBegin : SDTypeProfile<0, 2,
85 def SDT_ZInsertVectorElt : SDTypeProfile<1, 3,
89 def SDT_ZExtractVectorElt : SDTypeProfile<1, 2,
92 def SDT_ZReplicate : SDTypeProfile<1, 1,
94 def SDT_ZVecBinary : SDTypeProfile<1, 2,
98 def SDT_ZVecBinaryInt : SDTypeProfile<1, 2,
102 def SDT_ZVecBinaryConv : SDTypeProfile<1, 2,
105 SDTCisSameAs<1, 2>]>;
106 def SDT_ZRotateMask : SDTypeProfile<1, 2,
110 def SDT_ZJoinDwords : SDTypeProfile<1, 2,
114 def SDT_ZVecTernary : SDTypeProfile<1, 3,
118 SDTCisSameAs<0, 3>]>;
119 def SDT_ZVecTernaryInt : SDTypeProfile<1, 3,
125 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
131 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
133 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue,
135 def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>;
137 // Nodes for SystemZISD::*. See SystemZISelLowering.h for more details.
138 def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
140 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
141 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
143 def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall,
144 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
146 def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall,
147 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
149 def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall,
150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
152 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
153 def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET",
154 SDT_ZWrapOffset, []>;
155 def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>;
156 def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>;
157 def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>;
158 def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>;
159 def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask,
160 [SDNPHasChain, SDNPInGlue]>;
161 def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
163 def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
164 def z_extract_access : SDNode<"SystemZISD::EXTRACT_ACCESS",
166 def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>;
167 def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>;
168 def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>;
169 def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>;
170 def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
171 def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
173 def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone,
174 [SDNPHasChain, SDNPMayStore]>;
176 // Defined because the index is an i32 rather than a pointer.
177 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
178 SDT_ZInsertVectorElt>;
179 def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
180 SDT_ZExtractVectorElt>;
181 def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>;
182 def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>;
183 def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>;
184 def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>;
185 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>;
186 def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>;
187 def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>;
188 def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>;
189 def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS",
191 def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>;
192 def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>;
193 def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR",
195 def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR",
197 def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR",
199 def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>;
200 def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>;
201 def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>;
202 def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>;
204 class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
205 : SDNode<"SystemZISD::"##name, profile,
206 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
208 def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
209 def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">;
210 def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">;
211 def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">;
212 def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">;
213 def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">;
214 def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">;
215 def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">;
216 def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">;
217 def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
218 def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
219 def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
221 def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
222 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
223 def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop,
224 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
225 def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength,
226 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
227 def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop,
228 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
229 def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength,
230 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
231 def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop,
232 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
233 def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength,
234 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
235 def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop,
236 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
237 def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
238 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
239 def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop,
240 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
241 def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString,
242 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
243 def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString,
244 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
245 def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString,
246 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
247 def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic,
249 def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch,
250 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
253 def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
254 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
256 def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
257 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
259 def z_tend : SDNode<"SystemZISD::TEND", SDTNone,
260 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
262 def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>;
263 def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>;
264 def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>;
266 //===----------------------------------------------------------------------===//
268 //===----------------------------------------------------------------------===//
270 // Signed and unsigned comparisons.
271 def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
272 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
273 return Type != SystemZICMP::UnsignedOnly;
275 def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
276 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
277 return Type != SystemZICMP::SignedOnly;
280 // Register- and memory-based TEST UNDER MASK.
281 def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>;
282 def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>;
284 // Register sign-extend operations. Sub-32-bit values are represented as i32s.
285 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
286 def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>;
287 def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>;
289 // Match extensions of an i32 to an i64, followed by an in-register sign
290 // extension from a sub-i32 value.
291 def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>;
292 def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>;
294 // Register zero-extend operations. Sub-32-bit values are represented as i32s.
295 def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
296 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
297 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
299 // Match extensions of an i32 to an i64, followed by an AND of the low
301 def zext8dbl : PatFrag<(ops node:$src), (zext8 (anyext node:$src))>;
302 def zext16dbl : PatFrag<(ops node:$src), (zext16 (anyext node:$src))>;
304 // Typed floating-point loads.
305 def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>;
306 def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>;
308 // Extending loads in which the extension type can be signed.
309 def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
310 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
311 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
313 def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
314 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
316 def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
317 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
319 def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
320 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
323 // Extending loads in which the extension type can be unsigned.
324 def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
325 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
326 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
328 def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
329 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
331 def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
332 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
334 def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
335 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
338 // Extending loads in which the extension type doesn't matter.
339 def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
340 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;
342 def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
343 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
345 def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
346 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
348 def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
349 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
353 class AlignedLoad<SDPatternOperator load>
354 : PatFrag<(ops node:$addr), (load node:$addr), [{
355 auto *Load = cast<LoadSDNode>(N);
356 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
358 def aligned_load : AlignedLoad<load>;
359 def aligned_asextloadi16 : AlignedLoad<asextloadi16>;
360 def aligned_asextloadi32 : AlignedLoad<asextloadi32>;
361 def aligned_azextloadi16 : AlignedLoad<azextloadi16>;
362 def aligned_azextloadi32 : AlignedLoad<azextloadi32>;
365 class AlignedStore<SDPatternOperator store>
366 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
367 auto *Store = cast<StoreSDNode>(N);
368 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
370 def aligned_store : AlignedStore<store>;
371 def aligned_truncstorei16 : AlignedStore<truncstorei16>;
372 def aligned_truncstorei32 : AlignedStore<truncstorei32>;
374 // Non-volatile loads. Used for instructions that might access the storage
375 // location multiple times.
376 class NonvolatileLoad<SDPatternOperator load>
377 : PatFrag<(ops node:$addr), (load node:$addr), [{
378 auto *Load = cast<LoadSDNode>(N);
379 return !Load->isVolatile();
381 def nonvolatile_load : NonvolatileLoad<load>;
382 def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>;
383 def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>;
384 def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>;
386 // Non-volatile stores.
387 class NonvolatileStore<SDPatternOperator store>
388 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
389 auto *Store = cast<StoreSDNode>(N);
390 return !Store->isVolatile();
392 def nonvolatile_store : NonvolatileStore<store>;
393 def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>;
394 def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>;
395 def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>;
397 // A store of a load that can be implemented using MVC.
398 def mvc_store : PatFrag<(ops node:$value, node:$addr),
399 (unindexedstore node:$value, node:$addr),
400 [{ return storeLoadCanUseMVC(N); }]>;
402 // Binary read-modify-write operations on memory in which the other
403 // operand is also memory and for which block operations like NC can
404 // be used. There are two patterns for each operator, depending on
405 // which operand contains the "other" load.
406 multiclass block_op<SDPatternOperator operator> {
407 def "1" : PatFrag<(ops node:$value, node:$addr),
408 (unindexedstore (operator node:$value,
409 (unindexedload node:$addr)),
411 [{ return storeLoadCanUseBlockBinary(N, 0); }]>;
412 def "2" : PatFrag<(ops node:$value, node:$addr),
413 (unindexedstore (operator (unindexedload node:$addr),
416 [{ return storeLoadCanUseBlockBinary(N, 1); }]>;
418 defm block_and : block_op<and>;
419 defm block_or : block_op<or>;
420 defm block_xor : block_op<xor>;
423 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
424 (or (and node:$src1, -256), node:$src2)>;
425 def insertll : PatFrag<(ops node:$src1, node:$src2),
426 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
427 def insertlh : PatFrag<(ops node:$src1, node:$src2),
428 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
429 def inserthl : PatFrag<(ops node:$src1, node:$src2),
430 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
431 def inserthh : PatFrag<(ops node:$src1, node:$src2),
432 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
433 def insertlf : PatFrag<(ops node:$src1, node:$src2),
434 (or (and node:$src1, 0xffffffff00000000), node:$src2)>;
435 def inserthf : PatFrag<(ops node:$src1, node:$src2),
436 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>;
438 // ORs that can be treated as insertions.
439 def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2),
440 (or node:$src1, node:$src2), [{
441 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
442 return CurDAG->MaskedValueIsZero(N->getOperand(0),
443 APInt::getLowBitsSet(BitWidth, 8));
446 // ORs that can be treated as reversed insertions.
447 def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
448 (or node:$src1, node:$src2), [{
449 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
450 return CurDAG->MaskedValueIsZero(N->getOperand(1),
451 APInt::getLowBitsSet(BitWidth, 8));
454 // Negative integer absolute.
455 def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>;
457 // Integer absolute, matching the canonical form generated by DAGCombiner.
458 def z_iabs32 : PatFrag<(ops node:$src),
459 (xor (add node:$src, (sra node:$src, (i32 31))),
460 (sra node:$src, (i32 31)))>;
461 def z_iabs64 : PatFrag<(ops node:$src),
462 (xor (add node:$src, (sra node:$src, (i32 63))),
463 (sra node:$src, (i32 63)))>;
464 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
465 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
467 // Integer multiply-and-add
468 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
469 (add (mul node:$src1, node:$src2), node:$src3)>;
471 // Fused multiply-add and multiply-subtract, but with the order of the
472 // operands matching SystemZ's MA and MS instructions.
473 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
474 (fma node:$src2, node:$src3, node:$src1)>;
475 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
476 (fma node:$src2, node:$src3, (fneg node:$src1))>;
478 // Floating-point negative absolute.
479 def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>;
481 // Create a unary operator that loads from memory and then performs
482 // the given operation on it.
483 class loadu<SDPatternOperator operator, SDPatternOperator load = load>
484 : PatFrag<(ops node:$addr), (operator (load node:$addr))>;
486 // Create a store operator that performs the given unary operation
487 // on the value before storing it.
488 class storeu<SDPatternOperator operator, SDPatternOperator store = store>
489 : PatFrag<(ops node:$value, node:$addr),
490 (store (operator node:$value), node:$addr)>;
492 // Vector representation of all-zeros and all-ones.
493 def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>;
494 def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>;
496 // Load a scalar and replicate it in all elements of a vector.
497 class z_replicate_load<ValueType scalartype, SDPatternOperator load>
498 : PatFrag<(ops node:$addr),
499 (z_replicate (scalartype (load node:$addr)))>;
500 def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>;
501 def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>;
502 def z_replicate_loadi32 : z_replicate_load<i32, load>;
503 def z_replicate_loadi64 : z_replicate_load<i64, load>;
505 // Load a scalar and insert it into a single element of a vector.
506 class z_vle<ValueType scalartype, SDPatternOperator load>
507 : PatFrag<(ops node:$vec, node:$addr, node:$index),
508 (z_vector_insert node:$vec, (scalartype (load node:$addr)),
510 def z_vlei8 : z_vle<i32, anyextloadi8>;
511 def z_vlei16 : z_vle<i32, anyextloadi16>;
512 def z_vlei32 : z_vle<i32, load>;
513 def z_vlei64 : z_vle<i64, load>;
515 // Load a scalar and insert it into the low element of the high i64 of a
517 class z_vllez<ValueType scalartype, SDPatternOperator load, int index>
518 : PatFrag<(ops node:$addr),
519 (z_vector_insert (z_vzero),
520 (scalartype (load node:$addr)), (i32 index))>;
521 def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>;
522 def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>;
523 def z_vllezi32 : z_vllez<i32, load, 1>;
524 def z_vllezi64 : PatFrag<(ops node:$addr),
525 (z_join_dwords (i64 (load node:$addr)), (i64 0))>;
527 // Store one element of a vector.
528 class z_vste<ValueType scalartype, SDPatternOperator store>
529 : PatFrag<(ops node:$vec, node:$addr, node:$index),
530 (store (scalartype (z_vector_extract node:$vec, node:$index)),
532 def z_vstei8 : z_vste<i32, truncstorei8>;
533 def z_vstei16 : z_vste<i32, truncstorei16>;
534 def z_vstei32 : z_vste<i32, store>;
535 def z_vstei64 : z_vste<i64, store>;
537 // Arithmetic negation on vectors.
538 def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>;
540 // Bitwise negation on vectors.
541 def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>;
543 // Signed "integer greater than zero" on vectors.
544 def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>;
546 // Signed "integer less than zero" on vectors.
547 def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>;
549 // Integer absolute on vectors.
550 class z_viabs<int shift>
551 : PatFrag<(ops node:$src),
552 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))),
553 (z_vsra_by_scalar node:$src, (i32 shift)))>;
554 def z_viabs8 : z_viabs<7>;
555 def z_viabs16 : z_viabs<15>;
556 def z_viabs32 : z_viabs<31>;
557 def z_viabs64 : z_viabs<63>;
559 // Sign-extend the i64 elements of a vector.
560 class z_vse<int shift>
561 : PatFrag<(ops node:$src),
562 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>;
563 def z_vsei8 : z_vse<56>;
564 def z_vsei16 : z_vse<48>;
565 def z_vsei32 : z_vse<32>;
567 // ...and again with the extensions being done on individual i64 scalars.
568 class z_vse_by_parts<SDPatternOperator operator, int index1, int index2>
569 : PatFrag<(ops node:$src),
571 (operator (z_vector_extract node:$src, index1)),
572 (operator (z_vector_extract node:$src, index2)))>;
573 def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>;
574 def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>;
575 def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>;