1 //===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
14 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
16 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
17 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
18 def SDT_ZICmp : SDTypeProfile<0, 3,
21 def SDT_ZBRCCMask : SDTypeProfile<0, 3,
24 SDTCisVT<2, OtherVT>]>;
25 def SDT_ZSelectCCMask : SDTypeProfile<1, 4,
30 def SDT_ZWrapPtr : SDTypeProfile<1, 1,
33 def SDT_ZWrapOffset : SDTypeProfile<1, 2,
37 def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
38 def SDT_ZExtractAccess : SDTypeProfile<1, 1,
41 def SDT_ZGR128Binary32 : SDTypeProfile<1, 2,
42 [SDTCisVT<0, untyped>,
45 def SDT_ZGR128Binary64 : SDTypeProfile<1, 2,
46 [SDTCisVT<0, untyped>,
49 def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
56 def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
64 def SDT_ZMemMemLength : SDTypeProfile<0, 3,
68 def SDT_ZMemMemLoop : SDTypeProfile<0, 4,
73 def SDT_ZString : SDTypeProfile<1, 3,
78 def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
79 def SDT_ZPrefetch : SDTypeProfile<0, 2,
82 def SDT_ZTBegin : SDTypeProfile<0, 2,
85 def SDT_ZInsertVectorElt : SDTypeProfile<1, 3,
89 def SDT_ZExtractVectorElt : SDTypeProfile<1, 2,
92 def SDT_ZReplicate : SDTypeProfile<1, 1,
94 def SDT_ZVecUnaryConv : SDTypeProfile<1, 1,
97 def SDT_ZVecBinary : SDTypeProfile<1, 2,
100 SDTCisSameAs<0, 2>]>;
101 def SDT_ZVecBinaryInt : SDTypeProfile<1, 2,
105 def SDT_ZVecBinaryConv : SDTypeProfile<1, 2,
108 SDTCisSameAs<1, 2>]>;
109 def SDT_ZRotateMask : SDTypeProfile<1, 2,
113 def SDT_ZJoinDwords : SDTypeProfile<1, 2,
117 def SDT_ZVecTernary : SDTypeProfile<1, 3,
121 SDTCisSameAs<0, 3>]>;
122 def SDT_ZVecTernaryInt : SDTypeProfile<1, 3,
128 //===----------------------------------------------------------------------===//
130 //===----------------------------------------------------------------------===//
132 // These are target-independent nodes, but have target-specific formats.
133 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
134 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
135 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
136 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue,
138 def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>;
140 // Nodes for SystemZISD::*. See SystemZISelLowering.h for more details.
141 def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
143 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
144 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
146 def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall,
147 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
149 def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall,
150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
152 def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall,
153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
155 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
156 def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET",
157 SDT_ZWrapOffset, []>;
158 def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>;
159 def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>;
160 def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>;
161 def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>;
162 def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask,
163 [SDNPHasChain, SDNPInGlue]>;
164 def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
166 def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
167 def z_extract_access : SDNode<"SystemZISD::EXTRACT_ACCESS",
169 def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>;
170 def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>;
171 def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>;
172 def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>;
173 def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
174 def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
176 def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone,
177 [SDNPHasChain, SDNPMayStore]>;
179 // Defined because the index is an i32 rather than a pointer.
180 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
181 SDT_ZInsertVectorElt>;
182 def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
183 SDT_ZExtractVectorElt>;
184 def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>;
185 def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>;
186 def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>;
187 def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>;
188 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>;
189 def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>;
190 def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>;
191 def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>;
192 def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS",
194 def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>;
195 def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>;
196 def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR",
198 def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR",
200 def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR",
202 def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>;
203 def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>;
204 def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>;
205 def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>;
206 def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>;
207 def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>;
208 def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>;
209 def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>;
210 def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>;
212 class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
213 : SDNode<"SystemZISD::"##name, profile,
214 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
216 def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
217 def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">;
218 def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">;
219 def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">;
220 def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">;
221 def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">;
222 def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">;
223 def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">;
224 def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">;
225 def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
226 def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
227 def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
229 def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
230 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
231 def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop,
232 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
233 def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength,
234 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
235 def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop,
236 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
237 def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength,
238 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
239 def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop,
240 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
241 def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength,
242 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
243 def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop,
244 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
245 def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
246 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
247 def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop,
248 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
249 def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString,
250 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
251 def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString,
252 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
253 def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString,
254 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
255 def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic,
257 def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch,
258 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
261 def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
262 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
264 def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
265 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
267 def z_tend : SDNode<"SystemZISD::TEND", SDTNone,
268 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
270 def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>;
271 def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>;
272 def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>;
274 //===----------------------------------------------------------------------===//
276 //===----------------------------------------------------------------------===//
278 // Signed and unsigned comparisons.
279 def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
280 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
281 return Type != SystemZICMP::UnsignedOnly;
283 def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
284 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
285 return Type != SystemZICMP::SignedOnly;
288 // Register- and memory-based TEST UNDER MASK.
289 def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>;
290 def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>;
292 // Register sign-extend operations. Sub-32-bit values are represented as i32s.
293 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
294 def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>;
295 def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>;
297 // Match extensions of an i32 to an i64, followed by an in-register sign
298 // extension from a sub-i32 value.
299 def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>;
300 def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>;
302 // Register zero-extend operations. Sub-32-bit values are represented as i32s.
303 def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
304 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
305 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
307 // Match extensions of an i32 to an i64, followed by an AND of the low
309 def zext8dbl : PatFrag<(ops node:$src), (zext8 (anyext node:$src))>;
310 def zext16dbl : PatFrag<(ops node:$src), (zext16 (anyext node:$src))>;
312 // Typed floating-point loads.
313 def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>;
314 def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>;
316 // Extending loads in which the extension type can be signed.
317 def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
318 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
319 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
321 def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
322 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
324 def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
325 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
327 def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
328 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
331 // Extending loads in which the extension type can be unsigned.
332 def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
333 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
334 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
336 def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
337 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
339 def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
340 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
342 def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
343 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
346 // Extending loads in which the extension type doesn't matter.
347 def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
348 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;
350 def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
351 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
353 def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
354 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
356 def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
357 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
361 class AlignedLoad<SDPatternOperator load>
362 : PatFrag<(ops node:$addr), (load node:$addr), [{
363 auto *Load = cast<LoadSDNode>(N);
364 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
366 def aligned_load : AlignedLoad<load>;
367 def aligned_asextloadi16 : AlignedLoad<asextloadi16>;
368 def aligned_asextloadi32 : AlignedLoad<asextloadi32>;
369 def aligned_azextloadi16 : AlignedLoad<azextloadi16>;
370 def aligned_azextloadi32 : AlignedLoad<azextloadi32>;
373 class AlignedStore<SDPatternOperator store>
374 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
375 auto *Store = cast<StoreSDNode>(N);
376 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
378 def aligned_store : AlignedStore<store>;
379 def aligned_truncstorei16 : AlignedStore<truncstorei16>;
380 def aligned_truncstorei32 : AlignedStore<truncstorei32>;
382 // Non-volatile loads. Used for instructions that might access the storage
383 // location multiple times.
384 class NonvolatileLoad<SDPatternOperator load>
385 : PatFrag<(ops node:$addr), (load node:$addr), [{
386 auto *Load = cast<LoadSDNode>(N);
387 return !Load->isVolatile();
389 def nonvolatile_load : NonvolatileLoad<load>;
390 def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>;
391 def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>;
392 def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>;
394 // Non-volatile stores.
395 class NonvolatileStore<SDPatternOperator store>
396 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
397 auto *Store = cast<StoreSDNode>(N);
398 return !Store->isVolatile();
400 def nonvolatile_store : NonvolatileStore<store>;
401 def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>;
402 def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>;
403 def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>;
405 // A store of a load that can be implemented using MVC.
406 def mvc_store : PatFrag<(ops node:$value, node:$addr),
407 (unindexedstore node:$value, node:$addr),
408 [{ return storeLoadCanUseMVC(N); }]>;
410 // Binary read-modify-write operations on memory in which the other
411 // operand is also memory and for which block operations like NC can
412 // be used. There are two patterns for each operator, depending on
413 // which operand contains the "other" load.
414 multiclass block_op<SDPatternOperator operator> {
415 def "1" : PatFrag<(ops node:$value, node:$addr),
416 (unindexedstore (operator node:$value,
417 (unindexedload node:$addr)),
419 [{ return storeLoadCanUseBlockBinary(N, 0); }]>;
420 def "2" : PatFrag<(ops node:$value, node:$addr),
421 (unindexedstore (operator (unindexedload node:$addr),
424 [{ return storeLoadCanUseBlockBinary(N, 1); }]>;
426 defm block_and : block_op<and>;
427 defm block_or : block_op<or>;
428 defm block_xor : block_op<xor>;
431 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
432 (or (and node:$src1, -256), node:$src2)>;
433 def insertll : PatFrag<(ops node:$src1, node:$src2),
434 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
435 def insertlh : PatFrag<(ops node:$src1, node:$src2),
436 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
437 def inserthl : PatFrag<(ops node:$src1, node:$src2),
438 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
439 def inserthh : PatFrag<(ops node:$src1, node:$src2),
440 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
441 def insertlf : PatFrag<(ops node:$src1, node:$src2),
442 (or (and node:$src1, 0xffffffff00000000), node:$src2)>;
443 def inserthf : PatFrag<(ops node:$src1, node:$src2),
444 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>;
446 // ORs that can be treated as insertions.
447 def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2),
448 (or node:$src1, node:$src2), [{
449 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
450 return CurDAG->MaskedValueIsZero(N->getOperand(0),
451 APInt::getLowBitsSet(BitWidth, 8));
454 // ORs that can be treated as reversed insertions.
455 def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
456 (or node:$src1, node:$src2), [{
457 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
458 return CurDAG->MaskedValueIsZero(N->getOperand(1),
459 APInt::getLowBitsSet(BitWidth, 8));
462 // Negative integer absolute.
463 def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>;
465 // Integer absolute, matching the canonical form generated by DAGCombiner.
466 def z_iabs32 : PatFrag<(ops node:$src),
467 (xor (add node:$src, (sra node:$src, (i32 31))),
468 (sra node:$src, (i32 31)))>;
469 def z_iabs64 : PatFrag<(ops node:$src),
470 (xor (add node:$src, (sra node:$src, (i32 63))),
471 (sra node:$src, (i32 63)))>;
472 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
473 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
475 // Integer multiply-and-add
476 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
477 (add (mul node:$src1, node:$src2), node:$src3)>;
479 // Fused multiply-subtract, using the natural operand order.
480 def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
481 (fma node:$src1, node:$src2, (fneg node:$src3))>;
483 // Fused multiply-add and multiply-subtract, but with the order of the
484 // operands matching SystemZ's MA and MS instructions.
485 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
486 (fma node:$src2, node:$src3, node:$src1)>;
487 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
488 (fma node:$src2, node:$src3, (fneg node:$src1))>;
490 // Floating-point negative absolute.
491 def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>;
493 // Create a unary operator that loads from memory and then performs
494 // the given operation on it.
495 class loadu<SDPatternOperator operator, SDPatternOperator load = load>
496 : PatFrag<(ops node:$addr), (operator (load node:$addr))>;
498 // Create a store operator that performs the given unary operation
499 // on the value before storing it.
500 class storeu<SDPatternOperator operator, SDPatternOperator store = store>
501 : PatFrag<(ops node:$value, node:$addr),
502 (store (operator node:$value), node:$addr)>;
504 // Vector representation of all-zeros and all-ones.
505 def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>;
506 def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>;
508 // Load a scalar and replicate it in all elements of a vector.
509 class z_replicate_load<ValueType scalartype, SDPatternOperator load>
510 : PatFrag<(ops node:$addr),
511 (z_replicate (scalartype (load node:$addr)))>;
512 def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>;
513 def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>;
514 def z_replicate_loadi32 : z_replicate_load<i32, load>;
515 def z_replicate_loadi64 : z_replicate_load<i64, load>;
516 def z_replicate_loadf32 : z_replicate_load<f32, load>;
517 def z_replicate_loadf64 : z_replicate_load<f64, load>;
519 // Load a scalar and insert it into a single element of a vector.
520 class z_vle<ValueType scalartype, SDPatternOperator load>
521 : PatFrag<(ops node:$vec, node:$addr, node:$index),
522 (z_vector_insert node:$vec, (scalartype (load node:$addr)),
524 def z_vlei8 : z_vle<i32, anyextloadi8>;
525 def z_vlei16 : z_vle<i32, anyextloadi16>;
526 def z_vlei32 : z_vle<i32, load>;
527 def z_vlei64 : z_vle<i64, load>;
528 def z_vlef32 : z_vle<f32, load>;
529 def z_vlef64 : z_vle<f64, load>;
531 // Load a scalar and insert it into the low element of the high i64 of a
533 class z_vllez<ValueType scalartype, SDPatternOperator load, int index>
534 : PatFrag<(ops node:$addr),
535 (z_vector_insert (z_vzero),
536 (scalartype (load node:$addr)), (i32 index))>;
537 def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>;
538 def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>;
539 def z_vllezi32 : z_vllez<i32, load, 1>;
540 def z_vllezi64 : PatFrag<(ops node:$addr),
541 (z_join_dwords (i64 (load node:$addr)), (i64 0))>;
542 // We use high merges to form a v4f32 from four f32s. Propagating zero
543 // into all elements but index 1 gives this expression.
544 def z_vllezf32 : PatFrag<(ops node:$addr),
550 (v4f32 (scalar_to_vector
551 (f32 (load node:$addr))))))),
552 (v2i64 (z_vzero))))>;
553 def z_vllezf64 : PatFrag<(ops node:$addr),
555 (scalar_to_vector (f64 (load node:$addr))),
558 // Store one element of a vector.
559 class z_vste<ValueType scalartype, SDPatternOperator store>
560 : PatFrag<(ops node:$vec, node:$addr, node:$index),
561 (store (scalartype (z_vector_extract node:$vec, node:$index)),
563 def z_vstei8 : z_vste<i32, truncstorei8>;
564 def z_vstei16 : z_vste<i32, truncstorei16>;
565 def z_vstei32 : z_vste<i32, store>;
566 def z_vstei64 : z_vste<i64, store>;
567 def z_vstef32 : z_vste<f32, store>;
568 def z_vstef64 : z_vste<f64, store>;
570 // Arithmetic negation on vectors.
571 def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>;
573 // Bitwise negation on vectors.
574 def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>;
576 // Signed "integer greater than zero" on vectors.
577 def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>;
579 // Signed "integer less than zero" on vectors.
580 def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>;
582 // Integer absolute on vectors.
583 class z_viabs<int shift>
584 : PatFrag<(ops node:$src),
585 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))),
586 (z_vsra_by_scalar node:$src, (i32 shift)))>;
587 def z_viabs8 : z_viabs<7>;
588 def z_viabs16 : z_viabs<15>;
589 def z_viabs32 : z_viabs<31>;
590 def z_viabs64 : z_viabs<63>;
592 // Sign-extend the i64 elements of a vector.
593 class z_vse<int shift>
594 : PatFrag<(ops node:$src),
595 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>;
596 def z_vsei8 : z_vse<56>;
597 def z_vsei16 : z_vse<48>;
598 def z_vsei32 : z_vse<32>;
600 // ...and again with the extensions being done on individual i64 scalars.
601 class z_vse_by_parts<SDPatternOperator operator, int index1, int index2>
602 : PatFrag<(ops node:$src),
604 (operator (z_vector_extract node:$src, index1)),
605 (operator (z_vector_extract node:$src, index2)))>;
606 def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>;
607 def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>;
608 def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>;