1 //==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 let Predicates = [FeatureVector] in {
16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
18 // Load GR from VR element.
19 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>;
20 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>;
21 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>;
22 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, null_frag, v128g, 3>;
24 // Load VR element from GR.
25 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, null_frag, v128b, v128b, GR32, 0>;
26 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, null_frag, v128h, v128h, GR32, 1>;
27 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, null_frag, v128f, v128f, GR32, 2>;
28 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, null_frag, v128g, v128g, GR64, 3>;
30 // Load VR from GRs disjoint.
31 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, null_frag, v128g>;
34 //===----------------------------------------------------------------------===//
35 // Immediate instructions
36 //===----------------------------------------------------------------------===//
38 let Predicates = [FeatureVector] in {
39 // Generate byte mask.
40 def VZERO : InherentVRIa<"vzero", 0xE744, 0>;
41 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>;
42 def VGBM : UnaryVRIa<"vgbm", 0xE744, null_frag, v128b, imm32zx16>;
45 def VGMB : BinaryVRIb<"vgmb", 0xE746, null_frag, v128b, 0>;
46 def VGMH : BinaryVRIb<"vgmh", 0xE746, null_frag, v128h, 1>;
47 def VGMF : BinaryVRIb<"vgmf", 0xE746, null_frag, v128f, 2>;
48 def VGMG : BinaryVRIb<"vgmg", 0xE746, null_frag, v128g, 3>;
50 // Load element immediate.
51 def VLEIB : TernaryVRIa<"vleib", 0xE740, null_frag,
52 v128b, v128b, imm32sx16trunc, imm32zx4>;
53 def VLEIH : TernaryVRIa<"vleih", 0xE741, null_frag,
54 v128h, v128h, imm32sx16trunc, imm32zx3>;
55 def VLEIF : TernaryVRIa<"vleif", 0xE743, null_frag,
56 v128f, v128f, imm32sx16, imm32zx2>;
57 def VLEIG : TernaryVRIa<"vleig", 0xE742, null_frag,
58 v128g, v128g, imm64sx16, imm32zx1>;
60 // Replicate immediate.
61 def VREPIB : UnaryVRIa<"vrepib", 0xE745, null_frag, v128b, imm32sx16, 0>;
62 def VREPIH : UnaryVRIa<"vrepih", 0xE745, null_frag, v128h, imm32sx16, 1>;
63 def VREPIF : UnaryVRIa<"vrepif", 0xE745, null_frag, v128f, imm32sx16, 2>;
64 def VREPIG : UnaryVRIa<"vrepig", 0xE745, null_frag, v128g, imm32sx16, 3>;
67 //===----------------------------------------------------------------------===//
69 //===----------------------------------------------------------------------===//
71 let Predicates = [FeatureVector] in {
73 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>;
75 // Load to block boundary. The number of loaded bytes is only known
77 def VLBB : BinaryVRX<"vlbb", 0xE707, null_frag, v128any, 0>;
79 // Load count to block boundary.
81 def LCBB : InstRXE<0xE727, (outs GR32:$R1),
82 (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
83 "lcbb\t$R1, $XBD2, $M3", []>;
85 // Load with length. The number of loaded bytes is only known at run time.
86 def VLL : BinaryVRSb<"vll", 0xE737, null_frag, 0>;
89 def VLM : LoadMultipleVRSa<"vlm", 0xE736>;
92 def VLREPB : UnaryVRX<"vlrepb", 0xE705, null_frag, v128b, 1, 0>;
93 def VLREPH : UnaryVRX<"vlreph", 0xE705, null_frag, v128h, 2, 1>;
94 def VLREPF : UnaryVRX<"vlrepf", 0xE705, null_frag, v128f, 4, 2>;
95 def VLREPG : UnaryVRX<"vlrepg", 0xE705, null_frag, v128g, 8, 3>;
97 // Load logical element and zero.
98 def VLLEZB : UnaryVRX<"vllezb", 0xE704, null_frag, v128b, 1, 0>;
99 def VLLEZH : UnaryVRX<"vllezh", 0xE704, null_frag, v128h, 2, 1>;
100 def VLLEZF : UnaryVRX<"vllezf", 0xE704, null_frag, v128f, 4, 2>;
101 def VLLEZG : UnaryVRX<"vllezg", 0xE704, null_frag, v128g, 8, 3>;
104 def VLEB : TernaryVRX<"vleb", 0xE700, null_frag, v128b, v128b, 1, imm32zx4>;
105 def VLEH : TernaryVRX<"vleh", 0xE701, null_frag, v128h, v128h, 2, imm32zx3>;
106 def VLEF : TernaryVRX<"vlef", 0xE703, null_frag, v128f, v128f, 4, imm32zx2>;
107 def VLEG : TernaryVRX<"vleg", 0xE702, null_frag, v128g, v128g, 8, imm32zx1>;
110 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>;
111 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>;
114 //===----------------------------------------------------------------------===//
116 //===----------------------------------------------------------------------===//
118 let Predicates = [FeatureVector] in {
120 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>;
122 // Store with length. The number of stored bytes is only known at run time.
123 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, null_frag, 0>;
126 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>;
129 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, null_frag, v128b, 1, imm32zx4>;
130 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, null_frag, v128h, 2, imm32zx3>;
131 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, null_frag, v128f, 4, imm32zx2>;
132 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, null_frag, v128g, 8, imm32zx1>;
135 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>;
136 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>;
139 //===----------------------------------------------------------------------===//
140 // Selects and permutes
141 //===----------------------------------------------------------------------===//
143 let Predicates = [FeatureVector] in {
145 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, null_frag, v128b, v128b, 0>;
146 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, null_frag, v128h, v128h, 1>;
147 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, null_frag, v128f, v128f, 2>;
148 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, null_frag, v128g, v128g, 3>;
151 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, null_frag, v128b, v128b, 0>;
152 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, null_frag, v128h, v128h, 1>;
153 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, null_frag, v128f, v128f, 2>;
154 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, null_frag, v128g, v128g, 3>;
157 def VPERM : TernaryVRRe<"vperm", 0xE78C, null_frag, v128b, v128b>;
159 // Permute doubleword immediate.
160 def VPDI : TernaryVRRc<"vpdi", 0xE784, null_frag, v128b, v128b>;
163 def VREPB : BinaryVRIc<"vrepb", 0xE74D, null_frag, v128b, v128b, 0>;
164 def VREPH : BinaryVRIc<"vreph", 0xE74D, null_frag, v128h, v128h, 1>;
165 def VREPF : BinaryVRIc<"vrepf", 0xE74D, null_frag, v128f, v128f, 2>;
166 def VREPG : BinaryVRIc<"vrepg", 0xE74D, null_frag, v128g, v128g, 3>;
169 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>;
172 //===----------------------------------------------------------------------===//
173 // Widening and narrowing
174 //===----------------------------------------------------------------------===//
176 let Predicates = [FeatureVector] in {
178 def VPKH : BinaryVRRc<"vpkh", 0xE794, null_frag, v128b, v128h, 1>;
179 def VPKF : BinaryVRRc<"vpkf", 0xE794, null_frag, v128h, v128f, 2>;
180 def VPKG : BinaryVRRc<"vpkg", 0xE794, null_frag, v128f, v128g, 3>;
183 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, null_frag, null_frag,
185 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, null_frag, null_frag,
187 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, null_frag, null_frag,
190 // Pack saturate logical.
191 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, null_frag, null_frag,
193 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, null_frag, null_frag,
195 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, null_frag, null_frag,
198 // Sign-extend to doubleword.
199 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, null_frag, v128g, v128b, 0>;
200 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, null_frag, v128g, v128h, 1>;
201 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, null_frag, v128g, v128f, 2>;
204 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, null_frag, v128h, v128b, 0>;
205 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, null_frag, v128f, v128h, 1>;
206 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, null_frag, v128g, v128f, 2>;
208 // Unpack logical high.
209 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, null_frag, v128h, v128b, 0>;
210 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, null_frag, v128f, v128h, 1>;
211 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, null_frag, v128g, v128f, 2>;
214 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, null_frag, v128h, v128b, 0>;
215 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, null_frag, v128f, v128h, 1>;
216 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, null_frag, v128g, v128f, 2>;
218 // Unpack logical low.
219 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, null_frag, v128h, v128b, 0>;
220 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, null_frag, v128f, v128h, 1>;
221 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, null_frag, v128g, v128f, 2>;
224 //===----------------------------------------------------------------------===//
225 // Integer arithmetic
226 //===----------------------------------------------------------------------===//
228 let Predicates = [FeatureVector] in {
230 def VAB : BinaryVRRc<"vab", 0xE7F3, null_frag, v128b, v128b, 0>;
231 def VAH : BinaryVRRc<"vah", 0xE7F3, null_frag, v128h, v128h, 1>;
232 def VAF : BinaryVRRc<"vaf", 0xE7F3, null_frag, v128f, v128f, 2>;
233 def VAG : BinaryVRRc<"vag", 0xE7F3, null_frag, v128g, v128g, 3>;
234 def VAQ : BinaryVRRc<"vaq", 0xE7F3, null_frag, v128q, v128q, 4>;
236 // Add compute carry.
237 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, null_frag, v128b, v128b, 0>;
238 def VACCH : BinaryVRRc<"vacch", 0xE7F1, null_frag, v128h, v128h, 1>;
239 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, null_frag, v128f, v128f, 2>;
240 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, null_frag, v128g, v128g, 3>;
241 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, null_frag, v128q, v128q, 4>;
244 def VACQ : TernaryVRRd<"vacq", 0xE7BB, null_frag, v128q, v128q, 4>;
246 // Add with carry compute carry.
247 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, null_frag, v128q, v128q, 4>;
250 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>;
252 // And with complement.
253 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>;
256 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, null_frag, v128b, v128b, 0>;
257 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, null_frag, v128h, v128h, 1>;
258 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, null_frag, v128f, v128f, 2>;
259 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, null_frag, v128g, v128g, 3>;
262 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, null_frag, v128b, v128b, 0>;
263 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, null_frag, v128h, v128h, 1>;
264 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, null_frag, v128f, v128f, 2>;
265 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, null_frag, v128g, v128g, 3>;
268 def VCKSM : BinaryVRRc<"vcksm", 0xE766, null_frag, v128any, v128any>;
270 // Count leading zeros.
271 def VCLZB : UnaryVRRa<"vclzb", 0xE753, null_frag, v128b, v128b, 0>;
272 def VCLZH : UnaryVRRa<"vclzh", 0xE753, null_frag, v128h, v128h, 1>;
273 def VCLZF : UnaryVRRa<"vclzf", 0xE753, null_frag, v128f, v128f, 2>;
274 def VCLZG : UnaryVRRa<"vclzg", 0xE753, null_frag, v128g, v128g, 3>;
276 // Count trailing zeros.
277 def VCTZB : UnaryVRRa<"vctzb", 0xE752, null_frag, v128b, v128b, 0>;
278 def VCTZH : UnaryVRRa<"vctzh", 0xE752, null_frag, v128h, v128h, 1>;
279 def VCTZF : UnaryVRRa<"vctzf", 0xE752, null_frag, v128f, v128f, 2>;
280 def VCTZG : UnaryVRRa<"vctzg", 0xE752, null_frag, v128g, v128g, 3>;
283 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>;
285 // Galois field multiply sum.
286 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, null_frag, v128b, v128b, 0>;
287 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, null_frag, v128h, v128h, 1>;
288 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, null_frag, v128f, v128f, 2>;
289 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, null_frag, v128g, v128g, 3>;
291 // Galois field multiply sum and accumulate.
292 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, null_frag, v128b, v128b, 0>;
293 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, null_frag, v128h, v128h, 1>;
294 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, null_frag, v128f, v128f, 2>;
295 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, null_frag, v128g, v128g, 3>;
298 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, null_frag, v128b, v128b, 0>;
299 def VLCH : UnaryVRRa<"vlch", 0xE7DE, null_frag, v128h, v128h, 1>;
300 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, null_frag, v128f, v128f, 2>;
301 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, null_frag, v128g, v128g, 3>;
304 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, null_frag, v128b, v128b, 0>;
305 def VLPH : UnaryVRRa<"vlph", 0xE7DF, null_frag, v128h, v128h, 1>;
306 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, null_frag, v128f, v128f, 2>;
307 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, null_frag, v128g, v128g, 3>;
310 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>;
311 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>;
312 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>;
313 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>;
316 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>;
317 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>;
318 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>;
319 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>;
322 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>;
323 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>;
324 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>;
325 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>;
328 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>;
329 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>;
330 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>;
331 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>;
333 // Multiply and add low.
334 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, null_frag, v128b, v128b, 0>;
335 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, null_frag, v128h, v128h, 1>;
336 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, null_frag, v128f, v128f, 2>;
338 // Multiply and add high.
339 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, null_frag, v128b, v128b, 0>;
340 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, null_frag, v128h, v128h, 1>;
341 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, null_frag, v128f, v128f, 2>;
343 // Multiply and add logical high.
344 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, null_frag, v128b, v128b, 0>;
345 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, null_frag, v128h, v128h, 1>;
346 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, null_frag, v128f, v128f, 2>;
348 // Multiply and add even.
349 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, null_frag, v128h, v128b, 0>;
350 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, null_frag, v128f, v128h, 1>;
351 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, null_frag, v128g, v128f, 2>;
353 // Multiply and add logical even.
354 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, null_frag, v128h, v128b, 0>;
355 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, null_frag, v128f, v128h, 1>;
356 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, null_frag, v128g, v128f, 2>;
358 // Multiply and add odd.
359 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, null_frag, v128h, v128b, 0>;
360 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, null_frag, v128f, v128h, 1>;
361 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, null_frag, v128g, v128f, 2>;
363 // Multiply and add logical odd.
364 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, null_frag, v128h, v128b, 0>;
365 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, null_frag, v128f, v128h, 1>;
366 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, null_frag, v128g, v128f, 2>;
369 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, null_frag, v128b, v128b, 0>;
370 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, null_frag, v128h, v128h, 1>;
371 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, null_frag, v128f, v128f, 2>;
373 // Multiply logical high.
374 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, null_frag, v128b, v128b, 0>;
375 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, null_frag, v128h, v128h, 1>;
376 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, null_frag, v128f, v128f, 2>;
379 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, null_frag, v128b, v128b, 0>;
380 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, null_frag, v128h, v128h, 1>;
381 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, null_frag, v128f, v128f, 2>;
384 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, null_frag, v128h, v128b, 0>;
385 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, null_frag, v128f, v128h, 1>;
386 def VMEF : BinaryVRRc<"vmef", 0xE7A6, null_frag, v128g, v128f, 2>;
388 // Multiply logical even.
389 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, null_frag, v128h, v128b, 0>;
390 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, null_frag, v128f, v128h, 1>;
391 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, null_frag, v128g, v128f, 2>;
394 def VMOB : BinaryVRRc<"vmob", 0xE7A7, null_frag, v128h, v128b, 0>;
395 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, null_frag, v128f, v128h, 1>;
396 def VMOF : BinaryVRRc<"vmof", 0xE7A7, null_frag, v128g, v128f, 2>;
398 // Multiply logical odd.
399 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, null_frag, v128h, v128b, 0>;
400 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, null_frag, v128f, v128h, 1>;
401 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, null_frag, v128g, v128f, 2>;
404 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>;
407 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>;
410 def VPOPCT : BinaryVRRa<"vpopct", 0xE750>;
412 // Element rotate left logical (with vector shift amount).
413 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, null_frag, v128b, v128b, 0>;
414 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, null_frag, v128h, v128h, 1>;
415 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, null_frag, v128f, v128f, 2>;
416 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, null_frag, v128g, v128g, 3>;
418 // Element rotate left logical (with scalar shift amount).
419 def VERLLB : BinaryVRSa<"verllb", 0xE733, null_frag, v128b, v128b, 0>;
420 def VERLLH : BinaryVRSa<"verllh", 0xE733, null_frag, v128h, v128h, 1>;
421 def VERLLF : BinaryVRSa<"verllf", 0xE733, null_frag, v128f, v128f, 2>;
422 def VERLLG : BinaryVRSa<"verllg", 0xE733, null_frag, v128g, v128g, 3>;
424 // Element rotate and insert under mask.
425 def VERIMB : QuaternaryVRId<"verimb", 0xE772, null_frag, v128b, v128b, 0>;
426 def VERIMH : QuaternaryVRId<"verimh", 0xE772, null_frag, v128h, v128h, 1>;
427 def VERIMF : QuaternaryVRId<"verimf", 0xE772, null_frag, v128f, v128f, 2>;
428 def VERIMG : QuaternaryVRId<"verimg", 0xE772, null_frag, v128g, v128g, 3>;
430 // Element shift left (with vector shift amount).
431 def VESLVB : BinaryVRRc<"veslvb", 0xE770, null_frag, v128b, v128b, 0>;
432 def VESLVH : BinaryVRRc<"veslvh", 0xE770, null_frag, v128h, v128h, 1>;
433 def VESLVF : BinaryVRRc<"veslvf", 0xE770, null_frag, v128f, v128f, 2>;
434 def VESLVG : BinaryVRRc<"veslvg", 0xE770, null_frag, v128g, v128g, 3>;
436 // Element shift left (with scalar shift amount).
437 def VESLB : BinaryVRSa<"veslb", 0xE730, null_frag, v128b, v128b, 0>;
438 def VESLH : BinaryVRSa<"veslh", 0xE730, null_frag, v128h, v128h, 1>;
439 def VESLF : BinaryVRSa<"veslf", 0xE730, null_frag, v128f, v128f, 2>;
440 def VESLG : BinaryVRSa<"veslg", 0xE730, null_frag, v128g, v128g, 3>;
442 // Element shift right arithmetic (with vector shift amount).
443 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, null_frag, v128b, v128b, 0>;
444 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, null_frag, v128h, v128h, 1>;
445 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, null_frag, v128f, v128f, 2>;
446 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, null_frag, v128g, v128g, 3>;
448 // Element shift right arithmetic (with scalar shift amount).
449 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, null_frag, v128b, v128b, 0>;
450 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, null_frag, v128h, v128h, 1>;
451 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, null_frag, v128f, v128f, 2>;
452 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, null_frag, v128g, v128g, 3>;
454 // Element shift right logical (with vector shift amount).
455 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, null_frag, v128b, v128b, 0>;
456 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, null_frag, v128h, v128h, 1>;
457 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, null_frag, v128f, v128f, 2>;
458 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, null_frag, v128g, v128g, 3>;
460 // Element shift right logical (with scalar shift amount).
461 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, null_frag, v128b, v128b, 0>;
462 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, null_frag, v128h, v128h, 1>;
463 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, null_frag, v128f, v128f, 2>;
464 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, null_frag, v128g, v128g, 3>;
467 def VSL : BinaryVRRc<"vsl", 0xE774, null_frag, v128b, v128b>;
469 // Shift left by byte.
470 def VSLB : BinaryVRRc<"vslb", 0xE775, null_frag, v128b, v128b>;
472 // Shift left double by byte.
473 def VSLDB : TernaryVRId<"vsldb", 0xE777, null_frag, v128b, v128b, 0>;
475 // Shift right arithmetic.
476 def VSRA : BinaryVRRc<"vsra", 0xE77E, null_frag, v128b, v128b>;
478 // Shift right arithmetic by byte.
479 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, null_frag, v128b, v128b>;
481 // Shift right logical.
482 def VSRL : BinaryVRRc<"vsrl", 0xE77C, null_frag, v128b, v128b>;
484 // Shift right logical by byte.
485 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, null_frag, v128b, v128b>;
488 def VSB : BinaryVRRc<"vsb", 0xE7F7, null_frag, v128b, v128b, 0>;
489 def VSH : BinaryVRRc<"vsh", 0xE7F7, null_frag, v128h, v128h, 1>;
490 def VSF : BinaryVRRc<"vsf", 0xE7F7, null_frag, v128f, v128f, 2>;
491 def VSG : BinaryVRRc<"vsg", 0xE7F7, null_frag, v128g, v128g, 3>;
492 def VSQ : BinaryVRRc<"vsq", 0xE7F7, null_frag, v128q, v128q, 4>;
494 // Subtract compute borrow indication.
495 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, null_frag, v128b, v128b, 0>;
496 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, null_frag, v128h, v128h, 1>;
497 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, null_frag, v128f, v128f, 2>;
498 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, null_frag, v128g, v128g, 3>;
499 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, null_frag, v128q, v128q, 4>;
501 // Subtract with borrow indication.
502 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, null_frag, v128q, v128q, 4>;
504 // Subtract with borrow compute borrow indication.
505 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, null_frag, v128q, v128q, 4>;
507 // Sum across doubleword.
508 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, null_frag, v128g, v128h, 1>;
509 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, null_frag, v128g, v128f, 2>;
511 // Sum across quadword.
512 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, null_frag, v128q, v128f, 2>;
513 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, null_frag, v128q, v128g, 3>;
516 def VSUMB : BinaryVRRc<"vsumb", 0xE764, null_frag, v128f, v128b, 0>;
517 def VSUMH : BinaryVRRc<"vsumh", 0xE764, null_frag, v128f, v128h, 1>;
520 //===----------------------------------------------------------------------===//
521 // Integer comparison
522 //===----------------------------------------------------------------------===//
524 let Predicates = [FeatureVector] in {
527 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>;
528 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>;
529 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>;
530 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>;
533 // Element compare logical.
535 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>;
536 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>;
537 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>;
538 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>;
542 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, null_frag, null_frag,
544 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, null_frag, null_frag,
546 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, null_frag, null_frag,
548 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, null_frag, null_frag,
552 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, null_frag, null_frag,
554 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, null_frag, null_frag,
556 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, null_frag, null_frag,
558 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, null_frag, null_frag,
561 // Compare high logical.
562 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, null_frag, null_frag,
564 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, null_frag, null_frag,
566 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, null_frag, null_frag,
568 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, null_frag, null_frag,
573 def VTM : CompareVRRa<"vtm", 0xE7D8, null_frag, v128any, 0>;
576 //===----------------------------------------------------------------------===//
577 // Floating-point arithmetic
578 //===----------------------------------------------------------------------===//
580 let Predicates = [FeatureVector] in {
582 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, null_frag, v128db, v128db, 3, 0>;
583 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, null_frag, v64db, v64db, 3, 8>;
585 // Convert from fixed 64-bit.
586 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>;
587 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>;
589 // Convert from logical 64-bit.
590 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>;
591 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>;
593 // Convert to fixed 64-bit.
594 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>;
595 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>;
597 // Convert to logical 64-bit.
598 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>;
599 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>;
602 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, null_frag, v128db, v128db, 3, 0>;
603 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, null_frag, v64db, v64db, 3, 8>;
606 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, null_frag, v128db, v128db, 3, 0>;
607 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>;
610 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, null_frag, v128db, v128eb, 2, 0>;
611 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, null_frag, v64db, v32eb, 2, 8>;
614 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128eb, v128db, 3, 0>;
615 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32eb, v64db, 3, 8>;
618 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, null_frag, v128db, v128db, 3, 0>;
619 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, null_frag, v64db, v64db, 3, 8>;
622 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, null_frag, v128db, v128db, 0, 3>;
623 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, null_frag, v64db, v64db, 8, 3>;
625 // Multiply and subtract.
626 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, null_frag, v128db, v128db, 0, 3>;
627 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, null_frag, v64db, v64db, 8, 3>;
630 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 0>;
631 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 0>;
634 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 1>;
635 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 1>;
638 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 2>;
639 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 2>;
642 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, null_frag, v128db, v128db, 3, 0>;
643 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, null_frag, v64db, v64db, 3, 8>;
646 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, null_frag, v128db, v128db, 3, 0>;
647 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, null_frag, v64db, v64db, 3, 8>;
649 // Test data class immediate.
651 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, null_frag, v128g, v128db, 3, 0>;
652 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>;
656 //===----------------------------------------------------------------------===//
657 // Floating-point comparison
658 //===----------------------------------------------------------------------===//
660 let Predicates = [FeatureVector] in {
663 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, null_frag, v64db, 3>;
665 // Compare and signal scalar.
667 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>;
670 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, null_frag, null_frag,
671 v128g, v128db, 3, 0>;
672 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag,
676 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, null_frag, null_frag,
677 v128g, v128db, 3, 0>;
678 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag,
681 // Compare high or equal.
682 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, null_frag, null_frag,
683 v128g, v128db, 3, 0>;
684 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag,
688 //===----------------------------------------------------------------------===//
689 // String instructions
690 //===----------------------------------------------------------------------===//
692 let Predicates = [FeatureVector] in {
693 defm VFAEB : TernaryVRRbSPair<"vfaeb", 0xE782, null_frag, null_frag,
695 defm VFAEH : TernaryVRRbSPair<"vfaeh", 0xE782, null_frag, null_frag,
697 defm VFAEF : TernaryVRRbSPair<"vfaef", 0xE782, null_frag, null_frag,
699 defm VFAEZB : TernaryVRRbSPair<"vfaezb", 0xE782, null_frag, null_frag,
701 defm VFAEZH : TernaryVRRbSPair<"vfaezh", 0xE782, null_frag, null_frag,
703 defm VFAEZF : TernaryVRRbSPair<"vfaezf", 0xE782, null_frag, null_frag,
706 defm VFEEB : BinaryVRRbSPair<"vfeeb", 0xE780, null_frag, null_frag,
707 v128b, v128b, 0, 0, 1>;
708 defm VFEEH : BinaryVRRbSPair<"vfeeh", 0xE780, null_frag, null_frag,
709 v128h, v128h, 1, 0, 1>;
710 defm VFEEF : BinaryVRRbSPair<"vfeef", 0xE780, null_frag, null_frag,
711 v128f, v128f, 2, 0, 1>;
712 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, null_frag, null_frag,
713 v128b, v128b, 0, 2, 3>;
714 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, null_frag, null_frag,
715 v128h, v128h, 1, 2, 3>;
716 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, null_frag, null_frag,
717 v128f, v128f, 2, 2, 3>;
719 defm VFENEB : BinaryVRRbSPair<"vfeneb", 0xE781, null_frag, null_frag,
720 v128b, v128b, 0, 0, 1>;
721 defm VFENEH : BinaryVRRbSPair<"vfeneh", 0xE781, null_frag, null_frag,
722 v128h, v128h, 1, 0, 1>;
723 defm VFENEF : BinaryVRRbSPair<"vfenef", 0xE781, null_frag, null_frag,
724 v128f, v128f, 2, 0, 1>;
725 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, null_frag, null_frag,
726 v128b, v128b, 0, 2, 3>;
727 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, null_frag, null_frag,
728 v128h, v128h, 1, 2, 3>;
729 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, null_frag, null_frag,
730 v128f, v128f, 2, 2, 3>;
732 defm VISTRB : UnaryVRRaSPair<"vistrb", 0xE75C, null_frag, null_frag,
734 defm VISTRH : UnaryVRRaSPair<"vistrh", 0xE75C, null_frag, null_frag,
736 defm VISTRF : UnaryVRRaSPair<"vistrf", 0xE75C, null_frag, null_frag,
739 defm VSTRCB : QuaternaryVRRdSPair<"vstrcb", 0xE78A, null_frag, null_frag,
741 defm VSTRCH : QuaternaryVRRdSPair<"vstrch", 0xE78A, null_frag, null_frag,
743 defm VSTRCF : QuaternaryVRRdSPair<"vstrcf", 0xE78A, null_frag, null_frag,
745 defm VSTRCZB : QuaternaryVRRdSPair<"vstrczb", 0xE78A, null_frag, null_frag,
747 defm VSTRCZH : QuaternaryVRRdSPair<"vstrczh", 0xE78A, null_frag, null_frag,
749 defm VSTRCZF : QuaternaryVRRdSPair<"vstrczf", 0xE78A, null_frag, null_frag,